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0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
0004 *
0005 * Copyright (C) 2015 Atmel,
0006 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
0007 */
0008
0009 #include <dt-bindings/dma/at91.h>
0010 #include <dt-bindings/interrupt-controller/irq.h>
0011 #include <dt-bindings/clock/at91.h>
0012 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
0013
0014 / {
0015 #address-cells = <1>;
0016 #size-cells = <1>;
0017 model = "Atmel SAMA5D2 family SoC";
0018 compatible = "atmel,sama5d2";
0019 interrupt-parent = <&aic>;
0020
0021 aliases {
0022 serial0 = &uart1;
0023 serial1 = &uart3;
0024 };
0025
0026 cpus {
0027 #address-cells = <1>;
0028 #size-cells = <0>;
0029
0030 cpu@0 {
0031 device_type = "cpu";
0032 compatible = "arm,cortex-a5";
0033 reg = <0>;
0034 next-level-cache = <&L2>;
0035 };
0036 };
0037
0038 pmu {
0039 compatible = "arm,cortex-a5-pmu";
0040 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
0041 };
0042
0043 etb@740000 {
0044 compatible = "arm,coresight-etb10", "arm,primecell";
0045 reg = <0x740000 0x1000>;
0046
0047 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
0048 clock-names = "apb_pclk";
0049
0050 in-ports {
0051 port {
0052 etb_in: endpoint {
0053 remote-endpoint = <&etm_out>;
0054 };
0055 };
0056 };
0057 };
0058
0059 etm@73c000 {
0060 compatible = "arm,coresight-etm3x", "arm,primecell";
0061 reg = <0x73c000 0x1000>;
0062
0063 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
0064 clock-names = "apb_pclk";
0065
0066 out-ports {
0067 port {
0068 etm_out: endpoint {
0069 remote-endpoint = <&etb_in>;
0070 };
0071 };
0072 };
0073 };
0074
0075 memory@20000000 {
0076 device_type = "memory";
0077 reg = <0x20000000 0x20000000>;
0078 };
0079
0080 clocks {
0081 slow_xtal: slow_xtal {
0082 compatible = "fixed-clock";
0083 #clock-cells = <0>;
0084 clock-frequency = <0>;
0085 };
0086
0087 main_xtal: main_xtal {
0088 compatible = "fixed-clock";
0089 #clock-cells = <0>;
0090 clock-frequency = <0>;
0091 };
0092 };
0093
0094 ns_sram: sram@200000 {
0095 compatible = "mmio-sram";
0096 reg = <0x00200000 0x20000>;
0097 #address-cells = <1>;
0098 #size-cells = <1>;
0099 ranges = <0 0x00200000 0x20000>;
0100 };
0101
0102 resistive_touch: resistive-touch {
0103 compatible = "resistive-adc-touch";
0104 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>,
0105 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>,
0106 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>;
0107 io-channel-names = "x", "y", "pressure";
0108 touchscreen-min-pressure = <50000>;
0109 status = "disabled";
0110 };
0111
0112 ahb {
0113 compatible = "simple-bus";
0114 #address-cells = <1>;
0115 #size-cells = <1>;
0116 ranges;
0117
0118 nfc_sram: sram@100000 {
0119 compatible = "mmio-sram";
0120 no-memory-wc;
0121 reg = <0x00100000 0x2400>;
0122 #address-cells = <1>;
0123 #size-cells = <1>;
0124 ranges = <0 0x00100000 0x2400>;
0125
0126 };
0127
0128 usb0: gadget@300000 {
0129 compatible = "atmel,sama5d3-udc";
0130 reg = <0x00300000 0x100000
0131 0xfc02c000 0x400>;
0132 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
0133 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
0134 clock-names = "pclk", "hclk";
0135 status = "disabled";
0136 };
0137
0138 usb1: ohci@400000 {
0139 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
0140 reg = <0x00400000 0x100000>;
0141 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
0142 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>;
0143 clock-names = "ohci_clk", "hclk", "uhpck";
0144 status = "disabled";
0145 };
0146
0147 usb2: ehci@500000 {
0148 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
0149 reg = <0x00500000 0x100000>;
0150 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
0151 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>;
0152 clock-names = "usb_clk", "ehci_clk";
0153 status = "disabled";
0154 };
0155
0156 L2: cache-controller@a00000 {
0157 compatible = "arm,pl310-cache";
0158 reg = <0x00a00000 0x1000>;
0159 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
0160 cache-unified;
0161 cache-level = <2>;
0162 };
0163
0164 ebi: ebi@10000000 {
0165 compatible = "atmel,sama5d3-ebi";
0166 #address-cells = <2>;
0167 #size-cells = <1>;
0168 atmel,smc = <&hsmc>;
0169 reg = <0x10000000 0x10000000
0170 0x60000000 0x30000000>;
0171 ranges = <0x0 0x0 0x10000000 0x10000000
0172 0x1 0x0 0x60000000 0x10000000
0173 0x2 0x0 0x70000000 0x10000000
0174 0x3 0x0 0x80000000 0x10000000>;
0175 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
0176 status = "disabled";
0177
0178 nand_controller: nand-controller {
0179 compatible = "atmel,sama5d3-nand-controller";
0180 atmel,nfc-sram = <&nfc_sram>;
0181 atmel,nfc-io = <&nfc_io>;
0182 ecc-engine = <&pmecc>;
0183 #address-cells = <2>;
0184 #size-cells = <1>;
0185 ranges;
0186 status = "disabled";
0187 };
0188 };
0189
0190 sdmmc0: sdio-host@a0000000 {
0191 compatible = "atmel,sama5d2-sdhci";
0192 reg = <0xa0000000 0x300>;
0193 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
0194 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
0195 clock-names = "hclock", "multclk", "baseclk";
0196 assigned-clocks = <&pmc PMC_TYPE_GCK 31>;
0197 assigned-clock-rates = <480000000>;
0198 status = "disabled";
0199 };
0200
0201 sdmmc1: sdio-host@b0000000 {
0202 compatible = "atmel,sama5d2-sdhci";
0203 reg = <0xb0000000 0x300>;
0204 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
0205 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
0206 clock-names = "hclock", "multclk", "baseclk";
0207 assigned-clocks = <&pmc PMC_TYPE_GCK 32>;
0208 assigned-clock-rates = <480000000>;
0209 status = "disabled";
0210 };
0211
0212 nfc_io: nfc-io@c0000000 {
0213 compatible = "atmel,sama5d3-nfc-io", "syscon";
0214 reg = <0xc0000000 0x8000000>;
0215 };
0216
0217 apb {
0218 compatible = "simple-bus";
0219 #address-cells = <1>;
0220 #size-cells = <1>;
0221 ranges;
0222
0223 hlcdc: hlcdc@f0000000 {
0224 compatible = "atmel,sama5d2-hlcdc";
0225 reg = <0xf0000000 0x2000>;
0226 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
0227 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
0228 clock-names = "periph_clk","sys_clk", "slow_clk";
0229 status = "disabled";
0230
0231 hlcdc-display-controller {
0232 compatible = "atmel,hlcdc-display-controller";
0233 #address-cells = <1>;
0234 #size-cells = <0>;
0235
0236 port@0 {
0237 #address-cells = <1>;
0238 #size-cells = <0>;
0239 reg = <0>;
0240 };
0241 };
0242
0243 hlcdc_pwm: hlcdc-pwm {
0244 compatible = "atmel,hlcdc-pwm";
0245 #pwm-cells = <3>;
0246 };
0247 };
0248
0249 isc: isc@f0008000 {
0250 compatible = "atmel,sama5d2-isc";
0251 reg = <0xf0008000 0x4000>;
0252 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
0253 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>;
0254 clock-names = "hclock", "iscck", "gck";
0255 #clock-cells = <0>;
0256 clock-output-names = "isc-mck";
0257 status = "disabled";
0258 };
0259
0260 ramc0: ramc@f000c000 {
0261 compatible = "atmel,sama5d3-ddramc";
0262 reg = <0xf000c000 0x200>;
0263 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>;
0264 clock-names = "ddrck", "mpddr";
0265 };
0266
0267 dma0: dma-controller@f0010000 {
0268 compatible = "atmel,sama5d4-dma";
0269 reg = <0xf0010000 0x1000>;
0270 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
0271 #dma-cells = <1>;
0272 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
0273 clock-names = "dma_clk";
0274 };
0275
0276 /* Place dma1 here despite its address */
0277 dma1: dma-controller@f0004000 {
0278 compatible = "atmel,sama5d4-dma";
0279 reg = <0xf0004000 0x1000>;
0280 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
0281 #dma-cells = <1>;
0282 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
0283 clock-names = "dma_clk";
0284 };
0285
0286 pmc: pmc@f0014000 {
0287 compatible = "atmel,sama5d2-pmc", "syscon";
0288 reg = <0xf0014000 0x160>;
0289 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
0290 #clock-cells = <2>;
0291 clocks = <&clk32k>, <&main_xtal>;
0292 clock-names = "slow_clk", "main_xtal";
0293 };
0294
0295 qspi0: spi@f0020000 {
0296 compatible = "atmel,sama5d2-qspi";
0297 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
0298 reg-names = "qspi_base", "qspi_mmap";
0299 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
0300 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
0301 clock-names = "pclk";
0302 #address-cells = <1>;
0303 #size-cells = <0>;
0304 status = "disabled";
0305 };
0306
0307 qspi1: spi@f0024000 {
0308 compatible = "atmel,sama5d2-qspi";
0309 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
0310 reg-names = "qspi_base", "qspi_mmap";
0311 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
0312 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
0313 clock-names = "pclk";
0314 #address-cells = <1>;
0315 #size-cells = <0>;
0316 status = "disabled";
0317 };
0318
0319 sha: crypto@f0028000 {
0320 compatible = "atmel,at91sam9g46-sha";
0321 reg = <0xf0028000 0x100>;
0322 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
0323 dmas = <&dma0
0324 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0325 AT91_XDMAC_DT_PERID(30))>;
0326 dma-names = "tx";
0327 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
0328 clock-names = "sha_clk";
0329 };
0330
0331 aes: crypto@f002c000 {
0332 compatible = "atmel,at91sam9g46-aes";
0333 reg = <0xf002c000 0x100>;
0334 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
0335 dmas = <&dma0
0336 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0337 AT91_XDMAC_DT_PERID(26))>,
0338 <&dma0
0339 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0340 AT91_XDMAC_DT_PERID(27))>;
0341 dma-names = "tx", "rx";
0342 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
0343 clock-names = "aes_clk";
0344 };
0345
0346 spi0: spi@f8000000 {
0347 compatible = "atmel,at91rm9200-spi";
0348 reg = <0xf8000000 0x100>;
0349 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
0350 dmas = <&dma0
0351 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0352 AT91_XDMAC_DT_PERID(6))>,
0353 <&dma0
0354 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0355 AT91_XDMAC_DT_PERID(7))>;
0356 dma-names = "tx", "rx";
0357 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
0358 clock-names = "spi_clk";
0359 atmel,fifo-size = <16>;
0360 #address-cells = <1>;
0361 #size-cells = <0>;
0362 status = "disabled";
0363 };
0364
0365 ssc0: ssc@f8004000 {
0366 compatible = "atmel,at91sam9g45-ssc";
0367 reg = <0xf8004000 0x4000>;
0368 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
0369 dmas = <&dma0
0370 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0371 AT91_XDMAC_DT_PERID(21))>,
0372 <&dma0
0373 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0374 AT91_XDMAC_DT_PERID(22))>;
0375 dma-names = "tx", "rx";
0376 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
0377 clock-names = "pclk";
0378 status = "disabled";
0379 };
0380
0381 macb0: ethernet@f8008000 {
0382 compatible = "atmel,sama5d2-gem";
0383 reg = <0xf8008000 0x1000>;
0384 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
0385 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
0386 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
0387 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>;
0388 clock-names = "hclk", "pclk";
0389 status = "disabled";
0390 };
0391
0392 tcb0: timer@f800c000 {
0393 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
0394 #address-cells = <1>;
0395 #size-cells = <0>;
0396 reg = <0xf800c000 0x100>;
0397 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
0398 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>;
0399 clock-names = "t0_clk", "gclk", "slow_clk";
0400 };
0401
0402 tcb1: timer@f8010000 {
0403 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
0404 #address-cells = <1>;
0405 #size-cells = <0>;
0406 reg = <0xf8010000 0x100>;
0407 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
0408 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>;
0409 clock-names = "t0_clk", "gclk", "slow_clk";
0410 };
0411
0412 hsmc: hsmc@f8014000 {
0413 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
0414 reg = <0xf8014000 0x1000>;
0415 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
0416 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
0417 #address-cells = <1>;
0418 #size-cells = <1>;
0419 ranges;
0420
0421 pmecc: ecc-engine@f8014070 {
0422 compatible = "atmel,sama5d2-pmecc";
0423 reg = <0xf8014070 0x490>,
0424 <0xf8014500 0x200>;
0425 };
0426 };
0427
0428 pdmic: pdmic@f8018000 {
0429 compatible = "atmel,sama5d2-pdmic";
0430 reg = <0xf8018000 0x124>;
0431 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
0432 dmas = <&dma0
0433 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
0434 | AT91_XDMAC_DT_PERID(50))>;
0435 dma-names = "rx";
0436 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>;
0437 clock-names = "pclk", "gclk";
0438 status = "disabled";
0439 };
0440
0441 uart0: serial@f801c000 {
0442 compatible = "atmel,at91sam9260-usart";
0443 reg = <0xf801c000 0x100>;
0444 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
0445 dmas = <&dma0
0446 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0447 AT91_XDMAC_DT_PERID(35))>,
0448 <&dma0
0449 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0450 AT91_XDMAC_DT_PERID(36))>;
0451 dma-names = "tx", "rx";
0452 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
0453 clock-names = "usart";
0454 status = "disabled";
0455 };
0456
0457 uart1: serial@f8020000 {
0458 compatible = "atmel,at91sam9260-usart";
0459 reg = <0xf8020000 0x100>;
0460 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
0461 dmas = <&dma0
0462 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0463 AT91_XDMAC_DT_PERID(37))>,
0464 <&dma0
0465 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0466 AT91_XDMAC_DT_PERID(38))>;
0467 dma-names = "tx", "rx";
0468 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
0469 clock-names = "usart";
0470 status = "disabled";
0471 };
0472
0473 uart2: serial@f8024000 {
0474 compatible = "atmel,at91sam9260-usart";
0475 reg = <0xf8024000 0x100>;
0476 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
0477 dmas = <&dma0
0478 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0479 AT91_XDMAC_DT_PERID(39))>,
0480 <&dma0
0481 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0482 AT91_XDMAC_DT_PERID(40))>;
0483 dma-names = "tx", "rx";
0484 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
0485 clock-names = "usart";
0486 status = "disabled";
0487 };
0488
0489 i2c0: i2c@f8028000 {
0490 compatible = "atmel,sama5d2-i2c";
0491 reg = <0xf8028000 0x100>;
0492 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
0493 dmas = <&dma0
0494 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0495 AT91_XDMAC_DT_PERID(0))>,
0496 <&dma0
0497 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0498 AT91_XDMAC_DT_PERID(1))>;
0499 dma-names = "tx", "rx";
0500 #address-cells = <1>;
0501 #size-cells = <0>;
0502 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
0503 atmel,fifo-size = <16>;
0504 status = "disabled";
0505 };
0506
0507 pwm0: pwm@f802c000 {
0508 compatible = "atmel,sama5d2-pwm";
0509 reg = <0xf802c000 0x4000>;
0510 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
0511 #pwm-cells = <3>;
0512 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
0513 status = "disabled";
0514 };
0515
0516 sfr: sfr@f8030000 {
0517 compatible = "atmel,sama5d2-sfr", "syscon";
0518 reg = <0xf8030000 0x98>;
0519 };
0520
0521 flx0: flexcom@f8034000 {
0522 compatible = "atmel,sama5d2-flexcom";
0523 reg = <0xf8034000 0x200>;
0524 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
0525 #address-cells = <1>;
0526 #size-cells = <1>;
0527 ranges = <0x0 0xf8034000 0x800>;
0528 status = "disabled";
0529
0530 uart5: serial@200 {
0531 compatible = "atmel,at91sam9260-usart";
0532 reg = <0x200 0x200>;
0533 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
0534 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
0535 clock-names = "usart";
0536 dmas = <&dma0
0537 (AT91_XDMAC_DT_MEM_IF(0) |
0538 AT91_XDMAC_DT_PER_IF(1) |
0539 AT91_XDMAC_DT_PERID(11))>,
0540 <&dma0
0541 (AT91_XDMAC_DT_MEM_IF(0) |
0542 AT91_XDMAC_DT_PER_IF(1) |
0543 AT91_XDMAC_DT_PERID(12))>;
0544 dma-names = "tx", "rx";
0545 atmel,fifo-size = <32>;
0546 status = "disabled";
0547 };
0548
0549 spi2: spi@400 {
0550 compatible = "atmel,at91rm9200-spi";
0551 reg = <0x400 0x200>;
0552 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
0553 #address-cells = <1>;
0554 #size-cells = <0>;
0555 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
0556 clock-names = "spi_clk";
0557 dmas = <&dma0
0558 (AT91_XDMAC_DT_MEM_IF(0) |
0559 AT91_XDMAC_DT_PER_IF(1) |
0560 AT91_XDMAC_DT_PERID(11))>,
0561 <&dma0
0562 (AT91_XDMAC_DT_MEM_IF(0) |
0563 AT91_XDMAC_DT_PER_IF(1) |
0564 AT91_XDMAC_DT_PERID(12))>;
0565 dma-names = "tx", "rx";
0566 atmel,fifo-size = <16>;
0567 status = "disabled";
0568 };
0569
0570 i2c2: i2c@600 {
0571 compatible = "atmel,sama5d2-i2c";
0572 reg = <0x600 0x200>;
0573 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
0574 #address-cells = <1>;
0575 #size-cells = <0>;
0576 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
0577 dmas = <&dma0
0578 (AT91_XDMAC_DT_MEM_IF(0) |
0579 AT91_XDMAC_DT_PER_IF(1) |
0580 AT91_XDMAC_DT_PERID(11))>,
0581 <&dma0
0582 (AT91_XDMAC_DT_MEM_IF(0) |
0583 AT91_XDMAC_DT_PER_IF(1) |
0584 AT91_XDMAC_DT_PERID(12))>;
0585 dma-names = "tx", "rx";
0586 atmel,fifo-size = <16>;
0587 status = "disabled";
0588 };
0589 };
0590
0591 flx1: flexcom@f8038000 {
0592 compatible = "atmel,sama5d2-flexcom";
0593 reg = <0xf8038000 0x200>;
0594 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
0595 #address-cells = <1>;
0596 #size-cells = <1>;
0597 ranges = <0x0 0xf8038000 0x800>;
0598 status = "disabled";
0599
0600 uart6: serial@200 {
0601 compatible = "atmel,at91sam9260-usart";
0602 reg = <0x200 0x200>;
0603 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
0604 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
0605 clock-names = "usart";
0606 dmas = <&dma0
0607 (AT91_XDMAC_DT_MEM_IF(0) |
0608 AT91_XDMAC_DT_PER_IF(1) |
0609 AT91_XDMAC_DT_PERID(13))>,
0610 <&dma0
0611 (AT91_XDMAC_DT_MEM_IF(0) |
0612 AT91_XDMAC_DT_PER_IF(1) |
0613 AT91_XDMAC_DT_PERID(14))>;
0614 dma-names = "tx", "rx";
0615 atmel,fifo-size = <32>;
0616 status = "disabled";
0617 };
0618
0619 spi3: spi@400 {
0620 compatible = "atmel,at91rm9200-spi";
0621 reg = <0x400 0x200>;
0622 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
0623 #address-cells = <1>;
0624 #size-cells = <0>;
0625 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
0626 clock-names = "spi_clk";
0627 dmas = <&dma0
0628 (AT91_XDMAC_DT_MEM_IF(0) |
0629 AT91_XDMAC_DT_PER_IF(1) |
0630 AT91_XDMAC_DT_PERID(13))>,
0631 <&dma0
0632 (AT91_XDMAC_DT_MEM_IF(0) |
0633 AT91_XDMAC_DT_PER_IF(1) |
0634 AT91_XDMAC_DT_PERID(14))>;
0635 dma-names = "tx", "rx";
0636 atmel,fifo-size = <16>;
0637 status = "disabled";
0638 };
0639
0640 i2c3: i2c@600 {
0641 compatible = "atmel,sama5d2-i2c";
0642 reg = <0x600 0x200>;
0643 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
0644 #address-cells = <1>;
0645 #size-cells = <0>;
0646 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
0647 dmas = <&dma0
0648 (AT91_XDMAC_DT_MEM_IF(0) |
0649 AT91_XDMAC_DT_PER_IF(1) |
0650 AT91_XDMAC_DT_PERID(13))>,
0651 <&dma0
0652 (AT91_XDMAC_DT_MEM_IF(0) |
0653 AT91_XDMAC_DT_PER_IF(1) |
0654 AT91_XDMAC_DT_PERID(14))>;
0655 dma-names = "tx", "rx";
0656 atmel,fifo-size = <16>;
0657 status = "disabled";
0658 };
0659 };
0660
0661 securam: sram@f8044000 {
0662 compatible = "atmel,sama5d2-securam", "mmio-sram";
0663 reg = <0xf8044000 0x1420>;
0664 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>;
0665 #address-cells = <1>;
0666 #size-cells = <1>;
0667 no-memory-wc;
0668 ranges = <0 0xf8044000 0x1420>;
0669 };
0670
0671 reset_controller: reset-controller@f8048000 {
0672 compatible = "atmel,sama5d3-rstc";
0673 reg = <0xf8048000 0x10>;
0674 clocks = <&clk32k>;
0675 };
0676
0677 shutdown_controller: shdwc@f8048010 {
0678 compatible = "atmel,sama5d2-shdwc";
0679 reg = <0xf8048010 0x10>;
0680 clocks = <&clk32k>;
0681 #address-cells = <1>;
0682 #size-cells = <0>;
0683 atmel,wakeup-rtc-timer;
0684 };
0685
0686 pit: timer@f8048030 {
0687 compatible = "atmel,at91sam9260-pit";
0688 reg = <0xf8048030 0x10>;
0689 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
0690 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
0691 };
0692
0693 watchdog: watchdog@f8048040 {
0694 compatible = "atmel,sama5d4-wdt";
0695 reg = <0xf8048040 0x10>;
0696 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
0697 clocks = <&clk32k>;
0698 status = "disabled";
0699 };
0700
0701 clk32k: sckc@f8048050 {
0702 compatible = "atmel,sama5d4-sckc";
0703 reg = <0xf8048050 0x4>;
0704
0705 clocks = <&slow_xtal>;
0706 #clock-cells = <0>;
0707 };
0708
0709 rtc: rtc@f80480b0 {
0710 compatible = "atmel,sama5d2-rtc";
0711 reg = <0xf80480b0 0x30>;
0712 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
0713 clocks = <&clk32k>;
0714 };
0715
0716 i2s0: i2s@f8050000 {
0717 compatible = "atmel,sama5d2-i2s";
0718 reg = <0xf8050000 0x100>;
0719 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
0720 dmas = <&dma0
0721 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0722 AT91_XDMAC_DT_PERID(31))>,
0723 <&dma0
0724 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0725 AT91_XDMAC_DT_PERID(32))>;
0726 dma-names = "tx", "rx";
0727 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>;
0728 clock-names = "pclk", "gclk";
0729 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>;
0730 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>;
0731 status = "disabled";
0732 };
0733
0734 can0: can@f8054000 {
0735 compatible = "bosch,m_can";
0736 reg = <0xf8054000 0x4000>, <0x210000 0x1c00>;
0737 reg-names = "m_can", "message_ram";
0738 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
0739 <64 IRQ_TYPE_LEVEL_HIGH 7>;
0740 interrupt-names = "int0", "int1";
0741 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>;
0742 clock-names = "hclk", "cclk";
0743 assigned-clocks = <&pmc PMC_TYPE_GCK 56>;
0744 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
0745 assigned-clock-rates = <40000000>;
0746 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
0747 status = "disabled";
0748 };
0749
0750 spi1: spi@fc000000 {
0751 compatible = "atmel,at91rm9200-spi";
0752 reg = <0xfc000000 0x100>;
0753 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
0754 dmas = <&dma0
0755 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0756 AT91_XDMAC_DT_PERID(8))>,
0757 <&dma0
0758 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0759 AT91_XDMAC_DT_PERID(9))>;
0760 dma-names = "tx", "rx";
0761 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
0762 clock-names = "spi_clk";
0763 atmel,fifo-size = <16>;
0764 #address-cells = <1>;
0765 #size-cells = <0>;
0766 status = "disabled";
0767 };
0768
0769 uart3: serial@fc008000 {
0770 compatible = "atmel,at91sam9260-usart";
0771 reg = <0xfc008000 0x100>;
0772 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
0773 dmas = <&dma1
0774 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0775 AT91_XDMAC_DT_PERID(41))>,
0776 <&dma1
0777 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0778 AT91_XDMAC_DT_PERID(42))>;
0779 dma-names = "tx", "rx";
0780 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
0781 clock-names = "usart";
0782 status = "disabled";
0783 };
0784
0785 uart4: serial@fc00c000 {
0786 compatible = "atmel,at91sam9260-usart";
0787 reg = <0xfc00c000 0x100>;
0788 dmas = <&dma0
0789 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0790 AT91_XDMAC_DT_PERID(43))>,
0791 <&dma0
0792 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
0793 AT91_XDMAC_DT_PERID(44))>;
0794 dma-names = "tx", "rx";
0795 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
0796 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
0797 clock-names = "usart";
0798 status = "disabled";
0799 };
0800
0801 flx2: flexcom@fc010000 {
0802 compatible = "atmel,sama5d2-flexcom";
0803 reg = <0xfc010000 0x200>;
0804 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
0805 #address-cells = <1>;
0806 #size-cells = <1>;
0807 ranges = <0x0 0xfc010000 0x800>;
0808 status = "disabled";
0809
0810 uart7: serial@200 {
0811 compatible = "atmel,at91sam9260-usart";
0812 reg = <0x200 0x200>;
0813 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
0814 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
0815 clock-names = "usart";
0816 dmas = <&dma0
0817 (AT91_XDMAC_DT_MEM_IF(0) |
0818 AT91_XDMAC_DT_PER_IF(1) |
0819 AT91_XDMAC_DT_PERID(15))>,
0820 <&dma0
0821 (AT91_XDMAC_DT_MEM_IF(0) |
0822 AT91_XDMAC_DT_PER_IF(1) |
0823 AT91_XDMAC_DT_PERID(16))>;
0824 dma-names = "tx", "rx";
0825 atmel,fifo-size = <32>;
0826 status = "disabled";
0827 };
0828
0829 spi4: spi@400 {
0830 compatible = "atmel,at91rm9200-spi";
0831 reg = <0x400 0x200>;
0832 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
0833 #address-cells = <1>;
0834 #size-cells = <0>;
0835 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
0836 clock-names = "spi_clk";
0837 dmas = <&dma0
0838 (AT91_XDMAC_DT_MEM_IF(0) |
0839 AT91_XDMAC_DT_PER_IF(1) |
0840 AT91_XDMAC_DT_PERID(15))>,
0841 <&dma0
0842 (AT91_XDMAC_DT_MEM_IF(0) |
0843 AT91_XDMAC_DT_PER_IF(1) |
0844 AT91_XDMAC_DT_PERID(16))>;
0845 dma-names = "tx", "rx";
0846 atmel,fifo-size = <16>;
0847 status = "disabled";
0848 };
0849
0850 i2c4: i2c@600 {
0851 compatible = "atmel,sama5d2-i2c";
0852 reg = <0x600 0x200>;
0853 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
0854 #address-cells = <1>;
0855 #size-cells = <0>;
0856 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
0857 dmas = <&dma0
0858 (AT91_XDMAC_DT_MEM_IF(0) |
0859 AT91_XDMAC_DT_PER_IF(1) |
0860 AT91_XDMAC_DT_PERID(15))>,
0861 <&dma0
0862 (AT91_XDMAC_DT_MEM_IF(0) |
0863 AT91_XDMAC_DT_PER_IF(1) |
0864 AT91_XDMAC_DT_PERID(16))>;
0865 dma-names = "tx", "rx";
0866 atmel,fifo-size = <16>;
0867 status = "disabled";
0868 };
0869 };
0870
0871 flx3: flexcom@fc014000 {
0872 compatible = "atmel,sama5d2-flexcom";
0873 reg = <0xfc014000 0x200>;
0874 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
0875 #address-cells = <1>;
0876 #size-cells = <1>;
0877 ranges = <0x0 0xfc014000 0x800>;
0878 status = "disabled";
0879
0880 uart8: serial@200 {
0881 compatible = "atmel,at91sam9260-usart";
0882 reg = <0x200 0x200>;
0883 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
0884 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
0885 clock-names = "usart";
0886 dmas = <&dma0
0887 (AT91_XDMAC_DT_MEM_IF(0) |
0888 AT91_XDMAC_DT_PER_IF(1) |
0889 AT91_XDMAC_DT_PERID(17))>,
0890 <&dma0
0891 (AT91_XDMAC_DT_MEM_IF(0) |
0892 AT91_XDMAC_DT_PER_IF(1) |
0893 AT91_XDMAC_DT_PERID(18))>;
0894 dma-names = "tx", "rx";
0895 atmel,fifo-size = <32>;
0896 status = "disabled";
0897 };
0898
0899 spi5: spi@400 {
0900 compatible = "atmel,at91rm9200-spi";
0901 reg = <0x400 0x200>;
0902 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
0903 #address-cells = <1>;
0904 #size-cells = <0>;
0905 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
0906 clock-names = "spi_clk";
0907 dmas = <&dma0
0908 (AT91_XDMAC_DT_MEM_IF(0) |
0909 AT91_XDMAC_DT_PER_IF(1) |
0910 AT91_XDMAC_DT_PERID(17))>,
0911 <&dma0
0912 (AT91_XDMAC_DT_MEM_IF(0) |
0913 AT91_XDMAC_DT_PER_IF(1) |
0914 AT91_XDMAC_DT_PERID(18))>;
0915 dma-names = "tx", "rx";
0916 atmel,fifo-size = <16>;
0917 status = "disabled";
0918 };
0919
0920 i2c5: i2c@600 {
0921 compatible = "atmel,sama5d2-i2c";
0922 reg = <0x600 0x200>;
0923 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
0924 #address-cells = <1>;
0925 #size-cells = <0>;
0926 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
0927 dmas = <&dma0
0928 (AT91_XDMAC_DT_MEM_IF(0) |
0929 AT91_XDMAC_DT_PER_IF(1) |
0930 AT91_XDMAC_DT_PERID(17))>,
0931 <&dma0
0932 (AT91_XDMAC_DT_MEM_IF(0) |
0933 AT91_XDMAC_DT_PER_IF(1) |
0934 AT91_XDMAC_DT_PERID(18))>;
0935 dma-names = "tx", "rx";
0936 atmel,fifo-size = <16>;
0937 status = "disabled";
0938 };
0939
0940 };
0941
0942 flx4: flexcom@fc018000 {
0943 compatible = "atmel,sama5d2-flexcom";
0944 reg = <0xfc018000 0x200>;
0945 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
0946 #address-cells = <1>;
0947 #size-cells = <1>;
0948 ranges = <0x0 0xfc018000 0x800>;
0949 status = "disabled";
0950
0951 uart9: serial@200 {
0952 compatible = "atmel,at91sam9260-usart";
0953 reg = <0x200 0x200>;
0954 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
0955 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
0956 clock-names = "usart";
0957 dmas = <&dma0
0958 (AT91_XDMAC_DT_MEM_IF(0) |
0959 AT91_XDMAC_DT_PER_IF(1) |
0960 AT91_XDMAC_DT_PERID(19))>,
0961 <&dma0
0962 (AT91_XDMAC_DT_MEM_IF(0) |
0963 AT91_XDMAC_DT_PER_IF(1) |
0964 AT91_XDMAC_DT_PERID(20))>;
0965 dma-names = "tx", "rx";
0966 atmel,fifo-size = <32>;
0967 status = "disabled";
0968 };
0969
0970 spi6: spi@400 {
0971 compatible = "atmel,at91rm9200-spi";
0972 reg = <0x400 0x200>;
0973 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
0974 #address-cells = <1>;
0975 #size-cells = <0>;
0976 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
0977 clock-names = "spi_clk";
0978 dmas = <&dma0
0979 (AT91_XDMAC_DT_MEM_IF(0) |
0980 AT91_XDMAC_DT_PER_IF(1) |
0981 AT91_XDMAC_DT_PERID(19))>,
0982 <&dma0
0983 (AT91_XDMAC_DT_MEM_IF(0) |
0984 AT91_XDMAC_DT_PER_IF(1) |
0985 AT91_XDMAC_DT_PERID(20))>;
0986 dma-names = "tx", "rx";
0987 atmel,fifo-size = <16>;
0988 status = "disabled";
0989 };
0990
0991 i2c6: i2c@600 {
0992 compatible = "atmel,sama5d2-i2c";
0993 reg = <0x600 0x200>;
0994 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
0995 #address-cells = <1>;
0996 #size-cells = <0>;
0997 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
0998 dmas = <&dma0
0999 (AT91_XDMAC_DT_MEM_IF(0) |
1000 AT91_XDMAC_DT_PER_IF(1) |
1001 AT91_XDMAC_DT_PERID(19))>,
1002 <&dma0
1003 (AT91_XDMAC_DT_MEM_IF(0) |
1004 AT91_XDMAC_DT_PER_IF(1) |
1005 AT91_XDMAC_DT_PERID(20))>;
1006 dma-names = "tx", "rx";
1007 atmel,fifo-size = <16>;
1008 status = "disabled";
1009 };
1010 };
1011
1012 trng@fc01c000 {
1013 compatible = "atmel,at91sam9g45-trng";
1014 reg = <0xfc01c000 0x100>;
1015 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
1016 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
1017 };
1018
1019 aic: interrupt-controller@fc020000 {
1020 #interrupt-cells = <3>;
1021 compatible = "atmel,sama5d2-aic";
1022 interrupt-controller;
1023 reg = <0xfc020000 0x200>;
1024 atmel,external-irqs = <49>;
1025 };
1026
1027 i2c1: i2c@fc028000 {
1028 compatible = "atmel,sama5d2-i2c";
1029 reg = <0xfc028000 0x100>;
1030 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1031 dmas = <&dma0
1032 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1033 AT91_XDMAC_DT_PERID(2))>,
1034 <&dma0
1035 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1036 AT91_XDMAC_DT_PERID(3))>;
1037 dma-names = "tx", "rx";
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1040 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
1041 atmel,fifo-size = <16>;
1042 status = "disabled";
1043 };
1044
1045 adc: adc@fc030000 {
1046 compatible = "atmel,sama5d2-adc";
1047 reg = <0xfc030000 0x100>;
1048 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
1049 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
1050 clock-names = "adc_clk";
1051 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
1052 dma-names = "rx";
1053 atmel,min-sample-rate-hz = <200000>;
1054 atmel,max-sample-rate-hz = <20000000>;
1055 atmel,startup-time-ms = <4>;
1056 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
1057 #io-channel-cells = <1>;
1058 status = "disabled";
1059 };
1060
1061 pioA: pinctrl@fc038000 {
1062 compatible = "atmel,sama5d2-pinctrl";
1063 reg = <0xfc038000 0x600>;
1064 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1065 <68 IRQ_TYPE_LEVEL_HIGH 7>,
1066 <69 IRQ_TYPE_LEVEL_HIGH 7>,
1067 <70 IRQ_TYPE_LEVEL_HIGH 7>;
1068 interrupt-controller;
1069 #interrupt-cells = <2>;
1070 gpio-controller;
1071 #gpio-cells = <2>;
1072 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
1073 };
1074
1075 pioBU: secumod@fc040000 {
1076 compatible = "atmel,sama5d2-secumod", "syscon";
1077 reg = <0xfc040000 0x100>;
1078
1079 gpio-controller;
1080 #gpio-cells = <2>;
1081 };
1082
1083 tdes: crypto@fc044000 {
1084 compatible = "atmel,at91sam9g46-tdes";
1085 reg = <0xfc044000 0x100>;
1086 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1087 dmas = <&dma0
1088 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1089 AT91_XDMAC_DT_PERID(28))>,
1090 <&dma0
1091 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1092 AT91_XDMAC_DT_PERID(29))>;
1093 dma-names = "tx", "rx";
1094 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
1095 clock-names = "tdes_clk";
1096 };
1097
1098 classd: classd@fc048000 {
1099 compatible = "atmel,sama5d2-classd";
1100 reg = <0xfc048000 0x100>;
1101 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>;
1102 dmas = <&dma0
1103 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1104 AT91_XDMAC_DT_PERID(47))>;
1105 dma-names = "tx";
1106 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>;
1107 clock-names = "pclk", "gclk";
1108 status = "disabled";
1109 };
1110
1111 i2s1: i2s@fc04c000 {
1112 compatible = "atmel,sama5d2-i2s";
1113 reg = <0xfc04c000 0x100>;
1114 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>;
1115 dmas = <&dma0
1116 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1117 AT91_XDMAC_DT_PERID(33))>,
1118 <&dma0
1119 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1120 AT91_XDMAC_DT_PERID(34))>;
1121 dma-names = "tx", "rx";
1122 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>;
1123 clock-names = "pclk", "gclk";
1124 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>;
1125 assigned-clock-parents = <&pmc PMC_TYPE_GCK 55>;
1126 status = "disabled";
1127 };
1128
1129 can1: can@fc050000 {
1130 compatible = "bosch,m_can";
1131 reg = <0xfc050000 0x4000>, <0x210000 0x3800>;
1132 reg-names = "m_can", "message_ram";
1133 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
1134 <65 IRQ_TYPE_LEVEL_HIGH 7>;
1135 interrupt-names = "int0", "int1";
1136 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
1137 clock-names = "hclk", "cclk";
1138 assigned-clocks = <&pmc PMC_TYPE_GCK 57>;
1139 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
1140 assigned-clock-rates = <40000000>;
1141 bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>;
1142 status = "disabled";
1143 };
1144
1145 sfrbu: sfr@fc05c000 {
1146 compatible = "atmel,sama5d2-sfrbu", "syscon";
1147 reg = <0xfc05c000 0x20>;
1148 };
1149
1150 chipid@fc069000 {
1151 compatible = "atmel,sama5d2-chipid";
1152 reg = <0xfc069000 0x8>;
1153 };
1154 };
1155 };
1156 };
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