0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung's S3C64xx SoC series common device tree source
0004 *
0005 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
0006 *
0007 * Samsung's S3C64xx SoC series device nodes are listed in this file.
0008 * Particular SoCs from S3C64xx series can include this file and provide
0009 * values for SoCs specfic bindings.
0010 *
0011 * Note: This file does not include device nodes for all the controllers in
0012 * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional
0013 * nodes can be added to this file.
0014 */
0015
0016 #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
0017
0018 / {
0019 #address-cells = <1>;
0020 #size-cells = <1>;
0021
0022 aliases {
0023 i2c0 = &i2c0;
0024 pinctrl0 = &pinctrl0;
0025 serial0 = &uart0;
0026 serial1 = &uart1;
0027 serial2 = &uart2;
0028 serial3 = &uart3;
0029 };
0030
0031 cpus {
0032 #address-cells = <1>;
0033 #size-cells = <0>;
0034
0035 cpu@0 {
0036 device_type = "cpu";
0037 compatible = "arm,arm1176jzf-s";
0038 reg = <0x0>;
0039 };
0040 };
0041
0042 soc: soc {
0043 compatible = "simple-bus";
0044 #address-cells = <1>;
0045 #size-cells = <1>;
0046 ranges;
0047
0048 vic0: interrupt-controller@71200000 {
0049 compatible = "arm,pl192-vic";
0050 interrupt-controller;
0051 reg = <0x71200000 0x1000>;
0052 #interrupt-cells = <1>;
0053 };
0054
0055 vic1: interrupt-controller@71300000 {
0056 compatible = "arm,pl192-vic";
0057 interrupt-controller;
0058 reg = <0x71300000 0x1000>;
0059 #interrupt-cells = <1>;
0060 };
0061
0062 sdhci0: mmc@7c200000 {
0063 compatible = "samsung,s3c6410-sdhci";
0064 reg = <0x7c200000 0x100>;
0065 interrupt-parent = <&vic1>;
0066 interrupts = <24>;
0067 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
0068 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
0069 <&clocks SCLK_MMC0>;
0070 status = "disabled";
0071 };
0072
0073 sdhci1: mmc@7c300000 {
0074 compatible = "samsung,s3c6410-sdhci";
0075 reg = <0x7c300000 0x100>;
0076 interrupt-parent = <&vic1>;
0077 interrupts = <25>;
0078 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
0079 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
0080 <&clocks SCLK_MMC1>;
0081 status = "disabled";
0082 };
0083
0084 sdhci2: mmc@7c400000 {
0085 compatible = "samsung,s3c6410-sdhci";
0086 reg = <0x7c400000 0x100>;
0087 interrupt-parent = <&vic1>;
0088 interrupts = <17>;
0089 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
0090 clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
0091 <&clocks SCLK_MMC2>;
0092 status = "disabled";
0093 };
0094
0095 watchdog: watchdog@7e004000 {
0096 compatible = "samsung,s3c6410-wdt";
0097 reg = <0x7e004000 0x1000>;
0098 interrupt-parent = <&vic0>;
0099 interrupts = <26>;
0100 clock-names = "watchdog";
0101 clocks = <&clocks PCLK_WDT>;
0102 };
0103
0104 i2c0: i2c@7f004000 {
0105 compatible = "samsung,s3c2440-i2c";
0106 reg = <0x7f004000 0x1000>;
0107 interrupt-parent = <&vic1>;
0108 interrupts = <18>;
0109 clock-names = "i2c";
0110 clocks = <&clocks PCLK_IIC0>;
0111 status = "disabled";
0112 #address-cells = <1>;
0113 #size-cells = <0>;
0114 };
0115
0116 uart0: serial@7f005000 {
0117 compatible = "samsung,s3c6400-uart";
0118 reg = <0x7f005000 0x100>;
0119 interrupt-parent = <&vic1>;
0120 interrupts = <5>;
0121 clock-names = "uart", "clk_uart_baud2",
0122 "clk_uart_baud3";
0123 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
0124 <&clocks SCLK_UART>;
0125 status = "disabled";
0126 };
0127
0128 uart1: serial@7f005400 {
0129 compatible = "samsung,s3c6400-uart";
0130 reg = <0x7f005400 0x100>;
0131 interrupt-parent = <&vic1>;
0132 interrupts = <6>;
0133 clock-names = "uart", "clk_uart_baud2",
0134 "clk_uart_baud3";
0135 clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
0136 <&clocks SCLK_UART>;
0137 status = "disabled";
0138 };
0139
0140 uart2: serial@7f005800 {
0141 compatible = "samsung,s3c6400-uart";
0142 reg = <0x7f005800 0x100>;
0143 interrupt-parent = <&vic1>;
0144 interrupts = <7>;
0145 clock-names = "uart", "clk_uart_baud2",
0146 "clk_uart_baud3";
0147 clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
0148 <&clocks SCLK_UART>;
0149 status = "disabled";
0150 };
0151
0152 uart3: serial@7f005c00 {
0153 compatible = "samsung,s3c6400-uart";
0154 reg = <0x7f005c00 0x100>;
0155 interrupt-parent = <&vic1>;
0156 interrupts = <8>;
0157 clock-names = "uart", "clk_uart_baud2",
0158 "clk_uart_baud3";
0159 clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
0160 <&clocks SCLK_UART>;
0161 status = "disabled";
0162 };
0163
0164 pwm: pwm@7f006000 {
0165 compatible = "samsung,s3c6400-pwm";
0166 reg = <0x7f006000 0x1000>;
0167 interrupt-parent = <&vic0>;
0168 interrupts = <23>, <24>, <25>, <27>, <28>;
0169 clock-names = "timers";
0170 clocks = <&clocks PCLK_PWM>;
0171 samsung,pwm-outputs = <0>, <1>;
0172 #pwm-cells = <3>;
0173 };
0174
0175 pinctrl0: pinctrl@7f008000 {
0176 compatible = "samsung,s3c64xx-pinctrl";
0177 reg = <0x7f008000 0x1000>;
0178 interrupt-parent = <&vic1>;
0179 interrupts = <21>;
0180
0181 wakeup-interrupt-controller {
0182 compatible = "samsung,s3c64xx-wakeup-eint";
0183 interrupts-extended = <&vic0 0>,
0184 <&vic0 1>,
0185 <&vic1 0>,
0186 <&vic1 1>;
0187 };
0188 };
0189 };
0190 };
0191
0192 #include "s3c64xx-pinctrl.dtsi"
