0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Samsung's S3C2416 SoC device tree source
0004 *
0005 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
0006 */
0007
0008 #include <dt-bindings/clock/s3c2443.h>
0009 #include "s3c24xx.dtsi"
0010 #include "s3c2416-pinctrl.dtsi"
0011
0012 / {
0013 model = "Samsung S3C2416 SoC";
0014 compatible = "samsung,s3c2416";
0015
0016 aliases {
0017 serial3 = &uart_3;
0018 };
0019
0020 cpus {
0021 #address-cells = <1>;
0022 #size-cells = <0>;
0023
0024 cpu@0 {
0025 device_type = "cpu";
0026 compatible = "arm,arm926ej-s";
0027 reg = <0x0>;
0028 };
0029 };
0030
0031 clocks: clock-controller@4c000000 {
0032 compatible = "samsung,s3c2416-clock";
0033 reg = <0x4c000000 0x40>;
0034 #clock-cells = <1>;
0035 };
0036
0037 uart_3: serial@5000c000 {
0038 compatible = "samsung,s3c2440-uart";
0039 reg = <0x5000C000 0x4000>;
0040 interrupts = <1 18 24 4>, <1 18 25 4>;
0041 clock-names = "uart", "clk_uart_baud2",
0042 "clk_uart_baud3";
0043 clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
0044 <&clocks SCLK_UART>;
0045 status = "disabled";
0046 };
0047
0048 sdhci_1: mmc@4ac00000 {
0049 compatible = "samsung,s3c6410-sdhci";
0050 reg = <0x4AC00000 0x100>;
0051 interrupts = <0 0 21 3>;
0052 clock-names = "hsmmc", "mmc_busclk.0",
0053 "mmc_busclk.2";
0054 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
0055 <&clocks MUX_HSMMC0>;
0056 status = "disabled";
0057 };
0058
0059 sdhci_0: mmc@4a800000 {
0060 compatible = "samsung,s3c6410-sdhci";
0061 reg = <0x4A800000 0x100>;
0062 interrupts = <0 0 20 3>;
0063 clock-names = "hsmmc", "mmc_busclk.0",
0064 "mmc_busclk.2";
0065 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
0066 <&clocks MUX_HSMMC1>;
0067 status = "disabled";
0068 };
0069 };
0070
0071 &i2c {
0072 compatible = "samsung,s3c2440-i2c";
0073 clocks = <&clocks PCLK_I2C0>;
0074 clock-names = "i2c";
0075 };
0076
0077 &intc {
0078 compatible = "samsung,s3c2416-irq";
0079 };
0080
0081 &pinctrl_0 {
0082 compatible = "samsung,s3c2416-pinctrl";
0083 };
0084
0085 &rtc {
0086 compatible = "samsung,s3c2416-rtc";
0087 clocks = <&clocks PCLK_RTC>;
0088 clock-names = "rtc";
0089 };
0090
0091 &timer {
0092 clocks = <&clocks PCLK_PWM>;
0093 clock-names = "timers";
0094 };
0095
0096 &uart_0 {
0097 compatible = "samsung,s3c2440-uart";
0098 clock-names = "uart", "clk_uart_baud2",
0099 "clk_uart_baud3";
0100 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
0101 <&clocks SCLK_UART>;
0102 };
0103
0104 &uart_1 {
0105 compatible = "samsung,s3c2440-uart";
0106 clock-names = "uart", "clk_uart_baud2",
0107 "clk_uart_baud3";
0108 clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
0109 <&clocks SCLK_UART>;
0110 };
0111
0112 &uart_2 {
0113 compatible = "samsung,s3c2440-uart";
0114 clock-names = "uart", "clk_uart_baud2",
0115 "clk_uart_baud3";
0116 clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
0117 <&clocks SCLK_UART>;
0118 };
0119
0120 &watchdog {
0121 interrupts = <1 9 27 3>;
0122 clocks = <&clocks PCLK_WDT>;
0123 clock-names = "watchdog";
0124 };
