0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002
0003 #include <dt-bindings/gpio/gpio.h>
0004 #include <dt-bindings/interrupt-controller/irq.h>
0005 #include <dt-bindings/interrupt-controller/arm-gic.h>
0006 #include <dt-bindings/clock/rv1108-cru.h>
0007 #include <dt-bindings/pinctrl/rockchip.h>
0008 #include <dt-bindings/thermal/thermal.h>
0009 / {
0010 #address-cells = <1>;
0011 #size-cells = <1>;
0012
0013 compatible = "rockchip,rv1108";
0014
0015 interrupt-parent = <&gic>;
0016
0017 aliases {
0018 i2c0 = &i2c0;
0019 i2c1 = &i2c1;
0020 i2c2 = &i2c2;
0021 i2c3 = &i2c3;
0022 serial0 = &uart0;
0023 serial1 = &uart1;
0024 serial2 = &uart2;
0025 };
0026
0027 cpus {
0028 #address-cells = <1>;
0029 #size-cells = <0>;
0030
0031 cpu0: cpu@f00 {
0032 device_type = "cpu";
0033 compatible = "arm,cortex-a7";
0034 reg = <0xf00>;
0035 clock-latency = <40000>;
0036 clocks = <&cru ARMCLK>;
0037 #cooling-cells = <2>; /* min followed by max */
0038 dynamic-power-coefficient = <75>;
0039 operating-points-v2 = <&cpu_opp_table>;
0040 };
0041 };
0042
0043 cpu_opp_table: opp-table-0 {
0044 compatible = "operating-points-v2";
0045
0046 opp-408000000 {
0047 opp-hz = /bits/ 64 <408000000>;
0048 opp-microvolt = <975000>;
0049 clock-latency-ns = <40000>;
0050 };
0051 opp-600000000 {
0052 opp-hz = /bits/ 64 <600000000>;
0053 opp-microvolt = <975000>;
0054 clock-latency-ns = <40000>;
0055 };
0056 opp-816000000 {
0057 opp-hz = /bits/ 64 <816000000>;
0058 opp-microvolt = <1025000>;
0059 clock-latency-ns = <40000>;
0060 };
0061 opp-1008000000 {
0062 opp-hz = /bits/ 64 <1008000000>;
0063 opp-microvolt = <1150000>;
0064 clock-latency-ns = <40000>;
0065 };
0066 };
0067
0068 arm-pmu {
0069 compatible = "arm,cortex-a7-pmu";
0070 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0071 };
0072
0073 timer {
0074 compatible = "arm,armv7-timer";
0075 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
0076 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
0077 arm,cpu-registers-not-fw-configured;
0078 clock-frequency = <24000000>;
0079 };
0080
0081 xin24m: oscillator {
0082 compatible = "fixed-clock";
0083 clock-frequency = <24000000>;
0084 clock-output-names = "xin24m";
0085 #clock-cells = <0>;
0086 };
0087
0088 bus_intmem: sram@10080000 {
0089 compatible = "mmio-sram";
0090 reg = <0x10080000 0x2000>;
0091 #address-cells = <1>;
0092 #size-cells = <1>;
0093 ranges = <0 0x10080000 0x2000>;
0094 };
0095
0096 uart2: serial@10210000 {
0097 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
0098 reg = <0x10210000 0x100>;
0099 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0100 reg-shift = <2>;
0101 reg-io-width = <4>;
0102 clock-frequency = <24000000>;
0103 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
0104 clock-names = "baudclk", "apb_pclk";
0105 dmas = <&pdma 6>, <&pdma 7>;
0106 pinctrl-names = "default";
0107 pinctrl-0 = <&uart2m0_xfer>;
0108 status = "disabled";
0109 };
0110
0111 uart1: serial@10220000 {
0112 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
0113 reg = <0x10220000 0x100>;
0114 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0115 reg-shift = <2>;
0116 reg-io-width = <4>;
0117 clock-frequency = <24000000>;
0118 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
0119 clock-names = "baudclk", "apb_pclk";
0120 dmas = <&pdma 4>, <&pdma 5>;
0121 pinctrl-names = "default";
0122 pinctrl-0 = <&uart1_xfer>;
0123 status = "disabled";
0124 };
0125
0126 uart0: serial@10230000 {
0127 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
0128 reg = <0x10230000 0x100>;
0129 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
0130 reg-shift = <2>;
0131 reg-io-width = <4>;
0132 clock-frequency = <24000000>;
0133 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
0134 clock-names = "baudclk", "apb_pclk";
0135 dmas = <&pdma 2>, <&pdma 3>;
0136 pinctrl-names = "default";
0137 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
0138 status = "disabled";
0139 };
0140
0141 i2c1: i2c@10240000 {
0142 compatible = "rockchip,rv1108-i2c";
0143 reg = <0x10240000 0x1000>;
0144 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0145 #address-cells = <1>;
0146 #size-cells = <0>;
0147 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
0148 clock-names = "i2c", "pclk";
0149 pinctrl-names = "default";
0150 pinctrl-0 = <&i2c1_xfer>;
0151 rockchip,grf = <&grf>;
0152 status = "disabled";
0153 };
0154
0155 i2c2: i2c@10250000 {
0156 compatible = "rockchip,rv1108-i2c";
0157 reg = <0x10250000 0x1000>;
0158 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0159 #address-cells = <1>;
0160 #size-cells = <0>;
0161 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
0162 clock-names = "i2c", "pclk";
0163 pinctrl-names = "default";
0164 pinctrl-0 = <&i2c2m1_xfer>;
0165 rockchip,grf = <&grf>;
0166 status = "disabled";
0167 };
0168
0169 i2c3: i2c@10260000 {
0170 compatible = "rockchip,rv1108-i2c";
0171 reg = <0x10260000 0x1000>;
0172 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0173 #address-cells = <1>;
0174 #size-cells = <0>;
0175 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
0176 clock-names = "i2c", "pclk";
0177 pinctrl-names = "default";
0178 pinctrl-0 = <&i2c3_xfer>;
0179 rockchip,grf = <&grf>;
0180 status = "disabled";
0181 };
0182
0183 spi: spi@10270000 {
0184 compatible = "rockchip,rv1108-spi";
0185 reg = <0x10270000 0x1000>;
0186 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0187 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
0188 clock-names = "spiclk", "apb_pclk";
0189 dmas = <&pdma 8>, <&pdma 9>;
0190 dma-names = "tx", "rx";
0191 #address-cells = <1>;
0192 #size-cells = <0>;
0193 status = "disabled";
0194 };
0195
0196 pwm4: pwm@10280000 {
0197 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
0198 reg = <0x10280000 0x10>;
0199 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0200 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
0201 clock-names = "pwm", "pclk";
0202 pinctrl-names = "default";
0203 pinctrl-0 = <&pwm4_pin>;
0204 #pwm-cells = <3>;
0205 status = "disabled";
0206 };
0207
0208 pwm5: pwm@10280010 {
0209 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
0210 reg = <0x10280010 0x10>;
0211 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0212 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
0213 clock-names = "pwm", "pclk";
0214 pinctrl-names = "default";
0215 pinctrl-0 = <&pwm5_pin>;
0216 #pwm-cells = <3>;
0217 status = "disabled";
0218 };
0219
0220 pwm6: pwm@10280020 {
0221 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
0222 reg = <0x10280020 0x10>;
0223 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0224 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
0225 clock-names = "pwm", "pclk";
0226 pinctrl-names = "default";
0227 pinctrl-0 = <&pwm6_pin>;
0228 #pwm-cells = <3>;
0229 status = "disabled";
0230 };
0231
0232 pwm7: pwm@10280030 {
0233 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
0234 reg = <0x10280030 0x10>;
0235 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0236 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
0237 clock-names = "pwm", "pclk";
0238 pinctrl-names = "default";
0239 pinctrl-0 = <&pwm7_pin>;
0240 #pwm-cells = <3>;
0241 status = "disabled";
0242 };
0243
0244 pdma: dma-controller@102a0000 {
0245 compatible = "arm,pl330", "arm,primecell";
0246 reg = <0x102a0000 0x4000>;
0247 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0248 #dma-cells = <1>;
0249 arm,pl330-broken-no-flushp;
0250 arm,pl330-periph-burst;
0251 clocks = <&cru ACLK_DMAC>;
0252 clock-names = "apb_pclk";
0253 };
0254
0255 grf: syscon@10300000 {
0256 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
0257 reg = <0x10300000 0x1000>;
0258 #address-cells = <1>;
0259 #size-cells = <1>;
0260
0261 io_domains: io-domains {
0262 compatible = "rockchip,rv1108-io-voltage-domain";
0263 status = "disabled";
0264 };
0265
0266 u2phy: usb2phy@100 {
0267 compatible = "rockchip,rv1108-usb2phy";
0268 reg = <0x100 0x0c>;
0269 clocks = <&cru SCLK_USBPHY>;
0270 clock-names = "phyclk";
0271 #clock-cells = <0>;
0272 clock-output-names = "usbphy";
0273 rockchip,usbgrf = <&usbgrf>;
0274 status = "disabled";
0275
0276 u2phy_otg: otg-port {
0277 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0278 interrupt-names = "otg-mux";
0279 #phy-cells = <0>;
0280 status = "disabled";
0281 };
0282
0283 u2phy_host: host-port {
0284 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0285 interrupt-names = "linestate";
0286 #phy-cells = <0>;
0287 status = "disabled";
0288 };
0289 };
0290 };
0291
0292 timer: timer@10350000 {
0293 compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
0294 reg = <0x10350000 0x20>;
0295 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0296 clocks = <&cru PCLK_TIMER>, <&xin24m>;
0297 clock-names = "pclk", "timer";
0298 };
0299
0300 watchdog: watchdog@10360000 {
0301 compatible = "rockchip,rv1108-wdt", "snps,dw-wdt";
0302 reg = <0x10360000 0x100>;
0303 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0304 clocks = <&cru PCLK_WDT>;
0305 status = "disabled";
0306 };
0307
0308 thermal-zones {
0309 soc_thermal: soc-thermal {
0310 polling-delay-passive = <20>;
0311 polling-delay = <1000>;
0312 sustainable-power = <50>;
0313 thermal-sensors = <&tsadc 0>;
0314
0315 trips {
0316 threshold: trip-point0 {
0317 temperature = <70000>;
0318 hysteresis = <2000>;
0319 type = "passive";
0320 };
0321 target: trip-point1 {
0322 temperature = <85000>;
0323 hysteresis = <2000>;
0324 type = "passive";
0325 };
0326 soc_crit: soc-crit {
0327 temperature = <95000>;
0328 hysteresis = <2000>;
0329 type = "critical";
0330 };
0331 };
0332
0333 cooling-maps {
0334 map0 {
0335 trip = <&target>;
0336 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0337 contribution = <4096>;
0338 };
0339 };
0340 };
0341 };
0342
0343 tsadc: tsadc@10370000 {
0344 compatible = "rockchip,rv1108-tsadc";
0345 reg = <0x10370000 0x100>;
0346 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
0347 assigned-clocks = <&cru SCLK_TSADC>;
0348 assigned-clock-rates = <750000>;
0349 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
0350 clock-names = "tsadc", "apb_pclk";
0351 pinctrl-names = "init", "default", "sleep";
0352 pinctrl-0 = <&otp_pin>;
0353 pinctrl-1 = <&otp_out>;
0354 pinctrl-2 = <&otp_pin>;
0355 resets = <&cru SRST_TSADC>;
0356 reset-names = "tsadc-apb";
0357 rockchip,hw-tshut-temp = <120000>;
0358 #thermal-sensor-cells = <1>;
0359 status = "disabled";
0360 };
0361
0362 adc: adc@1038c000 {
0363 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
0364 reg = <0x1038c000 0x100>;
0365 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0366 #io-channel-cells = <1>;
0367 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
0368 clock-names = "saradc", "apb_pclk";
0369 status = "disabled";
0370 };
0371
0372 i2c0: i2c@20000000 {
0373 compatible = "rockchip,rv1108-i2c";
0374 reg = <0x20000000 0x1000>;
0375 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0376 #address-cells = <1>;
0377 #size-cells = <0>;
0378 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
0379 clock-names = "i2c", "pclk";
0380 pinctrl-names = "default";
0381 pinctrl-0 = <&i2c0_xfer>;
0382 rockchip,grf = <&grf>;
0383 status = "disabled";
0384 };
0385
0386 pwm0: pwm@20040000 {
0387 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
0388 reg = <0x20040000 0x10>;
0389 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0390 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
0391 clock-names = "pwm", "pclk";
0392 pinctrl-names = "default";
0393 pinctrl-0 = <&pwm0_pin>;
0394 #pwm-cells = <3>;
0395 status = "disabled";
0396 };
0397
0398 pwm1: pwm@20040010 {
0399 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
0400 reg = <0x20040010 0x10>;
0401 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0402 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
0403 clock-names = "pwm", "pclk";
0404 pinctrl-names = "default";
0405 pinctrl-0 = <&pwm1_pin>;
0406 #pwm-cells = <3>;
0407 status = "disabled";
0408 };
0409
0410 pwm2: pwm@20040020 {
0411 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
0412 reg = <0x20040020 0x10>;
0413 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0414 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
0415 clock-names = "pwm", "pclk";
0416 pinctrl-names = "default";
0417 pinctrl-0 = <&pwm2_pin>;
0418 #pwm-cells = <3>;
0419 status = "disabled";
0420 };
0421
0422 pwm3: pwm@20040030 {
0423 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
0424 reg = <0x20040030 0x10>;
0425 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0426 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
0427 clock-names = "pwm", "pclk";
0428 pinctrl-names = "default";
0429 pinctrl-0 = <&pwm3_pin>;
0430 #pwm-cells = <3>;
0431 status = "disabled";
0432 };
0433
0434 pmugrf: syscon@20060000 {
0435 compatible = "rockchip,rv1108-pmugrf", "syscon", "simple-mfd";
0436 reg = <0x20060000 0x1000>;
0437
0438 pmu_io_domains: io-domains {
0439 compatible = "rockchip,rv1108-pmu-io-voltage-domain";
0440 status = "disabled";
0441 };
0442 };
0443
0444 usbgrf: syscon@202a0000 {
0445 compatible = "rockchip,rv1108-usbgrf", "syscon";
0446 reg = <0x202a0000 0x1000>;
0447 };
0448
0449 cru: clock-controller@20200000 {
0450 compatible = "rockchip,rv1108-cru";
0451 reg = <0x20200000 0x1000>;
0452 clocks = <&xin24m>;
0453 clock-names = "xin24m";
0454 rockchip,grf = <&grf>;
0455 #clock-cells = <1>;
0456 #reset-cells = <1>;
0457 };
0458
0459 nfc: nand-controller@30100000 {
0460 compatible = "rockchip,rv1108-nfc";
0461 reg = <0x30100000 0x1000>;
0462 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0463 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
0464 clock-names = "ahb", "nfc";
0465 assigned-clocks = <&cru SCLK_NANDC>;
0466 assigned-clock-rates = <150000000>;
0467 status = "disabled";
0468 };
0469
0470 emmc: mmc@30110000 {
0471 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
0472 reg = <0x30110000 0x4000>;
0473 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0474 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
0475 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
0476 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
0477 fifo-depth = <0x100>;
0478 max-frequency = <150000000>;
0479 status = "disabled";
0480 };
0481
0482 sdio: mmc@30120000 {
0483 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
0484 reg = <0x30120000 0x4000>;
0485 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0486 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
0487 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
0488 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
0489 fifo-depth = <0x100>;
0490 max-frequency = <150000000>;
0491 status = "disabled";
0492 };
0493
0494 sdmmc: mmc@30130000 {
0495 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
0496 reg = <0x30130000 0x4000>;
0497 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0498 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
0499 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
0500 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
0501 fifo-depth = <0x100>;
0502 max-frequency = <100000000>;
0503 pinctrl-names = "default";
0504 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
0505 status = "disabled";
0506 };
0507
0508 usb_host_ehci: usb@30140000 {
0509 compatible = "generic-ehci";
0510 reg = <0x30140000 0x20000>;
0511 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0512 clocks = <&cru HCLK_HOST0>, <&u2phy>;
0513 phys = <&u2phy_host>;
0514 phy-names = "usb";
0515 status = "disabled";
0516 };
0517
0518 usb_host_ohci: usb@30160000 {
0519 compatible = "generic-ohci";
0520 reg = <0x30160000 0x20000>;
0521 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0522 clocks = <&cru HCLK_HOST0>, <&u2phy>;
0523 phys = <&u2phy_host>;
0524 phy-names = "usb";
0525 status = "disabled";
0526 };
0527
0528 usb_otg: usb@30180000 {
0529 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
0530 "snps,dwc2";
0531 reg = <0x30180000 0x40000>;
0532 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0533 clocks = <&cru HCLK_OTG>;
0534 clock-names = "otg";
0535 dr_mode = "otg";
0536 g-np-tx-fifo-size = <16>;
0537 g-rx-fifo-size = <280>;
0538 g-tx-fifo-size = <256 128 128 64 32 16>;
0539 phys = <&u2phy_otg>;
0540 phy-names = "usb2-phy";
0541 status = "disabled";
0542 };
0543
0544 sfc: spi@301c0000 {
0545 compatible = "rockchip,sfc";
0546 reg = <0x301c0000 0x4000>;
0547 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0548 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
0549 clock-names = "clk_sfc", "hclk_sfc";
0550 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
0551 pinctrl-names = "default";
0552 status = "disabled";
0553 };
0554
0555 gmac: ethernet@30200000 {
0556 compatible = "rockchip,rv1108-gmac";
0557 reg = <0x30200000 0x10000>;
0558 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0559 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0560 interrupt-names = "macirq", "eth_wake_irq";
0561 clocks = <&cru SCLK_MAC>,
0562 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
0563 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
0564 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
0565 clock-names = "stmmaceth",
0566 "mac_clk_rx", "mac_clk_tx",
0567 "clk_mac_ref", "clk_mac_refout",
0568 "aclk_mac", "pclk_mac";
0569 /* rv1108 only supports an rmii interface */
0570 phy-mode = "rmii";
0571 pinctrl-names = "default";
0572 pinctrl-0 = <&rmii_pins>;
0573 rockchip,grf = <&grf>;
0574 status = "disabled";
0575 };
0576
0577 gic: interrupt-controller@32010000 {
0578 compatible = "arm,gic-400";
0579 interrupt-controller;
0580 #interrupt-cells = <3>;
0581 #address-cells = <0>;
0582
0583 reg = <0x32011000 0x1000>,
0584 <0x32012000 0x2000>,
0585 <0x32014000 0x2000>,
0586 <0x32016000 0x2000>;
0587 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
0588 };
0589
0590 pinctrl: pinctrl {
0591 compatible = "rockchip,rv1108-pinctrl";
0592 rockchip,grf = <&grf>;
0593 rockchip,pmu = <&pmugrf>;
0594 #address-cells = <1>;
0595 #size-cells = <1>;
0596 ranges;
0597
0598 gpio0: gpio@20030000 {
0599 compatible = "rockchip,gpio-bank";
0600 reg = <0x20030000 0x100>;
0601 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
0602 clocks = <&cru PCLK_GPIO0_PMU>;
0603
0604 gpio-controller;
0605 #gpio-cells = <2>;
0606
0607 interrupt-controller;
0608 #interrupt-cells = <2>;
0609 };
0610
0611 gpio1: gpio@10310000 {
0612 compatible = "rockchip,gpio-bank";
0613 reg = <0x10310000 0x100>;
0614 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
0615 clocks = <&cru PCLK_GPIO1>;
0616
0617 gpio-controller;
0618 #gpio-cells = <2>;
0619
0620 interrupt-controller;
0621 #interrupt-cells = <2>;
0622 };
0623
0624 gpio2: gpio@10320000 {
0625 compatible = "rockchip,gpio-bank";
0626 reg = <0x10320000 0x100>;
0627 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0628 clocks = <&cru PCLK_GPIO2>;
0629
0630 gpio-controller;
0631 #gpio-cells = <2>;
0632
0633 interrupt-controller;
0634 #interrupt-cells = <2>;
0635 };
0636
0637 gpio3: gpio@10330000 {
0638 compatible = "rockchip,gpio-bank";
0639 reg = <0x10330000 0x100>;
0640 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
0641 clocks = <&cru PCLK_GPIO3>;
0642
0643 gpio-controller;
0644 #gpio-cells = <2>;
0645
0646 interrupt-controller;
0647 #interrupt-cells = <2>;
0648 };
0649
0650 pcfg_pull_up: pcfg-pull-up {
0651 bias-pull-up;
0652 };
0653
0654 pcfg_pull_down: pcfg-pull-down {
0655 bias-pull-down;
0656 };
0657
0658 pcfg_pull_none: pcfg-pull-none {
0659 bias-disable;
0660 };
0661
0662 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
0663 drive-strength = <8>;
0664 };
0665
0666 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
0667 drive-strength = <12>;
0668 };
0669
0670 pcfg_pull_none_smt: pcfg-pull-none-smt {
0671 bias-disable;
0672 input-schmitt-enable;
0673 };
0674
0675 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
0676 bias-pull-up;
0677 drive-strength = <8>;
0678 };
0679
0680 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
0681 drive-strength = <4>;
0682 };
0683
0684 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
0685 bias-pull-up;
0686 drive-strength = <4>;
0687 };
0688
0689 pcfg_output_high: pcfg-output-high {
0690 output-high;
0691 };
0692
0693 pcfg_output_low: pcfg-output-low {
0694 output-low;
0695 };
0696
0697 pcfg_input_high: pcfg-input-high {
0698 bias-pull-up;
0699 input-enable;
0700 };
0701
0702 emmc {
0703 emmc_bus8: emmc-bus8 {
0704 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>,
0705 <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>,
0706 <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>,
0707 <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>,
0708 <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>,
0709 <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>,
0710 <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>,
0711 <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>;
0712 };
0713
0714 emmc_clk: emmc-clk {
0715 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>;
0716 };
0717
0718 emmc_cmd: emmc-cmd {
0719 rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>;
0720 };
0721 };
0722
0723 sfc {
0724 sfc_bus4: sfc-bus4 {
0725 rockchip,pins =
0726 <2 RK_PA0 3 &pcfg_pull_none>,
0727 <2 RK_PA1 3 &pcfg_pull_none>,
0728 <2 RK_PA2 3 &pcfg_pull_none>,
0729 <2 RK_PA3 3 &pcfg_pull_none>;
0730 };
0731
0732 sfc_bus2: sfc-bus2 {
0733 rockchip,pins =
0734 <2 RK_PA0 3 &pcfg_pull_none>,
0735 <2 RK_PA1 3 &pcfg_pull_none>;
0736 };
0737
0738 sfc_cs0: sfc-cs0 {
0739 rockchip,pins =
0740 <2 RK_PB4 3 &pcfg_pull_none>;
0741 };
0742
0743 sfc_clk: sfc-clk {
0744 rockchip,pins =
0745 <2 RK_PB7 2 &pcfg_pull_none>;
0746 };
0747 };
0748
0749 gmac {
0750 rmii_pins: rmii-pins {
0751 rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,
0752 <1 RK_PC3 2 &pcfg_pull_none>,
0753 <1 RK_PC4 2 &pcfg_pull_none>,
0754 <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>,
0755 <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>,
0756 <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>,
0757 <1 RK_PB5 3 &pcfg_pull_none>,
0758 <1 RK_PB6 3 &pcfg_pull_none>,
0759 <1 RK_PB7 3 &pcfg_pull_none>,
0760 <1 RK_PC2 3 &pcfg_pull_none>;
0761 };
0762 };
0763
0764 i2c0 {
0765 i2c0_xfer: i2c0-xfer {
0766 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>,
0767 <0 RK_PB2 1 &pcfg_pull_none_smt>;
0768 };
0769 };
0770
0771 i2c1 {
0772 i2c1_xfer: i2c1-xfer {
0773 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>,
0774 <2 RK_PD4 1 &pcfg_pull_up>;
0775 };
0776 };
0777
0778 i2c2m1 {
0779 i2c2m1_xfer: i2c2m1-xfer {
0780 rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>,
0781 <0 RK_PC6 3 &pcfg_pull_none>;
0782 };
0783
0784 i2c2m1_pins: i2c2m1-pins {
0785 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
0786 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
0787 };
0788 };
0789
0790 i2c2m05v {
0791 i2c2m05v_xfer: i2c2m05v-xfer {
0792 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>,
0793 <1 RK_PD4 2 &pcfg_pull_none>;
0794 };
0795
0796 i2c2m05v_pins: i2c2m05v-pins {
0797 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
0798 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
0799 };
0800 };
0801
0802 i2c3 {
0803 i2c3_xfer: i2c3-xfer {
0804 rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>,
0805 <0 RK_PC4 2 &pcfg_pull_none>;
0806 };
0807 };
0808
0809 pwm0 {
0810 pwm0_pin: pwm0-pin {
0811 rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>;
0812 };
0813 };
0814
0815 pwm1 {
0816 pwm1_pin: pwm1-pin {
0817 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
0818 };
0819 };
0820
0821 pwm2 {
0822 pwm2_pin: pwm2-pin {
0823 rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>;
0824 };
0825 };
0826
0827 pwm3 {
0828 pwm3_pin: pwm3-pin {
0829 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>;
0830 };
0831 };
0832
0833 pwm4 {
0834 pwm4_pin: pwm4-pin {
0835 rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>;
0836 };
0837 };
0838
0839 pwm5 {
0840 pwm5_pin: pwm5-pin {
0841 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>;
0842 };
0843 };
0844
0845 pwm6 {
0846 pwm6_pin: pwm6-pin {
0847 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
0848 };
0849 };
0850
0851 pwm7 {
0852 pwm7_pin: pwm7-pin {
0853 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>;
0854 };
0855 };
0856
0857 sdmmc {
0858 sdmmc_clk: sdmmc-clk {
0859 rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>;
0860 };
0861
0862 sdmmc_cmd: sdmmc-cmd {
0863 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>;
0864 };
0865
0866 sdmmc_cd: sdmmc-cd {
0867 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>;
0868 };
0869
0870 sdmmc_bus1: sdmmc-bus1 {
0871 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>;
0872 };
0873
0874 sdmmc_bus4: sdmmc-bus4 {
0875 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>,
0876 <3 RK_PC2 1 &pcfg_pull_up_drv_4ma>,
0877 <3 RK_PC1 1 &pcfg_pull_up_drv_4ma>,
0878 <3 RK_PC0 1 &pcfg_pull_up_drv_4ma>;
0879 };
0880 };
0881
0882 spim0 {
0883 spim0_clk: spim0-clk {
0884 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>;
0885 };
0886
0887 spim0_cs0: spim0-cs0 {
0888 rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>;
0889 };
0890
0891 spim0_tx: spim0-tx {
0892 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
0893 };
0894
0895 spim0_rx: spim0-rx {
0896 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
0897 };
0898 };
0899
0900 spim1 {
0901 spim1_clk: spim1-clk {
0902 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
0903 };
0904
0905 spim1_cs0: spim1-cs0 {
0906 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>;
0907 };
0908
0909 spim1_rx: spim1-rx {
0910 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>;
0911 };
0912
0913 spim1_tx: spim1-tx {
0914 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>;
0915 };
0916 };
0917
0918 tsadc {
0919 otp_out: otp-out {
0920 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
0921 };
0922
0923 otp_pin: otp-pin {
0924 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
0925 };
0926 };
0927
0928 uart0 {
0929 uart0_xfer: uart0-xfer {
0930 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>,
0931 <3 RK_PA5 1 &pcfg_pull_none>;
0932 };
0933
0934 uart0_cts: uart0-cts {
0935 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
0936 };
0937
0938 uart0_rts: uart0-rts {
0939 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
0940 };
0941
0942 uart0_rts_pin: uart0-rts-pin {
0943 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
0944 };
0945 };
0946
0947 uart1 {
0948 uart1_xfer: uart1-xfer {
0949 rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>,
0950 <1 RK_PD2 1 &pcfg_pull_none>;
0951 };
0952
0953 uart1_cts: uart1-cts {
0954 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
0955 };
0956
0957 uart1_rts: uart1-rts {
0958 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
0959 };
0960 };
0961
0962 uart2m0 {
0963 uart2m0_xfer: uart2m0-xfer {
0964 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>,
0965 <2 RK_PD1 1 &pcfg_pull_none>;
0966 };
0967 };
0968
0969 uart2m1 {
0970 uart2m1_xfer: uart2m1-xfer {
0971 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>,
0972 <3 RK_PC2 2 &pcfg_pull_none>;
0973 };
0974 };
0975
0976 uart2_5v {
0977 uart2_5v_cts: uart2_5v-cts {
0978 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
0979 };
0980
0981 uart2_5v_rts: uart2_5v-rts {
0982 rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>;
0983 };
0984 };
0985 };
0986 };
