0001 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
0002 /*
0003 * Copyright (c) 2017-2019 Andreas Färber
0004 */
0005
0006 /memreserve/ 0x00000000 0x0000a800; /* boot code */
0007 /memreserve/ 0x0000a800 0x000f5800;
0008 /memreserve/ 0x17fff000 0x00001000;
0009
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/reset/realtek,rtd1195.h>
0012
0013 / {
0014 compatible = "realtek,rtd1195";
0015 interrupt-parent = <&gic>;
0016 #address-cells = <1>;
0017 #size-cells = <1>;
0018
0019 cpus {
0020 #address-cells = <1>;
0021 #size-cells = <0>;
0022
0023 cpu0: cpu@0 {
0024 device_type = "cpu";
0025 compatible = "arm,cortex-a7";
0026 reg = <0x0>;
0027 clock-frequency = <1000000000>;
0028 };
0029
0030 cpu1: cpu@1 {
0031 device_type = "cpu";
0032 compatible = "arm,cortex-a7";
0033 reg = <0x1>;
0034 clock-frequency = <1000000000>;
0035 };
0036 };
0037
0038 reserved-memory {
0039 #address-cells = <1>;
0040 #size-cells = <1>;
0041 ranges;
0042
0043 rpc_comm: rpc@b000 {
0044 reg = <0x0000b000 0x1000>;
0045 };
0046
0047 audio@1b00000 {
0048 reg = <0x01b00000 0x400000>;
0049 };
0050
0051 rpc_ringbuf: rpc@1ffe000 {
0052 reg = <0x01ffe000 0x4000>;
0053 };
0054
0055 secure@10000000 {
0056 reg = <0x10000000 0x100000>;
0057 no-map;
0058 };
0059 };
0060
0061 arm-pmu {
0062 compatible = "arm,cortex-a7-pmu";
0063 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
0064 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0065 interrupt-affinity = <&cpu0>, <&cpu1>;
0066 };
0067
0068 timer {
0069 compatible = "arm,armv7-timer";
0070 interrupts = <GIC_PPI 13
0071 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0072 <GIC_PPI 14
0073 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0074 <GIC_PPI 11
0075 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0076 <GIC_PPI 10
0077 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
0078 clock-frequency = <27000000>;
0079 };
0080
0081 osc27M: osc {
0082 compatible = "fixed-clock";
0083 clock-frequency = <27000000>;
0084 #clock-cells = <0>;
0085 clock-output-names = "osc27M";
0086 };
0087
0088 soc {
0089 compatible = "simple-bus";
0090 #address-cells = <1>;
0091 #size-cells = <1>;
0092 ranges = <0x00000000 0x00000000 0x0000a800>,
0093 <0x18000000 0x18000000 0x00070000>,
0094 <0x18100000 0x18100000 0x01000000>,
0095 <0x80000000 0x80000000 0x80000000>;
0096
0097 rbus: bus@18000000 {
0098 compatible = "simple-bus";
0099 reg = <0x18000000 0x70000>;
0100 #address-cells = <1>;
0101 #size-cells = <1>;
0102 ranges = <0x0 0x18000000 0x70000>;
0103
0104 crt: syscon@0 {
0105 compatible = "syscon", "simple-mfd";
0106 reg = <0x0 0x1000>;
0107 reg-io-width = <4>;
0108 #address-cells = <1>;
0109 #size-cells = <1>;
0110 ranges = <0x0 0x0 0x1000>;
0111 };
0112
0113 iso: syscon@7000 {
0114 compatible = "syscon", "simple-mfd";
0115 reg = <0x7000 0x1000>;
0116 reg-io-width = <4>;
0117 #address-cells = <1>;
0118 #size-cells = <1>;
0119 ranges = <0x0 0x7000 0x1000>;
0120 };
0121
0122 sb2: syscon@1a000 {
0123 compatible = "syscon", "simple-mfd";
0124 reg = <0x1a000 0x1000>;
0125 reg-io-width = <4>;
0126 #address-cells = <1>;
0127 #size-cells = <1>;
0128 ranges = <0x0 0x1a000 0x1000>;
0129 };
0130
0131 misc: syscon@1b000 {
0132 compatible = "syscon", "simple-mfd";
0133 reg = <0x1b000 0x1000>;
0134 reg-io-width = <4>;
0135 #address-cells = <1>;
0136 #size-cells = <1>;
0137 ranges = <0x0 0x1b000 0x1000>;
0138 };
0139
0140 scpu_wrapper: syscon@1d000 {
0141 compatible = "syscon", "simple-mfd";
0142 reg = <0x1d000 0x1000>;
0143 reg-io-width = <4>;
0144 #address-cells = <1>;
0145 #size-cells = <1>;
0146 ranges = <0x0 0x1d000 0x1000>;
0147 };
0148 };
0149
0150 gic: interrupt-controller@ff011000 {
0151 compatible = "arm,cortex-a7-gic";
0152 reg = <0xff011000 0x1000>,
0153 <0xff012000 0x2000>,
0154 <0xff014000 0x2000>,
0155 <0xff016000 0x2000>;
0156 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
0157 interrupt-controller;
0158 #interrupt-cells = <3>;
0159 };
0160 };
0161 };
0162
0163 &crt {
0164 reset1: reset-controller@0 {
0165 compatible = "snps,dw-low-reset";
0166 reg = <0x0 0x4>;
0167 #reset-cells = <1>;
0168 };
0169
0170 reset2: reset-controller@4 {
0171 compatible = "snps,dw-low-reset";
0172 reg = <0x4 0x4>;
0173 #reset-cells = <1>;
0174 };
0175
0176 reset3: reset-controller@8 {
0177 compatible = "snps,dw-low-reset";
0178 reg = <0x8 0x4>;
0179 #reset-cells = <1>;
0180 };
0181 };
0182
0183 &iso {
0184 iso_reset: reset-controller@88 {
0185 compatible = "snps,dw-low-reset";
0186 reg = <0x88 0x4>;
0187 #reset-cells = <1>;
0188 };
0189
0190 wdt: watchdog@680 {
0191 compatible = "realtek,rtd1295-watchdog";
0192 reg = <0x680 0x100>;
0193 clocks = <&osc27M>;
0194 };
0195
0196 uart0: serial@800 {
0197 compatible = "snps,dw-apb-uart";
0198 reg = <0x800 0x400>;
0199 reg-shift = <2>;
0200 reg-io-width = <4>;
0201 resets = <&iso_reset RTD1195_ISO_RSTN_UR0>;
0202 clock-frequency = <27000000>;
0203 status = "disabled";
0204 };
0205 };
0206
0207 &misc {
0208 uart1: serial@200 {
0209 compatible = "snps,dw-apb-uart";
0210 reg = <0x200 0x100>;
0211 reg-shift = <2>;
0212 reg-io-width = <4>;
0213 resets = <&reset2 RTD1195_RSTN_UR1>;
0214 clock-frequency = <27000000>;
0215 status = "disabled";
0216 };
0217 };
