0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2013 MundoReader S.L.
0004 * Author: Heiko Stuebner <heiko@sntech.de>
0005 */
0006
0007 #include <dt-bindings/interrupt-controller/irq.h>
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/soc/rockchip,boot-mode.h>
0010
0011 / {
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014
0015 interrupt-parent = <&gic>;
0016
0017 aliases {
0018 ethernet0 = &emac;
0019 i2c0 = &i2c0;
0020 i2c1 = &i2c1;
0021 i2c2 = &i2c2;
0022 i2c3 = &i2c3;
0023 i2c4 = &i2c4;
0024 serial0 = &uart0;
0025 serial1 = &uart1;
0026 serial2 = &uart2;
0027 serial3 = &uart3;
0028 spi0 = &spi0;
0029 spi1 = &spi1;
0030 };
0031
0032 xin24m: oscillator {
0033 compatible = "fixed-clock";
0034 clock-frequency = <24000000>;
0035 #clock-cells = <0>;
0036 clock-output-names = "xin24m";
0037 };
0038
0039 gpu: gpu@10090000 {
0040 compatible = "arm,mali-400";
0041 reg = <0x10090000 0x10000>;
0042 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
0043 clock-names = "bus", "core";
0044 assigned-clocks = <&cru ACLK_GPU>;
0045 assigned-clock-rates = <100000000>;
0046 resets = <&cru SRST_GPU>;
0047 status = "disabled";
0048 };
0049
0050 vpu: video-codec@10104000 {
0051 compatible = "rockchip,rk3066-vpu";
0052 reg = <0x10104000 0x800>;
0053 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0054 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0055 interrupt-names = "vepu", "vdpu";
0056 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
0057 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
0058 clock-names = "aclk_vdpu", "hclk_vdpu",
0059 "aclk_vepu", "hclk_vepu";
0060 };
0061
0062 L2: cache-controller@10138000 {
0063 compatible = "arm,pl310-cache";
0064 reg = <0x10138000 0x1000>;
0065 cache-unified;
0066 cache-level = <2>;
0067 };
0068
0069 scu@1013c000 {
0070 compatible = "arm,cortex-a9-scu";
0071 reg = <0x1013c000 0x100>;
0072 };
0073
0074 global_timer: global-timer@1013c200 {
0075 compatible = "arm,cortex-a9-global-timer";
0076 reg = <0x1013c200 0x20>;
0077 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
0078 clocks = <&cru CORE_PERI>;
0079 };
0080
0081 local_timer: local-timer@1013c600 {
0082 compatible = "arm,cortex-a9-twd-timer";
0083 reg = <0x1013c600 0x20>;
0084 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
0085 clocks = <&cru CORE_PERI>;
0086 };
0087
0088 gic: interrupt-controller@1013d000 {
0089 compatible = "arm,cortex-a9-gic";
0090 interrupt-controller;
0091 #interrupt-cells = <3>;
0092 reg = <0x1013d000 0x1000>,
0093 <0x1013c100 0x0100>;
0094 };
0095
0096 uart0: serial@10124000 {
0097 compatible = "snps,dw-apb-uart";
0098 reg = <0x10124000 0x400>;
0099 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0100 reg-shift = <2>;
0101 reg-io-width = <1>;
0102 clock-names = "baudclk", "apb_pclk";
0103 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
0104 status = "disabled";
0105 };
0106
0107 uart1: serial@10126000 {
0108 compatible = "snps,dw-apb-uart";
0109 reg = <0x10126000 0x400>;
0110 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0111 reg-shift = <2>;
0112 reg-io-width = <1>;
0113 clock-names = "baudclk", "apb_pclk";
0114 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
0115 status = "disabled";
0116 };
0117
0118 qos_gpu: qos@1012d000 {
0119 compatible = "rockchip,rk3066-qos", "syscon";
0120 reg = <0x1012d000 0x20>;
0121 };
0122
0123 qos_vpu: qos@1012e000 {
0124 compatible = "rockchip,rk3066-qos", "syscon";
0125 reg = <0x1012e000 0x20>;
0126 };
0127
0128 qos_lcdc0: qos@1012f000 {
0129 compatible = "rockchip,rk3066-qos", "syscon";
0130 reg = <0x1012f000 0x20>;
0131 };
0132
0133 qos_cif0: qos@1012f080 {
0134 compatible = "rockchip,rk3066-qos", "syscon";
0135 reg = <0x1012f080 0x20>;
0136 };
0137
0138 qos_ipp: qos@1012f100 {
0139 compatible = "rockchip,rk3066-qos", "syscon";
0140 reg = <0x1012f100 0x20>;
0141 };
0142
0143 qos_lcdc1: qos@1012f180 {
0144 compatible = "rockchip,rk3066-qos", "syscon";
0145 reg = <0x1012f180 0x20>;
0146 };
0147
0148 qos_cif1: qos@1012f200 {
0149 compatible = "rockchip,rk3066-qos", "syscon";
0150 reg = <0x1012f200 0x20>;
0151 };
0152
0153 qos_rga: qos@1012f280 {
0154 compatible = "rockchip,rk3066-qos", "syscon";
0155 reg = <0x1012f280 0x20>;
0156 };
0157
0158 usb_otg: usb@10180000 {
0159 compatible = "rockchip,rk3066-usb", "snps,dwc2";
0160 reg = <0x10180000 0x40000>;
0161 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0162 clocks = <&cru HCLK_OTG0>;
0163 clock-names = "otg";
0164 dr_mode = "otg";
0165 g-np-tx-fifo-size = <16>;
0166 g-rx-fifo-size = <275>;
0167 g-tx-fifo-size = <256 128 128 64 64 32>;
0168 phys = <&usbphy0>;
0169 phy-names = "usb2-phy";
0170 status = "disabled";
0171 };
0172
0173 usb_host: usb@101c0000 {
0174 compatible = "snps,dwc2";
0175 reg = <0x101c0000 0x40000>;
0176 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0177 clocks = <&cru HCLK_OTG1>;
0178 clock-names = "otg";
0179 dr_mode = "host";
0180 phys = <&usbphy1>;
0181 phy-names = "usb2-phy";
0182 status = "disabled";
0183 };
0184
0185 emac: ethernet@10204000 {
0186 compatible = "snps,arc-emac";
0187 reg = <0x10204000 0x3c>;
0188 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0189 #address-cells = <1>;
0190 #size-cells = <0>;
0191
0192 rockchip,grf = <&grf>;
0193
0194 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
0195 clock-names = "hclk", "macref";
0196 max-speed = <100>;
0197 phy-mode = "rmii";
0198
0199 status = "disabled";
0200 };
0201
0202 mmc0: mmc@10214000 {
0203 compatible = "rockchip,rk2928-dw-mshc";
0204 reg = <0x10214000 0x1000>;
0205 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0206 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
0207 clock-names = "biu", "ciu";
0208 dmas = <&dmac2 1>;
0209 dma-names = "rx-tx";
0210 fifo-depth = <256>;
0211 resets = <&cru SRST_SDMMC>;
0212 reset-names = "reset";
0213 status = "disabled";
0214 };
0215
0216 mmc1: mmc@10218000 {
0217 compatible = "rockchip,rk2928-dw-mshc";
0218 reg = <0x10218000 0x1000>;
0219 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0220 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
0221 clock-names = "biu", "ciu";
0222 dmas = <&dmac2 3>;
0223 dma-names = "rx-tx";
0224 fifo-depth = <256>;
0225 resets = <&cru SRST_SDIO>;
0226 reset-names = "reset";
0227 status = "disabled";
0228 };
0229
0230 emmc: mmc@1021c000 {
0231 compatible = "rockchip,rk2928-dw-mshc";
0232 reg = <0x1021c000 0x1000>;
0233 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0234 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
0235 clock-names = "biu", "ciu";
0236 dmas = <&dmac2 4>;
0237 dma-names = "rx-tx";
0238 fifo-depth = <256>;
0239 resets = <&cru SRST_EMMC>;
0240 reset-names = "reset";
0241 status = "disabled";
0242 };
0243
0244 nfc: nand-controller@10500000 {
0245 compatible = "rockchip,rk2928-nfc";
0246 reg = <0x10500000 0x4000>;
0247 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0248 clocks = <&cru HCLK_NANDC0>;
0249 clock-names = "ahb";
0250 status = "disabled";
0251 };
0252
0253 pmu: pmu@20004000 {
0254 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
0255 reg = <0x20004000 0x100>;
0256
0257 reboot-mode {
0258 compatible = "syscon-reboot-mode";
0259 offset = <0x40>;
0260 mode-normal = <BOOT_NORMAL>;
0261 mode-recovery = <BOOT_RECOVERY>;
0262 mode-bootloader = <BOOT_FASTBOOT>;
0263 mode-loader = <BOOT_BL_DOWNLOAD>;
0264 };
0265 };
0266
0267 grf: grf@20008000 {
0268 compatible = "syscon", "simple-mfd";
0269 reg = <0x20008000 0x200>;
0270 };
0271
0272 dmac1_s: dma-controller@20018000 {
0273 compatible = "arm,pl330", "arm,primecell";
0274 reg = <0x20018000 0x4000>;
0275 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0276 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0277 #dma-cells = <1>;
0278 arm,pl330-broken-no-flushp;
0279 arm,pl330-periph-burst;
0280 clocks = <&cru ACLK_DMA1>;
0281 clock-names = "apb_pclk";
0282 };
0283
0284 dmac1_ns: dma-controller@2001c000 {
0285 compatible = "arm,pl330", "arm,primecell";
0286 reg = <0x2001c000 0x4000>;
0287 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0288 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0289 #dma-cells = <1>;
0290 arm,pl330-broken-no-flushp;
0291 arm,pl330-periph-burst;
0292 clocks = <&cru ACLK_DMA1>;
0293 clock-names = "apb_pclk";
0294 status = "disabled";
0295 };
0296
0297 i2c0: i2c@2002d000 {
0298 compatible = "rockchip,rk3066-i2c";
0299 reg = <0x2002d000 0x1000>;
0300 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
0301 #address-cells = <1>;
0302 #size-cells = <0>;
0303
0304 rockchip,grf = <&grf>;
0305
0306 clock-names = "i2c";
0307 clocks = <&cru PCLK_I2C0>;
0308
0309 status = "disabled";
0310 };
0311
0312 i2c1: i2c@2002f000 {
0313 compatible = "rockchip,rk3066-i2c";
0314 reg = <0x2002f000 0x1000>;
0315 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
0316 #address-cells = <1>;
0317 #size-cells = <0>;
0318
0319 rockchip,grf = <&grf>;
0320
0321 clocks = <&cru PCLK_I2C1>;
0322 clock-names = "i2c";
0323
0324 status = "disabled";
0325 };
0326
0327 pwm0: pwm@20030000 {
0328 compatible = "rockchip,rk2928-pwm";
0329 reg = <0x20030000 0x10>;
0330 #pwm-cells = <2>;
0331 clocks = <&cru PCLK_PWM01>;
0332 status = "disabled";
0333 };
0334
0335 pwm1: pwm@20030010 {
0336 compatible = "rockchip,rk2928-pwm";
0337 reg = <0x20030010 0x10>;
0338 #pwm-cells = <2>;
0339 clocks = <&cru PCLK_PWM01>;
0340 status = "disabled";
0341 };
0342
0343 wdt: watchdog@2004c000 {
0344 compatible = "snps,dw-wdt";
0345 reg = <0x2004c000 0x100>;
0346 clocks = <&cru PCLK_WDT>;
0347 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0348 status = "disabled";
0349 };
0350
0351 pwm2: pwm@20050020 {
0352 compatible = "rockchip,rk2928-pwm";
0353 reg = <0x20050020 0x10>;
0354 #pwm-cells = <2>;
0355 clocks = <&cru PCLK_PWM23>;
0356 status = "disabled";
0357 };
0358
0359 pwm3: pwm@20050030 {
0360 compatible = "rockchip,rk2928-pwm";
0361 reg = <0x20050030 0x10>;
0362 #pwm-cells = <2>;
0363 clocks = <&cru PCLK_PWM23>;
0364 status = "disabled";
0365 };
0366
0367 i2c2: i2c@20056000 {
0368 compatible = "rockchip,rk3066-i2c";
0369 reg = <0x20056000 0x1000>;
0370 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0371 #address-cells = <1>;
0372 #size-cells = <0>;
0373
0374 rockchip,grf = <&grf>;
0375
0376 clocks = <&cru PCLK_I2C2>;
0377 clock-names = "i2c";
0378
0379 status = "disabled";
0380 };
0381
0382 i2c3: i2c@2005a000 {
0383 compatible = "rockchip,rk3066-i2c";
0384 reg = <0x2005a000 0x1000>;
0385 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
0386 #address-cells = <1>;
0387 #size-cells = <0>;
0388
0389 rockchip,grf = <&grf>;
0390
0391 clocks = <&cru PCLK_I2C3>;
0392 clock-names = "i2c";
0393
0394 status = "disabled";
0395 };
0396
0397 i2c4: i2c@2005e000 {
0398 compatible = "rockchip,rk3066-i2c";
0399 reg = <0x2005e000 0x1000>;
0400 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
0401 #address-cells = <1>;
0402 #size-cells = <0>;
0403
0404 rockchip,grf = <&grf>;
0405
0406 clocks = <&cru PCLK_I2C4>;
0407 clock-names = "i2c";
0408
0409 status = "disabled";
0410 };
0411
0412 uart2: serial@20064000 {
0413 compatible = "snps,dw-apb-uart";
0414 reg = <0x20064000 0x400>;
0415 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0416 reg-shift = <2>;
0417 reg-io-width = <1>;
0418 clock-names = "baudclk", "apb_pclk";
0419 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
0420 status = "disabled";
0421 };
0422
0423 uart3: serial@20068000 {
0424 compatible = "snps,dw-apb-uart";
0425 reg = <0x20068000 0x400>;
0426 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0427 reg-shift = <2>;
0428 reg-io-width = <1>;
0429 clock-names = "baudclk", "apb_pclk";
0430 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
0431 status = "disabled";
0432 };
0433
0434 saradc: saradc@2006c000 {
0435 compatible = "rockchip,saradc";
0436 reg = <0x2006c000 0x100>;
0437 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0438 #io-channel-cells = <1>;
0439 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
0440 clock-names = "saradc", "apb_pclk";
0441 resets = <&cru SRST_SARADC>;
0442 reset-names = "saradc-apb";
0443 status = "disabled";
0444 };
0445
0446 spi0: spi@20070000 {
0447 compatible = "rockchip,rk3066-spi";
0448 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
0449 clock-names = "spiclk", "apb_pclk";
0450 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0451 reg = <0x20070000 0x1000>;
0452 #address-cells = <1>;
0453 #size-cells = <0>;
0454 dmas = <&dmac2 10>, <&dmac2 11>;
0455 dma-names = "tx", "rx";
0456 status = "disabled";
0457 };
0458
0459 spi1: spi@20074000 {
0460 compatible = "rockchip,rk3066-spi";
0461 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
0462 clock-names = "spiclk", "apb_pclk";
0463 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0464 reg = <0x20074000 0x1000>;
0465 #address-cells = <1>;
0466 #size-cells = <0>;
0467 dmas = <&dmac2 12>, <&dmac2 13>;
0468 dma-names = "tx", "rx";
0469 status = "disabled";
0470 };
0471
0472 dmac2: dma-controller@20078000 {
0473 compatible = "arm,pl330", "arm,primecell";
0474 reg = <0x20078000 0x4000>;
0475 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0476 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0477 #dma-cells = <1>;
0478 arm,pl330-broken-no-flushp;
0479 arm,pl330-periph-burst;
0480 clocks = <&cru ACLK_DMA2>;
0481 clock-names = "apb_pclk";
0482 };
0483 };
