0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002
0003 #include <dt-bindings/gpio/gpio.h>
0004 #include <dt-bindings/interrupt-controller/irq.h>
0005 #include <dt-bindings/interrupt-controller/arm-gic.h>
0006 #include <dt-bindings/pinctrl/rockchip.h>
0007 #include <dt-bindings/clock/rk3288-cru.h>
0008 #include <dt-bindings/power/rk3288-power.h>
0009 #include <dt-bindings/thermal/thermal.h>
0010 #include <dt-bindings/soc/rockchip,boot-mode.h>
0011
0012 / {
0013 #address-cells = <2>;
0014 #size-cells = <2>;
0015
0016 compatible = "rockchip,rk3288";
0017
0018 interrupt-parent = <&gic>;
0019
0020 aliases {
0021 ethernet0 = &gmac;
0022 i2c0 = &i2c0;
0023 i2c1 = &i2c1;
0024 i2c2 = &i2c2;
0025 i2c3 = &i2c3;
0026 i2c4 = &i2c4;
0027 i2c5 = &i2c5;
0028 mshc0 = &emmc;
0029 mshc1 = &sdmmc;
0030 mshc2 = &sdio0;
0031 mshc3 = &sdio1;
0032 serial0 = &uart0;
0033 serial1 = &uart1;
0034 serial2 = &uart2;
0035 serial3 = &uart3;
0036 serial4 = &uart4;
0037 spi0 = &spi0;
0038 spi1 = &spi1;
0039 spi2 = &spi2;
0040 };
0041
0042 arm-pmu {
0043 compatible = "arm,cortex-a12-pmu";
0044 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
0045 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
0046 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
0047 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
0048 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0049 };
0050
0051 cpus {
0052 #address-cells = <1>;
0053 #size-cells = <0>;
0054 enable-method = "rockchip,rk3066-smp";
0055 rockchip,pmu = <&pmu>;
0056
0057 cpu0: cpu@500 {
0058 device_type = "cpu";
0059 compatible = "arm,cortex-a12";
0060 reg = <0x500>;
0061 resets = <&cru SRST_CORE0>;
0062 operating-points-v2 = <&cpu_opp_table>;
0063 #cooling-cells = <2>; /* min followed by max */
0064 clock-latency = <40000>;
0065 clocks = <&cru ARMCLK>;
0066 dynamic-power-coefficient = <370>;
0067 };
0068 cpu1: cpu@501 {
0069 device_type = "cpu";
0070 compatible = "arm,cortex-a12";
0071 reg = <0x501>;
0072 resets = <&cru SRST_CORE1>;
0073 operating-points-v2 = <&cpu_opp_table>;
0074 #cooling-cells = <2>; /* min followed by max */
0075 clock-latency = <40000>;
0076 clocks = <&cru ARMCLK>;
0077 dynamic-power-coefficient = <370>;
0078 };
0079 cpu2: cpu@502 {
0080 device_type = "cpu";
0081 compatible = "arm,cortex-a12";
0082 reg = <0x502>;
0083 resets = <&cru SRST_CORE2>;
0084 operating-points-v2 = <&cpu_opp_table>;
0085 #cooling-cells = <2>; /* min followed by max */
0086 clock-latency = <40000>;
0087 clocks = <&cru ARMCLK>;
0088 dynamic-power-coefficient = <370>;
0089 };
0090 cpu3: cpu@503 {
0091 device_type = "cpu";
0092 compatible = "arm,cortex-a12";
0093 reg = <0x503>;
0094 resets = <&cru SRST_CORE3>;
0095 operating-points-v2 = <&cpu_opp_table>;
0096 #cooling-cells = <2>; /* min followed by max */
0097 clock-latency = <40000>;
0098 clocks = <&cru ARMCLK>;
0099 dynamic-power-coefficient = <370>;
0100 };
0101 };
0102
0103 cpu_opp_table: opp-table-0 {
0104 compatible = "operating-points-v2";
0105 opp-shared;
0106
0107 opp-126000000 {
0108 opp-hz = /bits/ 64 <126000000>;
0109 opp-microvolt = <900000>;
0110 };
0111 opp-216000000 {
0112 opp-hz = /bits/ 64 <216000000>;
0113 opp-microvolt = <900000>;
0114 };
0115 opp-312000000 {
0116 opp-hz = /bits/ 64 <312000000>;
0117 opp-microvolt = <900000>;
0118 };
0119 opp-408000000 {
0120 opp-hz = /bits/ 64 <408000000>;
0121 opp-microvolt = <900000>;
0122 };
0123 opp-600000000 {
0124 opp-hz = /bits/ 64 <600000000>;
0125 opp-microvolt = <900000>;
0126 };
0127 opp-696000000 {
0128 opp-hz = /bits/ 64 <696000000>;
0129 opp-microvolt = <950000>;
0130 };
0131 opp-816000000 {
0132 opp-hz = /bits/ 64 <816000000>;
0133 opp-microvolt = <1000000>;
0134 };
0135 opp-1008000000 {
0136 opp-hz = /bits/ 64 <1008000000>;
0137 opp-microvolt = <1050000>;
0138 };
0139 opp-1200000000 {
0140 opp-hz = /bits/ 64 <1200000000>;
0141 opp-microvolt = <1100000>;
0142 };
0143 opp-1416000000 {
0144 opp-hz = /bits/ 64 <1416000000>;
0145 opp-microvolt = <1200000>;
0146 };
0147 opp-1512000000 {
0148 opp-hz = /bits/ 64 <1512000000>;
0149 opp-microvolt = <1300000>;
0150 };
0151 opp-1608000000 {
0152 opp-hz = /bits/ 64 <1608000000>;
0153 opp-microvolt = <1350000>;
0154 };
0155 };
0156
0157 reserved-memory {
0158 #address-cells = <2>;
0159 #size-cells = <2>;
0160 ranges;
0161
0162 /*
0163 * The rk3288 cannot use the memory area above 0xfe000000
0164 * for dma operations for some reason. While there is
0165 * probably a better solution available somewhere, we
0166 * haven't found it yet and while devices with 2GB of ram
0167 * are not affected, this issue prevents 4GB from booting.
0168 * So to make these devices at least bootable, block
0169 * this area for the time being until the real solution
0170 * is found.
0171 */
0172 dma-unusable@fe000000 {
0173 reg = <0x0 0xfe000000 0x0 0x1000000>;
0174 };
0175 };
0176
0177 xin24m: oscillator {
0178 compatible = "fixed-clock";
0179 clock-frequency = <24000000>;
0180 clock-output-names = "xin24m";
0181 #clock-cells = <0>;
0182 };
0183
0184 timer {
0185 compatible = "arm,armv7-timer";
0186 arm,cpu-registers-not-fw-configured;
0187 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0188 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0189 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0190 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0191 clock-frequency = <24000000>;
0192 arm,no-tick-in-suspend;
0193 };
0194
0195 timer: timer@ff810000 {
0196 compatible = "rockchip,rk3288-timer";
0197 reg = <0x0 0xff810000 0x0 0x20>;
0198 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0199 clocks = <&cru PCLK_TIMER>, <&xin24m>;
0200 clock-names = "pclk", "timer";
0201 };
0202
0203 display-subsystem {
0204 compatible = "rockchip,display-subsystem";
0205 ports = <&vopl_out>, <&vopb_out>;
0206 };
0207
0208 sdmmc: mmc@ff0c0000 {
0209 compatible = "rockchip,rk3288-dw-mshc";
0210 max-frequency = <150000000>;
0211 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
0212 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
0213 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
0214 fifo-depth = <0x100>;
0215 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0216 reg = <0x0 0xff0c0000 0x0 0x4000>;
0217 resets = <&cru SRST_MMC0>;
0218 reset-names = "reset";
0219 status = "disabled";
0220 };
0221
0222 sdio0: mmc@ff0d0000 {
0223 compatible = "rockchip,rk3288-dw-mshc";
0224 max-frequency = <150000000>;
0225 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
0226 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
0227 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
0228 fifo-depth = <0x100>;
0229 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0230 reg = <0x0 0xff0d0000 0x0 0x4000>;
0231 resets = <&cru SRST_SDIO0>;
0232 reset-names = "reset";
0233 status = "disabled";
0234 };
0235
0236 sdio1: mmc@ff0e0000 {
0237 compatible = "rockchip,rk3288-dw-mshc";
0238 max-frequency = <150000000>;
0239 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
0240 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
0241 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
0242 fifo-depth = <0x100>;
0243 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0244 reg = <0x0 0xff0e0000 0x0 0x4000>;
0245 resets = <&cru SRST_SDIO1>;
0246 reset-names = "reset";
0247 status = "disabled";
0248 };
0249
0250 emmc: mmc@ff0f0000 {
0251 compatible = "rockchip,rk3288-dw-mshc";
0252 max-frequency = <150000000>;
0253 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
0254 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
0255 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
0256 fifo-depth = <0x100>;
0257 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0258 reg = <0x0 0xff0f0000 0x0 0x4000>;
0259 resets = <&cru SRST_EMMC>;
0260 reset-names = "reset";
0261 status = "disabled";
0262 };
0263
0264 saradc: saradc@ff100000 {
0265 compatible = "rockchip,saradc";
0266 reg = <0x0 0xff100000 0x0 0x100>;
0267 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0268 #io-channel-cells = <1>;
0269 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
0270 clock-names = "saradc", "apb_pclk";
0271 resets = <&cru SRST_SARADC>;
0272 reset-names = "saradc-apb";
0273 status = "disabled";
0274 };
0275
0276 spi0: spi@ff110000 {
0277 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
0278 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
0279 clock-names = "spiclk", "apb_pclk";
0280 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
0281 dma-names = "tx", "rx";
0282 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
0283 pinctrl-names = "default";
0284 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
0285 reg = <0x0 0xff110000 0x0 0x1000>;
0286 #address-cells = <1>;
0287 #size-cells = <0>;
0288 status = "disabled";
0289 };
0290
0291 spi1: spi@ff120000 {
0292 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
0293 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
0294 clock-names = "spiclk", "apb_pclk";
0295 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
0296 dma-names = "tx", "rx";
0297 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0298 pinctrl-names = "default";
0299 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
0300 reg = <0x0 0xff120000 0x0 0x1000>;
0301 #address-cells = <1>;
0302 #size-cells = <0>;
0303 status = "disabled";
0304 };
0305
0306 spi2: spi@ff130000 {
0307 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
0308 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
0309 clock-names = "spiclk", "apb_pclk";
0310 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
0311 dma-names = "tx", "rx";
0312 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0313 pinctrl-names = "default";
0314 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
0315 reg = <0x0 0xff130000 0x0 0x1000>;
0316 #address-cells = <1>;
0317 #size-cells = <0>;
0318 status = "disabled";
0319 };
0320
0321 i2c1: i2c@ff140000 {
0322 compatible = "rockchip,rk3288-i2c";
0323 reg = <0x0 0xff140000 0x0 0x1000>;
0324 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0325 #address-cells = <1>;
0326 #size-cells = <0>;
0327 clock-names = "i2c";
0328 clocks = <&cru PCLK_I2C1>;
0329 pinctrl-names = "default";
0330 pinctrl-0 = <&i2c1_xfer>;
0331 status = "disabled";
0332 };
0333
0334 i2c3: i2c@ff150000 {
0335 compatible = "rockchip,rk3288-i2c";
0336 reg = <0x0 0xff150000 0x0 0x1000>;
0337 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0338 #address-cells = <1>;
0339 #size-cells = <0>;
0340 clock-names = "i2c";
0341 clocks = <&cru PCLK_I2C3>;
0342 pinctrl-names = "default";
0343 pinctrl-0 = <&i2c3_xfer>;
0344 status = "disabled";
0345 };
0346
0347 i2c4: i2c@ff160000 {
0348 compatible = "rockchip,rk3288-i2c";
0349 reg = <0x0 0xff160000 0x0 0x1000>;
0350 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
0351 #address-cells = <1>;
0352 #size-cells = <0>;
0353 clock-names = "i2c";
0354 clocks = <&cru PCLK_I2C4>;
0355 pinctrl-names = "default";
0356 pinctrl-0 = <&i2c4_xfer>;
0357 status = "disabled";
0358 };
0359
0360 i2c5: i2c@ff170000 {
0361 compatible = "rockchip,rk3288-i2c";
0362 reg = <0x0 0xff170000 0x0 0x1000>;
0363 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0364 #address-cells = <1>;
0365 #size-cells = <0>;
0366 clock-names = "i2c";
0367 clocks = <&cru PCLK_I2C5>;
0368 pinctrl-names = "default";
0369 pinctrl-0 = <&i2c5_xfer>;
0370 status = "disabled";
0371 };
0372
0373 uart0: serial@ff180000 {
0374 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
0375 reg = <0x0 0xff180000 0x0 0x100>;
0376 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0377 reg-shift = <2>;
0378 reg-io-width = <4>;
0379 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
0380 clock-names = "baudclk", "apb_pclk";
0381 dmas = <&dmac_peri 1>, <&dmac_peri 2>;
0382 dma-names = "tx", "rx";
0383 pinctrl-names = "default";
0384 pinctrl-0 = <&uart0_xfer>;
0385 status = "disabled";
0386 };
0387
0388 uart1: serial@ff190000 {
0389 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
0390 reg = <0x0 0xff190000 0x0 0x100>;
0391 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0392 reg-shift = <2>;
0393 reg-io-width = <4>;
0394 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
0395 clock-names = "baudclk", "apb_pclk";
0396 dmas = <&dmac_peri 3>, <&dmac_peri 4>;
0397 dma-names = "tx", "rx";
0398 pinctrl-names = "default";
0399 pinctrl-0 = <&uart1_xfer>;
0400 status = "disabled";
0401 };
0402
0403 uart2: serial@ff690000 {
0404 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
0405 reg = <0x0 0xff690000 0x0 0x100>;
0406 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0407 reg-shift = <2>;
0408 reg-io-width = <4>;
0409 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
0410 clock-names = "baudclk", "apb_pclk";
0411 pinctrl-names = "default";
0412 pinctrl-0 = <&uart2_xfer>;
0413 status = "disabled";
0414 };
0415
0416 uart3: serial@ff1b0000 {
0417 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
0418 reg = <0x0 0xff1b0000 0x0 0x100>;
0419 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0420 reg-shift = <2>;
0421 reg-io-width = <4>;
0422 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
0423 clock-names = "baudclk", "apb_pclk";
0424 dmas = <&dmac_peri 7>, <&dmac_peri 8>;
0425 dma-names = "tx", "rx";
0426 pinctrl-names = "default";
0427 pinctrl-0 = <&uart3_xfer>;
0428 status = "disabled";
0429 };
0430
0431 uart4: serial@ff1c0000 {
0432 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
0433 reg = <0x0 0xff1c0000 0x0 0x100>;
0434 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
0435 reg-shift = <2>;
0436 reg-io-width = <4>;
0437 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
0438 clock-names = "baudclk", "apb_pclk";
0439 dmas = <&dmac_peri 9>, <&dmac_peri 10>;
0440 dma-names = "tx", "rx";
0441 pinctrl-names = "default";
0442 pinctrl-0 = <&uart4_xfer>;
0443 status = "disabled";
0444 };
0445
0446 dmac_peri: dma-controller@ff250000 {
0447 compatible = "arm,pl330", "arm,primecell";
0448 reg = <0x0 0xff250000 0x0 0x4000>;
0449 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0450 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0451 #dma-cells = <1>;
0452 arm,pl330-broken-no-flushp;
0453 arm,pl330-periph-burst;
0454 clocks = <&cru ACLK_DMAC2>;
0455 clock-names = "apb_pclk";
0456 };
0457
0458 thermal-zones {
0459 reserve_thermal: reserve-thermal {
0460 polling-delay-passive = <1000>; /* milliseconds */
0461 polling-delay = <5000>; /* milliseconds */
0462
0463 thermal-sensors = <&tsadc 0>;
0464 };
0465
0466 cpu_thermal: cpu-thermal {
0467 polling-delay-passive = <100>; /* milliseconds */
0468 polling-delay = <5000>; /* milliseconds */
0469
0470 thermal-sensors = <&tsadc 1>;
0471
0472 trips {
0473 cpu_alert0: cpu_alert0 {
0474 temperature = <70000>; /* millicelsius */
0475 hysteresis = <2000>; /* millicelsius */
0476 type = "passive";
0477 };
0478 cpu_alert1: cpu_alert1 {
0479 temperature = <75000>; /* millicelsius */
0480 hysteresis = <2000>; /* millicelsius */
0481 type = "passive";
0482 };
0483 cpu_crit: cpu_crit {
0484 temperature = <90000>; /* millicelsius */
0485 hysteresis = <2000>; /* millicelsius */
0486 type = "critical";
0487 };
0488 };
0489
0490 cooling-maps {
0491 map0 {
0492 trip = <&cpu_alert0>;
0493 cooling-device =
0494 <&cpu0 THERMAL_NO_LIMIT 6>,
0495 <&cpu1 THERMAL_NO_LIMIT 6>,
0496 <&cpu2 THERMAL_NO_LIMIT 6>,
0497 <&cpu3 THERMAL_NO_LIMIT 6>;
0498 };
0499 map1 {
0500 trip = <&cpu_alert1>;
0501 cooling-device =
0502 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0503 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0504 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0505 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0506 };
0507 };
0508 };
0509
0510 gpu_thermal: gpu-thermal {
0511 polling-delay-passive = <100>; /* milliseconds */
0512 polling-delay = <5000>; /* milliseconds */
0513
0514 thermal-sensors = <&tsadc 2>;
0515
0516 trips {
0517 gpu_alert0: gpu_alert0 {
0518 temperature = <70000>; /* millicelsius */
0519 hysteresis = <2000>; /* millicelsius */
0520 type = "passive";
0521 };
0522 gpu_crit: gpu_crit {
0523 temperature = <90000>; /* millicelsius */
0524 hysteresis = <2000>; /* millicelsius */
0525 type = "critical";
0526 };
0527 };
0528
0529 cooling-maps {
0530 map0 {
0531 trip = <&gpu_alert0>;
0532 cooling-device =
0533 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0534 };
0535 };
0536 };
0537 };
0538
0539 tsadc: tsadc@ff280000 {
0540 compatible = "rockchip,rk3288-tsadc";
0541 reg = <0x0 0xff280000 0x0 0x100>;
0542 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0543 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
0544 clock-names = "tsadc", "apb_pclk";
0545 resets = <&cru SRST_TSADC>;
0546 reset-names = "tsadc-apb";
0547 pinctrl-names = "init", "default", "sleep";
0548 pinctrl-0 = <&otp_pin>;
0549 pinctrl-1 = <&otp_out>;
0550 pinctrl-2 = <&otp_pin>;
0551 #thermal-sensor-cells = <1>;
0552 rockchip,grf = <&grf>;
0553 rockchip,hw-tshut-temp = <95000>;
0554 status = "disabled";
0555 };
0556
0557 gmac: ethernet@ff290000 {
0558 compatible = "rockchip,rk3288-gmac";
0559 reg = <0x0 0xff290000 0x0 0x10000>;
0560 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
0561 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0562 interrupt-names = "macirq", "eth_wake_irq";
0563 rockchip,grf = <&grf>;
0564 clocks = <&cru SCLK_MAC>,
0565 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
0566 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
0567 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
0568 clock-names = "stmmaceth",
0569 "mac_clk_rx", "mac_clk_tx",
0570 "clk_mac_ref", "clk_mac_refout",
0571 "aclk_mac", "pclk_mac";
0572 resets = <&cru SRST_MAC>;
0573 reset-names = "stmmaceth";
0574 status = "disabled";
0575 };
0576
0577 usb_host0_ehci: usb@ff500000 {
0578 compatible = "generic-ehci";
0579 reg = <0x0 0xff500000 0x0 0x100>;
0580 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0581 clocks = <&cru HCLK_USBHOST0>;
0582 phys = <&usbphy1>;
0583 phy-names = "usb";
0584 status = "disabled";
0585 };
0586
0587 /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */
0588 usb_host0_ohci: usb@ff520000 {
0589 compatible = "generic-ohci";
0590 reg = <0x0 0xff520000 0x0 0x100>;
0591 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
0592 clocks = <&cru HCLK_USBHOST0>;
0593 phys = <&usbphy1>;
0594 phy-names = "usb";
0595 status = "disabled";
0596 };
0597
0598 usb_host1: usb@ff540000 {
0599 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
0600 "snps,dwc2";
0601 reg = <0x0 0xff540000 0x0 0x40000>;
0602 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0603 clocks = <&cru HCLK_USBHOST1>;
0604 clock-names = "otg";
0605 dr_mode = "host";
0606 phys = <&usbphy2>;
0607 phy-names = "usb2-phy";
0608 snps,reset-phy-on-wake;
0609 status = "disabled";
0610 };
0611
0612 usb_otg: usb@ff580000 {
0613 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
0614 "snps,dwc2";
0615 reg = <0x0 0xff580000 0x0 0x40000>;
0616 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0617 clocks = <&cru HCLK_OTG0>;
0618 clock-names = "otg";
0619 dr_mode = "otg";
0620 g-np-tx-fifo-size = <16>;
0621 g-rx-fifo-size = <275>;
0622 g-tx-fifo-size = <256 128 128 64 64 32>;
0623 phys = <&usbphy0>;
0624 phy-names = "usb2-phy";
0625 status = "disabled";
0626 };
0627
0628 usb_hsic: usb@ff5c0000 {
0629 compatible = "generic-ehci";
0630 reg = <0x0 0xff5c0000 0x0 0x100>;
0631 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0632 clocks = <&cru HCLK_HSIC>;
0633 status = "disabled";
0634 };
0635
0636 dmac_bus_ns: dma-controller@ff600000 {
0637 compatible = "arm,pl330", "arm,primecell";
0638 reg = <0x0 0xff600000 0x0 0x4000>;
0639 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0640 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0641 #dma-cells = <1>;
0642 arm,pl330-broken-no-flushp;
0643 arm,pl330-periph-burst;
0644 clocks = <&cru ACLK_DMAC1>;
0645 clock-names = "apb_pclk";
0646 status = "disabled";
0647 };
0648
0649 i2c0: i2c@ff650000 {
0650 compatible = "rockchip,rk3288-i2c";
0651 reg = <0x0 0xff650000 0x0 0x1000>;
0652 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0653 #address-cells = <1>;
0654 #size-cells = <0>;
0655 clock-names = "i2c";
0656 clocks = <&cru PCLK_I2C0>;
0657 pinctrl-names = "default";
0658 pinctrl-0 = <&i2c0_xfer>;
0659 status = "disabled";
0660 };
0661
0662 i2c2: i2c@ff660000 {
0663 compatible = "rockchip,rk3288-i2c";
0664 reg = <0x0 0xff660000 0x0 0x1000>;
0665 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0666 #address-cells = <1>;
0667 #size-cells = <0>;
0668 clock-names = "i2c";
0669 clocks = <&cru PCLK_I2C2>;
0670 pinctrl-names = "default";
0671 pinctrl-0 = <&i2c2_xfer>;
0672 status = "disabled";
0673 };
0674
0675 pwm0: pwm@ff680000 {
0676 compatible = "rockchip,rk3288-pwm";
0677 reg = <0x0 0xff680000 0x0 0x10>;
0678 #pwm-cells = <3>;
0679 pinctrl-names = "default";
0680 pinctrl-0 = <&pwm0_pin>;
0681 clocks = <&cru PCLK_RKPWM>;
0682 status = "disabled";
0683 };
0684
0685 pwm1: pwm@ff680010 {
0686 compatible = "rockchip,rk3288-pwm";
0687 reg = <0x0 0xff680010 0x0 0x10>;
0688 #pwm-cells = <3>;
0689 pinctrl-names = "default";
0690 pinctrl-0 = <&pwm1_pin>;
0691 clocks = <&cru PCLK_RKPWM>;
0692 status = "disabled";
0693 };
0694
0695 pwm2: pwm@ff680020 {
0696 compatible = "rockchip,rk3288-pwm";
0697 reg = <0x0 0xff680020 0x0 0x10>;
0698 #pwm-cells = <3>;
0699 pinctrl-names = "default";
0700 pinctrl-0 = <&pwm2_pin>;
0701 clocks = <&cru PCLK_RKPWM>;
0702 status = "disabled";
0703 };
0704
0705 pwm3: pwm@ff680030 {
0706 compatible = "rockchip,rk3288-pwm";
0707 reg = <0x0 0xff680030 0x0 0x10>;
0708 #pwm-cells = <3>;
0709 pinctrl-names = "default";
0710 pinctrl-0 = <&pwm3_pin>;
0711 clocks = <&cru PCLK_RKPWM>;
0712 status = "disabled";
0713 };
0714
0715 bus_intmem: sram@ff700000 {
0716 compatible = "mmio-sram";
0717 reg = <0x0 0xff700000 0x0 0x18000>;
0718 #address-cells = <1>;
0719 #size-cells = <1>;
0720 ranges = <0 0x0 0xff700000 0x18000>;
0721 smp-sram@0 {
0722 compatible = "rockchip,rk3066-smp-sram";
0723 reg = <0x00 0x10>;
0724 };
0725 };
0726
0727 pmu_sram: sram@ff720000 {
0728 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
0729 reg = <0x0 0xff720000 0x0 0x1000>;
0730 };
0731
0732 pmu: power-management@ff730000 {
0733 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
0734 reg = <0x0 0xff730000 0x0 0x100>;
0735
0736 power: power-controller {
0737 compatible = "rockchip,rk3288-power-controller";
0738 #power-domain-cells = <1>;
0739 #address-cells = <1>;
0740 #size-cells = <0>;
0741
0742 assigned-clocks = <&cru SCLK_EDP_24M>;
0743 assigned-clock-parents = <&xin24m>;
0744
0745 /*
0746 * Note: Although SCLK_* are the working clocks
0747 * of device without including on the NOC, needed for
0748 * synchronous reset.
0749 *
0750 * The clocks on the which NOC:
0751 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
0752 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
0753 * ACLK_RGA is on ACLK_RGA_NIU.
0754 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
0755 *
0756 * Which clock are device clocks:
0757 * clocks devices
0758 * *_IEP IEP:Image Enhancement Processor
0759 * *_ISP ISP:Image Signal Processing
0760 * *_VIP VIP:Video Input Processor
0761 * *_VOP* VOP:Visual Output Processor
0762 * *_RGA RGA
0763 * *_EDP* EDP
0764 * *_LVDS_* LVDS
0765 * *_HDMI HDMI
0766 * *_MIPI_* MIPI
0767 */
0768 power-domain@RK3288_PD_VIO {
0769 reg = <RK3288_PD_VIO>;
0770 clocks = <&cru ACLK_IEP>,
0771 <&cru ACLK_ISP>,
0772 <&cru ACLK_RGA>,
0773 <&cru ACLK_VIP>,
0774 <&cru ACLK_VOP0>,
0775 <&cru ACLK_VOP1>,
0776 <&cru DCLK_VOP0>,
0777 <&cru DCLK_VOP1>,
0778 <&cru HCLK_IEP>,
0779 <&cru HCLK_ISP>,
0780 <&cru HCLK_RGA>,
0781 <&cru HCLK_VIP>,
0782 <&cru HCLK_VOP0>,
0783 <&cru HCLK_VOP1>,
0784 <&cru PCLK_EDP_CTRL>,
0785 <&cru PCLK_HDMI_CTRL>,
0786 <&cru PCLK_LVDS_PHY>,
0787 <&cru PCLK_MIPI_CSI>,
0788 <&cru PCLK_MIPI_DSI0>,
0789 <&cru PCLK_MIPI_DSI1>,
0790 <&cru SCLK_EDP_24M>,
0791 <&cru SCLK_EDP>,
0792 <&cru SCLK_ISP_JPE>,
0793 <&cru SCLK_ISP>,
0794 <&cru SCLK_RGA>;
0795 pm_qos = <&qos_vio0_iep>,
0796 <&qos_vio1_vop>,
0797 <&qos_vio1_isp_w0>,
0798 <&qos_vio1_isp_w1>,
0799 <&qos_vio0_vop>,
0800 <&qos_vio0_vip>,
0801 <&qos_vio2_rga_r>,
0802 <&qos_vio2_rga_w>,
0803 <&qos_vio1_isp_r>;
0804 #power-domain-cells = <0>;
0805 };
0806
0807 /*
0808 * Note: The following 3 are HEVC(H.265) clocks,
0809 * and on the ACLK_HEVC_NIU (NOC).
0810 */
0811 power-domain@RK3288_PD_HEVC {
0812 reg = <RK3288_PD_HEVC>;
0813 clocks = <&cru ACLK_HEVC>,
0814 <&cru SCLK_HEVC_CABAC>,
0815 <&cru SCLK_HEVC_CORE>;
0816 pm_qos = <&qos_hevc_r>,
0817 <&qos_hevc_w>;
0818 #power-domain-cells = <0>;
0819 };
0820
0821 /*
0822 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
0823 * (video endecoder & decoder) clocks that on the
0824 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
0825 */
0826 power-domain@RK3288_PD_VIDEO {
0827 reg = <RK3288_PD_VIDEO>;
0828 clocks = <&cru ACLK_VCODEC>,
0829 <&cru HCLK_VCODEC>;
0830 pm_qos = <&qos_video>;
0831 #power-domain-cells = <0>;
0832 };
0833
0834 /*
0835 * Note: ACLK_GPU is the GPU clock,
0836 * and on the ACLK_GPU_NIU (NOC).
0837 */
0838 power-domain@RK3288_PD_GPU {
0839 reg = <RK3288_PD_GPU>;
0840 clocks = <&cru ACLK_GPU>;
0841 pm_qos = <&qos_gpu_r>,
0842 <&qos_gpu_w>;
0843 #power-domain-cells = <0>;
0844 };
0845 };
0846
0847 reboot-mode {
0848 compatible = "syscon-reboot-mode";
0849 offset = <0x94>;
0850 mode-normal = <BOOT_NORMAL>;
0851 mode-recovery = <BOOT_RECOVERY>;
0852 mode-bootloader = <BOOT_FASTBOOT>;
0853 mode-loader = <BOOT_BL_DOWNLOAD>;
0854 };
0855 };
0856
0857 sgrf: syscon@ff740000 {
0858 compatible = "rockchip,rk3288-sgrf", "syscon";
0859 reg = <0x0 0xff740000 0x0 0x1000>;
0860 };
0861
0862 cru: clock-controller@ff760000 {
0863 compatible = "rockchip,rk3288-cru";
0864 reg = <0x0 0xff760000 0x0 0x1000>;
0865 clocks = <&xin24m>;
0866 clock-names = "xin24m";
0867 rockchip,grf = <&grf>;
0868 #clock-cells = <1>;
0869 #reset-cells = <1>;
0870 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
0871 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
0872 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
0873 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
0874 <&cru PCLK_PERI>;
0875 assigned-clock-rates = <594000000>, <400000000>,
0876 <500000000>, <300000000>,
0877 <150000000>, <75000000>,
0878 <300000000>, <150000000>,
0879 <75000000>;
0880 };
0881
0882 grf: syscon@ff770000 {
0883 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
0884 reg = <0x0 0xff770000 0x0 0x1000>;
0885
0886 edp_phy: edp-phy {
0887 compatible = "rockchip,rk3288-dp-phy";
0888 clocks = <&cru SCLK_EDP_24M>;
0889 clock-names = "24m";
0890 #phy-cells = <0>;
0891 status = "disabled";
0892 };
0893
0894 io_domains: io-domains {
0895 compatible = "rockchip,rk3288-io-voltage-domain";
0896 status = "disabled";
0897 };
0898
0899 usbphy: usbphy {
0900 compatible = "rockchip,rk3288-usb-phy";
0901 #address-cells = <1>;
0902 #size-cells = <0>;
0903 status = "disabled";
0904
0905 usbphy0: usb-phy@320 {
0906 #phy-cells = <0>;
0907 reg = <0x320>;
0908 clocks = <&cru SCLK_OTGPHY0>;
0909 clock-names = "phyclk";
0910 #clock-cells = <0>;
0911 resets = <&cru SRST_USBOTG_PHY>;
0912 reset-names = "phy-reset";
0913 };
0914
0915 usbphy1: usb-phy@334 {
0916 #phy-cells = <0>;
0917 reg = <0x334>;
0918 clocks = <&cru SCLK_OTGPHY1>;
0919 clock-names = "phyclk";
0920 #clock-cells = <0>;
0921 resets = <&cru SRST_USBHOST0_PHY>;
0922 reset-names = "phy-reset";
0923 };
0924
0925 usbphy2: usb-phy@348 {
0926 #phy-cells = <0>;
0927 reg = <0x348>;
0928 clocks = <&cru SCLK_OTGPHY2>;
0929 clock-names = "phyclk";
0930 #clock-cells = <0>;
0931 resets = <&cru SRST_USBHOST1_PHY>;
0932 reset-names = "phy-reset";
0933 };
0934 };
0935 };
0936
0937 wdt: watchdog@ff800000 {
0938 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
0939 reg = <0x0 0xff800000 0x0 0x100>;
0940 clocks = <&cru PCLK_WDT>;
0941 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0942 status = "disabled";
0943 };
0944
0945 spdif: sound@ff88b0000 {
0946 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
0947 reg = <0x0 0xff8b0000 0x0 0x10000>;
0948 #sound-dai-cells = <0>;
0949 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
0950 clock-names = "mclk", "hclk";
0951 dmas = <&dmac_bus_s 3>;
0952 dma-names = "tx";
0953 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
0954 pinctrl-names = "default";
0955 pinctrl-0 = <&spdif_tx>;
0956 rockchip,grf = <&grf>;
0957 status = "disabled";
0958 };
0959
0960 i2s: i2s@ff890000 {
0961 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
0962 reg = <0x0 0xff890000 0x0 0x10000>;
0963 #sound-dai-cells = <0>;
0964 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0965 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
0966 clock-names = "i2s_clk", "i2s_hclk";
0967 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
0968 dma-names = "tx", "rx";
0969 pinctrl-names = "default";
0970 pinctrl-0 = <&i2s0_bus>;
0971 rockchip,playback-channels = <8>;
0972 rockchip,capture-channels = <2>;
0973 status = "disabled";
0974 };
0975
0976 crypto: crypto@ff8a0000 {
0977 compatible = "rockchip,rk3288-crypto";
0978 reg = <0x0 0xff8a0000 0x0 0x4000>;
0979 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0980 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
0981 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
0982 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
0983 resets = <&cru SRST_CRYPTO>;
0984 reset-names = "crypto-rst";
0985 };
0986
0987 iep_mmu: iommu@ff900800 {
0988 compatible = "rockchip,iommu";
0989 reg = <0x0 0xff900800 0x0 0x40>;
0990 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0991 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
0992 clock-names = "aclk", "iface";
0993 #iommu-cells = <0>;
0994 status = "disabled";
0995 };
0996
0997 isp_mmu: iommu@ff914000 {
0998 compatible = "rockchip,iommu";
0999 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1000 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1001 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1002 clock-names = "aclk", "iface";
1003 #iommu-cells = <0>;
1004 rockchip,disable-mmu-reset;
1005 status = "disabled";
1006 };
1007
1008 rga: rga@ff920000 {
1009 compatible = "rockchip,rk3288-rga";
1010 reg = <0x0 0xff920000 0x0 0x180>;
1011 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1012 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1013 clock-names = "aclk", "hclk", "sclk";
1014 power-domains = <&power RK3288_PD_VIO>;
1015 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1016 reset-names = "core", "axi", "ahb";
1017 };
1018
1019 vopb: vop@ff930000 {
1020 compatible = "rockchip,rk3288-vop";
1021 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
1022 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1024 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1025 power-domains = <&power RK3288_PD_VIO>;
1026 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1027 reset-names = "axi", "ahb", "dclk";
1028 iommus = <&vopb_mmu>;
1029 status = "disabled";
1030
1031 vopb_out: port {
1032 #address-cells = <1>;
1033 #size-cells = <0>;
1034
1035 vopb_out_hdmi: endpoint@0 {
1036 reg = <0>;
1037 remote-endpoint = <&hdmi_in_vopb>;
1038 };
1039
1040 vopb_out_edp: endpoint@1 {
1041 reg = <1>;
1042 remote-endpoint = <&edp_in_vopb>;
1043 };
1044
1045 vopb_out_mipi: endpoint@2 {
1046 reg = <2>;
1047 remote-endpoint = <&mipi_in_vopb>;
1048 };
1049
1050 vopb_out_lvds: endpoint@3 {
1051 reg = <3>;
1052 remote-endpoint = <&lvds_in_vopb>;
1053 };
1054 };
1055 };
1056
1057 vopb_mmu: iommu@ff930300 {
1058 compatible = "rockchip,iommu";
1059 reg = <0x0 0xff930300 0x0 0x100>;
1060 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1061 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1062 clock-names = "aclk", "iface";
1063 power-domains = <&power RK3288_PD_VIO>;
1064 #iommu-cells = <0>;
1065 status = "disabled";
1066 };
1067
1068 vopl: vop@ff940000 {
1069 compatible = "rockchip,rk3288-vop";
1070 reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
1071 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1073 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1074 power-domains = <&power RK3288_PD_VIO>;
1075 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1076 reset-names = "axi", "ahb", "dclk";
1077 iommus = <&vopl_mmu>;
1078 status = "disabled";
1079
1080 vopl_out: port {
1081 #address-cells = <1>;
1082 #size-cells = <0>;
1083
1084 vopl_out_hdmi: endpoint@0 {
1085 reg = <0>;
1086 remote-endpoint = <&hdmi_in_vopl>;
1087 };
1088
1089 vopl_out_edp: endpoint@1 {
1090 reg = <1>;
1091 remote-endpoint = <&edp_in_vopl>;
1092 };
1093
1094 vopl_out_mipi: endpoint@2 {
1095 reg = <2>;
1096 remote-endpoint = <&mipi_in_vopl>;
1097 };
1098
1099 vopl_out_lvds: endpoint@3 {
1100 reg = <3>;
1101 remote-endpoint = <&lvds_in_vopl>;
1102 };
1103 };
1104 };
1105
1106 vopl_mmu: iommu@ff940300 {
1107 compatible = "rockchip,iommu";
1108 reg = <0x0 0xff940300 0x0 0x100>;
1109 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1110 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1111 clock-names = "aclk", "iface";
1112 power-domains = <&power RK3288_PD_VIO>;
1113 #iommu-cells = <0>;
1114 status = "disabled";
1115 };
1116
1117 mipi_dsi: mipi@ff960000 {
1118 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1119 reg = <0x0 0xff960000 0x0 0x4000>;
1120 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1121 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1122 clock-names = "ref", "pclk";
1123 power-domains = <&power RK3288_PD_VIO>;
1124 rockchip,grf = <&grf>;
1125 status = "disabled";
1126
1127 ports {
1128 mipi_in: port {
1129 #address-cells = <1>;
1130 #size-cells = <0>;
1131 mipi_in_vopb: endpoint@0 {
1132 reg = <0>;
1133 remote-endpoint = <&vopb_out_mipi>;
1134 };
1135 mipi_in_vopl: endpoint@1 {
1136 reg = <1>;
1137 remote-endpoint = <&vopl_out_mipi>;
1138 };
1139 };
1140 };
1141 };
1142
1143 lvds: lvds@ff96c000 {
1144 compatible = "rockchip,rk3288-lvds";
1145 reg = <0x0 0xff96c000 0x0 0x4000>;
1146 clocks = <&cru PCLK_LVDS_PHY>;
1147 clock-names = "pclk_lvds";
1148 pinctrl-names = "lcdc";
1149 pinctrl-0 = <&lcdc_ctl>;
1150 power-domains = <&power RK3288_PD_VIO>;
1151 rockchip,grf = <&grf>;
1152 status = "disabled";
1153
1154 ports {
1155 #address-cells = <1>;
1156 #size-cells = <0>;
1157
1158 lvds_in: port@0 {
1159 reg = <0>;
1160
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1163
1164 lvds_in_vopb: endpoint@0 {
1165 reg = <0>;
1166 remote-endpoint = <&vopb_out_lvds>;
1167 };
1168 lvds_in_vopl: endpoint@1 {
1169 reg = <1>;
1170 remote-endpoint = <&vopl_out_lvds>;
1171 };
1172 };
1173 };
1174 };
1175
1176 edp: dp@ff970000 {
1177 compatible = "rockchip,rk3288-dp";
1178 reg = <0x0 0xff970000 0x0 0x4000>;
1179 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1180 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1181 clock-names = "dp", "pclk";
1182 phys = <&edp_phy>;
1183 phy-names = "dp";
1184 resets = <&cru SRST_EDP>;
1185 reset-names = "dp";
1186 rockchip,grf = <&grf>;
1187 status = "disabled";
1188
1189 ports {
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1192 edp_in: port@0 {
1193 reg = <0>;
1194 #address-cells = <1>;
1195 #size-cells = <0>;
1196 edp_in_vopb: endpoint@0 {
1197 reg = <0>;
1198 remote-endpoint = <&vopb_out_edp>;
1199 };
1200 edp_in_vopl: endpoint@1 {
1201 reg = <1>;
1202 remote-endpoint = <&vopl_out_edp>;
1203 };
1204 };
1205 };
1206 };
1207
1208 hdmi: hdmi@ff980000 {
1209 compatible = "rockchip,rk3288-dw-hdmi";
1210 reg = <0x0 0xff980000 0x0 0x20000>;
1211 reg-io-width = <4>;
1212 #sound-dai-cells = <0>;
1213 rockchip,grf = <&grf>;
1214 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1215 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1216 clock-names = "iahb", "isfr", "cec";
1217 power-domains = <&power RK3288_PD_VIO>;
1218 status = "disabled";
1219
1220 ports {
1221 hdmi_in: port {
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1224 hdmi_in_vopb: endpoint@0 {
1225 reg = <0>;
1226 remote-endpoint = <&vopb_out_hdmi>;
1227 };
1228 hdmi_in_vopl: endpoint@1 {
1229 reg = <1>;
1230 remote-endpoint = <&vopl_out_hdmi>;
1231 };
1232 };
1233 };
1234 };
1235
1236 vpu: video-codec@ff9a0000 {
1237 compatible = "rockchip,rk3288-vpu";
1238 reg = <0x0 0xff9a0000 0x0 0x800>;
1239 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1241 interrupt-names = "vepu", "vdpu";
1242 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1243 clock-names = "aclk", "hclk";
1244 iommus = <&vpu_mmu>;
1245 power-domains = <&power RK3288_PD_VIDEO>;
1246 };
1247
1248 vpu_mmu: iommu@ff9a0800 {
1249 compatible = "rockchip,iommu";
1250 reg = <0x0 0xff9a0800 0x0 0x100>;
1251 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1252 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1253 clock-names = "aclk", "iface";
1254 #iommu-cells = <0>;
1255 power-domains = <&power RK3288_PD_VIDEO>;
1256 };
1257
1258 hevc_mmu: iommu@ff9c0440 {
1259 compatible = "rockchip,iommu";
1260 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1261 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1263 clock-names = "aclk", "iface";
1264 #iommu-cells = <0>;
1265 status = "disabled";
1266 };
1267
1268 gpu: gpu@ffa30000 {
1269 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1270 reg = <0x0 0xffa30000 0x0 0x10000>;
1271 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1274 interrupt-names = "job", "mmu", "gpu";
1275 clocks = <&cru ACLK_GPU>;
1276 operating-points-v2 = <&gpu_opp_table>;
1277 #cooling-cells = <2>; /* min followed by max */
1278 power-domains = <&power RK3288_PD_GPU>;
1279 status = "disabled";
1280 };
1281
1282 gpu_opp_table: opp-table-1 {
1283 compatible = "operating-points-v2";
1284
1285 opp-100000000 {
1286 opp-hz = /bits/ 64 <100000000>;
1287 opp-microvolt = <950000>;
1288 };
1289 opp-200000000 {
1290 opp-hz = /bits/ 64 <200000000>;
1291 opp-microvolt = <950000>;
1292 };
1293 opp-300000000 {
1294 opp-hz = /bits/ 64 <300000000>;
1295 opp-microvolt = <1000000>;
1296 };
1297 opp-400000000 {
1298 opp-hz = /bits/ 64 <400000000>;
1299 opp-microvolt = <1100000>;
1300 };
1301 opp-600000000 {
1302 opp-hz = /bits/ 64 <600000000>;
1303 opp-microvolt = <1250000>;
1304 };
1305 };
1306
1307 qos_gpu_r: qos@ffaa0000 {
1308 compatible = "rockchip,rk3288-qos", "syscon";
1309 reg = <0x0 0xffaa0000 0x0 0x20>;
1310 };
1311
1312 qos_gpu_w: qos@ffaa0080 {
1313 compatible = "rockchip,rk3288-qos", "syscon";
1314 reg = <0x0 0xffaa0080 0x0 0x20>;
1315 };
1316
1317 qos_vio1_vop: qos@ffad0000 {
1318 compatible = "rockchip,rk3288-qos", "syscon";
1319 reg = <0x0 0xffad0000 0x0 0x20>;
1320 };
1321
1322 qos_vio1_isp_w0: qos@ffad0100 {
1323 compatible = "rockchip,rk3288-qos", "syscon";
1324 reg = <0x0 0xffad0100 0x0 0x20>;
1325 };
1326
1327 qos_vio1_isp_w1: qos@ffad0180 {
1328 compatible = "rockchip,rk3288-qos", "syscon";
1329 reg = <0x0 0xffad0180 0x0 0x20>;
1330 };
1331
1332 qos_vio0_vop: qos@ffad0400 {
1333 compatible = "rockchip,rk3288-qos", "syscon";
1334 reg = <0x0 0xffad0400 0x0 0x20>;
1335 };
1336
1337 qos_vio0_vip: qos@ffad0480 {
1338 compatible = "rockchip,rk3288-qos", "syscon";
1339 reg = <0x0 0xffad0480 0x0 0x20>;
1340 };
1341
1342 qos_vio0_iep: qos@ffad0500 {
1343 compatible = "rockchip,rk3288-qos", "syscon";
1344 reg = <0x0 0xffad0500 0x0 0x20>;
1345 };
1346
1347 qos_vio2_rga_r: qos@ffad0800 {
1348 compatible = "rockchip,rk3288-qos", "syscon";
1349 reg = <0x0 0xffad0800 0x0 0x20>;
1350 };
1351
1352 qos_vio2_rga_w: qos@ffad0880 {
1353 compatible = "rockchip,rk3288-qos", "syscon";
1354 reg = <0x0 0xffad0880 0x0 0x20>;
1355 };
1356
1357 qos_vio1_isp_r: qos@ffad0900 {
1358 compatible = "rockchip,rk3288-qos", "syscon";
1359 reg = <0x0 0xffad0900 0x0 0x20>;
1360 };
1361
1362 qos_video: qos@ffae0000 {
1363 compatible = "rockchip,rk3288-qos", "syscon";
1364 reg = <0x0 0xffae0000 0x0 0x20>;
1365 };
1366
1367 qos_hevc_r: qos@ffaf0000 {
1368 compatible = "rockchip,rk3288-qos", "syscon";
1369 reg = <0x0 0xffaf0000 0x0 0x20>;
1370 };
1371
1372 qos_hevc_w: qos@ffaf0080 {
1373 compatible = "rockchip,rk3288-qos", "syscon";
1374 reg = <0x0 0xffaf0080 0x0 0x20>;
1375 };
1376
1377 dmac_bus_s: dma-controller@ffb20000 {
1378 compatible = "arm,pl330", "arm,primecell";
1379 reg = <0x0 0xffb20000 0x0 0x4000>;
1380 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1382 #dma-cells = <1>;
1383 arm,pl330-broken-no-flushp;
1384 arm,pl330-periph-burst;
1385 clocks = <&cru ACLK_DMAC1>;
1386 clock-names = "apb_pclk";
1387 };
1388
1389 efuse: efuse@ffb40000 {
1390 compatible = "rockchip,rk3288-efuse";
1391 reg = <0x0 0xffb40000 0x0 0x20>;
1392 #address-cells = <1>;
1393 #size-cells = <1>;
1394 clocks = <&cru PCLK_EFUSE256>;
1395 clock-names = "pclk_efuse";
1396
1397 cpu_id: cpu-id@7 {
1398 reg = <0x07 0x10>;
1399 };
1400 cpu_leakage: cpu_leakage@17 {
1401 reg = <0x17 0x1>;
1402 };
1403 };
1404
1405 gic: interrupt-controller@ffc01000 {
1406 compatible = "arm,gic-400";
1407 interrupt-controller;
1408 #interrupt-cells = <3>;
1409 #address-cells = <0>;
1410
1411 reg = <0x0 0xffc01000 0x0 0x1000>,
1412 <0x0 0xffc02000 0x0 0x2000>,
1413 <0x0 0xffc04000 0x0 0x2000>,
1414 <0x0 0xffc06000 0x0 0x2000>;
1415 interrupts = <GIC_PPI 9 0xf04>;
1416 };
1417
1418 pinctrl: pinctrl {
1419 compatible = "rockchip,rk3288-pinctrl";
1420 rockchip,grf = <&grf>;
1421 rockchip,pmu = <&pmu>;
1422 #address-cells = <2>;
1423 #size-cells = <2>;
1424 ranges;
1425
1426 gpio0: gpio@ff750000 {
1427 compatible = "rockchip,gpio-bank";
1428 reg = <0x0 0xff750000 0x0 0x100>;
1429 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1430 clocks = <&cru PCLK_GPIO0>;
1431
1432 gpio-controller;
1433 #gpio-cells = <2>;
1434
1435 interrupt-controller;
1436 #interrupt-cells = <2>;
1437 };
1438
1439 gpio1: gpio@ff780000 {
1440 compatible = "rockchip,gpio-bank";
1441 reg = <0x0 0xff780000 0x0 0x100>;
1442 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1443 clocks = <&cru PCLK_GPIO1>;
1444
1445 gpio-controller;
1446 #gpio-cells = <2>;
1447
1448 interrupt-controller;
1449 #interrupt-cells = <2>;
1450 };
1451
1452 gpio2: gpio@ff790000 {
1453 compatible = "rockchip,gpio-bank";
1454 reg = <0x0 0xff790000 0x0 0x100>;
1455 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1456 clocks = <&cru PCLK_GPIO2>;
1457
1458 gpio-controller;
1459 #gpio-cells = <2>;
1460
1461 interrupt-controller;
1462 #interrupt-cells = <2>;
1463 };
1464
1465 gpio3: gpio@ff7a0000 {
1466 compatible = "rockchip,gpio-bank";
1467 reg = <0x0 0xff7a0000 0x0 0x100>;
1468 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1469 clocks = <&cru PCLK_GPIO3>;
1470
1471 gpio-controller;
1472 #gpio-cells = <2>;
1473
1474 interrupt-controller;
1475 #interrupt-cells = <2>;
1476 };
1477
1478 gpio4: gpio@ff7b0000 {
1479 compatible = "rockchip,gpio-bank";
1480 reg = <0x0 0xff7b0000 0x0 0x100>;
1481 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1482 clocks = <&cru PCLK_GPIO4>;
1483
1484 gpio-controller;
1485 #gpio-cells = <2>;
1486
1487 interrupt-controller;
1488 #interrupt-cells = <2>;
1489 };
1490
1491 gpio5: gpio@ff7c0000 {
1492 compatible = "rockchip,gpio-bank";
1493 reg = <0x0 0xff7c0000 0x0 0x100>;
1494 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1495 clocks = <&cru PCLK_GPIO5>;
1496
1497 gpio-controller;
1498 #gpio-cells = <2>;
1499
1500 interrupt-controller;
1501 #interrupt-cells = <2>;
1502 };
1503
1504 gpio6: gpio@ff7d0000 {
1505 compatible = "rockchip,gpio-bank";
1506 reg = <0x0 0xff7d0000 0x0 0x100>;
1507 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1508 clocks = <&cru PCLK_GPIO6>;
1509
1510 gpio-controller;
1511 #gpio-cells = <2>;
1512
1513 interrupt-controller;
1514 #interrupt-cells = <2>;
1515 };
1516
1517 gpio7: gpio@ff7e0000 {
1518 compatible = "rockchip,gpio-bank";
1519 reg = <0x0 0xff7e0000 0x0 0x100>;
1520 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1521 clocks = <&cru PCLK_GPIO7>;
1522
1523 gpio-controller;
1524 #gpio-cells = <2>;
1525
1526 interrupt-controller;
1527 #interrupt-cells = <2>;
1528 };
1529
1530 gpio8: gpio@ff7f0000 {
1531 compatible = "rockchip,gpio-bank";
1532 reg = <0x0 0xff7f0000 0x0 0x100>;
1533 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1534 clocks = <&cru PCLK_GPIO8>;
1535
1536 gpio-controller;
1537 #gpio-cells = <2>;
1538
1539 interrupt-controller;
1540 #interrupt-cells = <2>;
1541 };
1542
1543 hdmi {
1544 hdmi_cec_c0: hdmi-cec-c0 {
1545 rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
1546 };
1547
1548 hdmi_cec_c7: hdmi-cec-c7 {
1549 rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>;
1550 };
1551
1552 hdmi_ddc: hdmi-ddc {
1553 rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
1554 <7 RK_PC4 2 &pcfg_pull_none>;
1555 };
1556
1557 hdmi_ddc_unwedge: hdmi-ddc-unwedge {
1558 rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
1559 <7 RK_PC4 2 &pcfg_pull_none>;
1560 };
1561 };
1562
1563 pcfg_output_low: pcfg-output-low {
1564 output-low;
1565 };
1566
1567 pcfg_pull_up: pcfg-pull-up {
1568 bias-pull-up;
1569 };
1570
1571 pcfg_pull_down: pcfg-pull-down {
1572 bias-pull-down;
1573 };
1574
1575 pcfg_pull_none: pcfg-pull-none {
1576 bias-disable;
1577 };
1578
1579 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1580 bias-disable;
1581 drive-strength = <12>;
1582 };
1583
1584 suspend {
1585 global_pwroff: global-pwroff {
1586 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
1587 };
1588
1589 ddrio_pwroff: ddrio-pwroff {
1590 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
1591 };
1592
1593 ddr0_retention: ddr0-retention {
1594 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
1595 };
1596
1597 ddr1_retention: ddr1-retention {
1598 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
1599 };
1600 };
1601
1602 edp {
1603 edp_hpd: edp-hpd {
1604 rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
1605 };
1606 };
1607
1608 i2c0 {
1609 i2c0_xfer: i2c0-xfer {
1610 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
1611 <0 RK_PC0 1 &pcfg_pull_none>;
1612 };
1613 };
1614
1615 i2c1 {
1616 i2c1_xfer: i2c1-xfer {
1617 rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
1618 <8 RK_PA5 1 &pcfg_pull_none>;
1619 };
1620 };
1621
1622 i2c2 {
1623 i2c2_xfer: i2c2-xfer {
1624 rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
1625 <6 RK_PB2 1 &pcfg_pull_none>;
1626 };
1627 };
1628
1629 i2c3 {
1630 i2c3_xfer: i2c3-xfer {
1631 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
1632 <2 RK_PC1 1 &pcfg_pull_none>;
1633 };
1634 };
1635
1636 i2c4 {
1637 i2c4_xfer: i2c4-xfer {
1638 rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
1639 <7 RK_PC2 1 &pcfg_pull_none>;
1640 };
1641 };
1642
1643 i2c5 {
1644 i2c5_xfer: i2c5-xfer {
1645 rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
1646 <7 RK_PC4 1 &pcfg_pull_none>;
1647 };
1648 };
1649
1650 i2s0 {
1651 i2s0_bus: i2s0-bus {
1652 rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
1653 <6 RK_PA1 1 &pcfg_pull_none>,
1654 <6 RK_PA2 1 &pcfg_pull_none>,
1655 <6 RK_PA3 1 &pcfg_pull_none>,
1656 <6 RK_PA4 1 &pcfg_pull_none>,
1657 <6 RK_PB0 1 &pcfg_pull_none>;
1658 };
1659 };
1660
1661 lcdc {
1662 lcdc_ctl: lcdc-ctl {
1663 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
1664 <1 RK_PD1 1 &pcfg_pull_none>,
1665 <1 RK_PD2 1 &pcfg_pull_none>,
1666 <1 RK_PD3 1 &pcfg_pull_none>;
1667 };
1668 };
1669
1670 sdmmc {
1671 sdmmc_clk: sdmmc-clk {
1672 rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
1673 };
1674
1675 sdmmc_cmd: sdmmc-cmd {
1676 rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
1677 };
1678
1679 sdmmc_cd: sdmmc-cd {
1680 rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
1681 };
1682
1683 sdmmc_bus1: sdmmc-bus1 {
1684 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
1685 };
1686
1687 sdmmc_bus4: sdmmc-bus4 {
1688 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
1689 <6 RK_PC1 1 &pcfg_pull_up>,
1690 <6 RK_PC2 1 &pcfg_pull_up>,
1691 <6 RK_PC3 1 &pcfg_pull_up>;
1692 };
1693 };
1694
1695 sdio0 {
1696 sdio0_bus1: sdio0-bus1 {
1697 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
1698 };
1699
1700 sdio0_bus4: sdio0-bus4 {
1701 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
1702 <4 RK_PC5 1 &pcfg_pull_up>,
1703 <4 RK_PC6 1 &pcfg_pull_up>,
1704 <4 RK_PC7 1 &pcfg_pull_up>;
1705 };
1706
1707 sdio0_cmd: sdio0-cmd {
1708 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
1709 };
1710
1711 sdio0_clk: sdio0-clk {
1712 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
1713 };
1714
1715 sdio0_cd: sdio0-cd {
1716 rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
1717 };
1718
1719 sdio0_wp: sdio0-wp {
1720 rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
1721 };
1722
1723 sdio0_pwr: sdio0-pwr {
1724 rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
1725 };
1726
1727 sdio0_bkpwr: sdio0-bkpwr {
1728 rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
1729 };
1730
1731 sdio0_int: sdio0-int {
1732 rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
1733 };
1734 };
1735
1736 sdio1 {
1737 sdio1_bus1: sdio1-bus1 {
1738 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
1739 };
1740
1741 sdio1_bus4: sdio1-bus4 {
1742 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
1743 <3 RK_PD1 4 &pcfg_pull_up>,
1744 <3 RK_PD2 4 &pcfg_pull_up>,
1745 <3 RK_PD3 4 &pcfg_pull_up>;
1746 };
1747
1748 sdio1_cd: sdio1-cd {
1749 rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
1750 };
1751
1752 sdio1_wp: sdio1-wp {
1753 rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
1754 };
1755
1756 sdio1_bkpwr: sdio1-bkpwr {
1757 rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
1758 };
1759
1760 sdio1_int: sdio1-int {
1761 rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
1762 };
1763
1764 sdio1_cmd: sdio1-cmd {
1765 rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
1766 };
1767
1768 sdio1_clk: sdio1-clk {
1769 rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
1770 };
1771
1772 sdio1_pwr: sdio1-pwr {
1773 rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
1774 };
1775 };
1776
1777 emmc {
1778 emmc_clk: emmc-clk {
1779 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
1780 };
1781
1782 emmc_cmd: emmc-cmd {
1783 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
1784 };
1785
1786 emmc_pwr: emmc-pwr {
1787 rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
1788 };
1789
1790 emmc_bus1: emmc-bus1 {
1791 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
1792 };
1793
1794 emmc_bus4: emmc-bus4 {
1795 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1796 <3 RK_PA1 2 &pcfg_pull_up>,
1797 <3 RK_PA2 2 &pcfg_pull_up>,
1798 <3 RK_PA3 2 &pcfg_pull_up>;
1799 };
1800
1801 emmc_bus8: emmc-bus8 {
1802 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1803 <3 RK_PA1 2 &pcfg_pull_up>,
1804 <3 RK_PA2 2 &pcfg_pull_up>,
1805 <3 RK_PA3 2 &pcfg_pull_up>,
1806 <3 RK_PA4 2 &pcfg_pull_up>,
1807 <3 RK_PA5 2 &pcfg_pull_up>,
1808 <3 RK_PA6 2 &pcfg_pull_up>,
1809 <3 RK_PA7 2 &pcfg_pull_up>;
1810 };
1811 };
1812
1813 spi0 {
1814 spi0_clk: spi0-clk {
1815 rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
1816 };
1817 spi0_cs0: spi0-cs0 {
1818 rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
1819 };
1820 spi0_tx: spi0-tx {
1821 rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
1822 };
1823 spi0_rx: spi0-rx {
1824 rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
1825 };
1826 spi0_cs1: spi0-cs1 {
1827 rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
1828 };
1829 };
1830 spi1 {
1831 spi1_clk: spi1-clk {
1832 rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
1833 };
1834 spi1_cs0: spi1-cs0 {
1835 rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
1836 };
1837 spi1_rx: spi1-rx {
1838 rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
1839 };
1840 spi1_tx: spi1-tx {
1841 rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
1842 };
1843 };
1844
1845 spi2 {
1846 spi2_cs1: spi2-cs1 {
1847 rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
1848 };
1849 spi2_clk: spi2-clk {
1850 rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
1851 };
1852 spi2_cs0: spi2-cs0 {
1853 rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
1854 };
1855 spi2_rx: spi2-rx {
1856 rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
1857 };
1858 spi2_tx: spi2-tx {
1859 rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
1860 };
1861 };
1862
1863 uart0 {
1864 uart0_xfer: uart0-xfer {
1865 rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
1866 <4 RK_PC1 1 &pcfg_pull_none>;
1867 };
1868
1869 uart0_cts: uart0-cts {
1870 rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
1871 };
1872
1873 uart0_rts: uart0-rts {
1874 rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
1875 };
1876 };
1877
1878 uart1 {
1879 uart1_xfer: uart1-xfer {
1880 rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
1881 <5 RK_PB1 1 &pcfg_pull_none>;
1882 };
1883
1884 uart1_cts: uart1-cts {
1885 rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
1886 };
1887
1888 uart1_rts: uart1-rts {
1889 rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
1890 };
1891 };
1892
1893 uart2 {
1894 uart2_xfer: uart2-xfer {
1895 rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
1896 <7 RK_PC7 1 &pcfg_pull_none>;
1897 };
1898 /* no rts / cts for uart2 */
1899 };
1900
1901 uart3 {
1902 uart3_xfer: uart3-xfer {
1903 rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
1904 <7 RK_PB0 1 &pcfg_pull_none>;
1905 };
1906
1907 uart3_cts: uart3-cts {
1908 rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
1909 };
1910
1911 uart3_rts: uart3-rts {
1912 rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
1913 };
1914 };
1915
1916 uart4 {
1917 uart4_xfer: uart4-xfer {
1918 rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
1919 <5 RK_PB6 3 &pcfg_pull_none>;
1920 };
1921
1922 uart4_cts: uart4-cts {
1923 rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
1924 };
1925
1926 uart4_rts: uart4-rts {
1927 rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
1928 };
1929 };
1930
1931 tsadc {
1932 otp_pin: otp-pin {
1933 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1934 };
1935
1936 otp_out: otp-out {
1937 rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
1938 };
1939 };
1940
1941 pwm0 {
1942 pwm0_pin: pwm0-pin {
1943 rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
1944 };
1945 };
1946
1947 pwm1 {
1948 pwm1_pin: pwm1-pin {
1949 rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
1950 };
1951 };
1952
1953 pwm2 {
1954 pwm2_pin: pwm2-pin {
1955 rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
1956 };
1957 };
1958
1959 pwm3 {
1960 pwm3_pin: pwm3-pin {
1961 rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
1962 };
1963 };
1964
1965 gmac {
1966 rgmii_pins: rgmii-pins {
1967 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1968 <3 RK_PD7 3 &pcfg_pull_none>,
1969 <3 RK_PD2 3 &pcfg_pull_none>,
1970 <3 RK_PD3 3 &pcfg_pull_none>,
1971 <3 RK_PD4 3 &pcfg_pull_none_12ma>,
1972 <3 RK_PD5 3 &pcfg_pull_none_12ma>,
1973 <3 RK_PD0 3 &pcfg_pull_none_12ma>,
1974 <3 RK_PD1 3 &pcfg_pull_none_12ma>,
1975 <4 RK_PA0 3 &pcfg_pull_none>,
1976 <4 RK_PA5 3 &pcfg_pull_none>,
1977 <4 RK_PA6 3 &pcfg_pull_none>,
1978 <4 RK_PB1 3 &pcfg_pull_none_12ma>,
1979 <4 RK_PA4 3 &pcfg_pull_none_12ma>,
1980 <4 RK_PA1 3 &pcfg_pull_none>,
1981 <4 RK_PA3 3 &pcfg_pull_none>;
1982 };
1983
1984 rmii_pins: rmii-pins {
1985 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1986 <3 RK_PD7 3 &pcfg_pull_none>,
1987 <3 RK_PD4 3 &pcfg_pull_none>,
1988 <3 RK_PD5 3 &pcfg_pull_none>,
1989 <4 RK_PA0 3 &pcfg_pull_none>,
1990 <4 RK_PA5 3 &pcfg_pull_none>,
1991 <4 RK_PA4 3 &pcfg_pull_none>,
1992 <4 RK_PA1 3 &pcfg_pull_none>,
1993 <4 RK_PA2 3 &pcfg_pull_none>,
1994 <4 RK_PA3 3 &pcfg_pull_none>;
1995 };
1996 };
1997
1998 spdif {
1999 spdif_tx: spdif-tx {
2000 rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
2001 };
2002 };
2003 };
2004 };
