0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Google Veyron (and derivatives) board device tree source
0004 *
0005 * Copyright 2015 Google, Inc
0006 */
0007
0008 #include <dt-bindings/clock/rockchip,rk808.h>
0009 #include <dt-bindings/input/input.h>
0010 #include "rk3288.dtsi"
0011
0012 / {
0013 chosen {
0014 stdout-path = "serial2:115200n8";
0015 };
0016
0017 /*
0018 * The default coreboot on veyron devices ignores memory@0 nodes
0019 * and would instead create another memory node.
0020 */
0021 memory {
0022 device_type = "memory";
0023 reg = <0x0 0x0 0x0 0x80000000>;
0024 };
0025
0026
0027 power_button: power-button {
0028 compatible = "gpio-keys";
0029 pinctrl-names = "default";
0030 pinctrl-0 = <&pwr_key_l>;
0031
0032 key-power {
0033 label = "Power";
0034 gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
0035 linux,code = <KEY_POWER>;
0036 debounce-interval = <100>;
0037 wakeup-source;
0038 };
0039 };
0040
0041 gpio-restart {
0042 compatible = "gpio-restart";
0043 gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
0044 pinctrl-names = "default";
0045 pinctrl-0 = <&ap_warm_reset_h>;
0046 priority = <200>;
0047 };
0048
0049 emmc_pwrseq: emmc-pwrseq {
0050 compatible = "mmc-pwrseq-emmc";
0051 pinctrl-0 = <&emmc_reset>;
0052 pinctrl-names = "default";
0053 reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
0054 };
0055
0056 sdio_pwrseq: sdio-pwrseq {
0057 compatible = "mmc-pwrseq-simple";
0058 clocks = <&rk808 RK808_CLKOUT1>;
0059 clock-names = "ext_clock";
0060 pinctrl-names = "default";
0061 pinctrl-0 = <&wifi_enable_h>;
0062
0063 /*
0064 * Depending on the actual card populated GPIO4 D4
0065 * correspond to one of these signals on the module:
0066 *
0067 * D4:
0068 * - SDIO_RESET_L_WL_REG_ON
0069 * - PDN (power down when low)
0070 */
0071 reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
0072 };
0073
0074 vcc_5v: vcc-5v {
0075 compatible = "regulator-fixed";
0076 regulator-name = "vcc_5v";
0077 regulator-always-on;
0078 regulator-boot-on;
0079 regulator-min-microvolt = <5000000>;
0080 regulator-max-microvolt = <5000000>;
0081 };
0082
0083 vcc33_sys: vcc33-sys {
0084 compatible = "regulator-fixed";
0085 regulator-name = "vcc33_sys";
0086 regulator-always-on;
0087 regulator-boot-on;
0088 regulator-min-microvolt = <3300000>;
0089 regulator-max-microvolt = <3300000>;
0090 };
0091
0092 vcc50_hdmi: vcc50-hdmi {
0093 compatible = "regulator-fixed";
0094 regulator-name = "vcc50_hdmi";
0095 regulator-always-on;
0096 regulator-boot-on;
0097 vin-supply = <&vcc_5v>;
0098 };
0099
0100 vdd_logic: vdd-logic {
0101 compatible = "pwm-regulator";
0102 regulator-name = "vdd_logic";
0103
0104 pwms = <&pwm1 0 1994 0>;
0105 pwm-supply = <&vcc33_sys>;
0106
0107 pwm-dutycycle-range = <0x7b 0>;
0108 pwm-dutycycle-unit = <0x94>;
0109
0110 regulator-always-on;
0111 regulator-boot-on;
0112 regulator-min-microvolt = <950000>;
0113 regulator-max-microvolt = <1350000>;
0114 regulator-ramp-delay = <4000>;
0115 };
0116 };
0117
0118 &cpu0 {
0119 cpu0-supply = <&vdd_cpu>;
0120 };
0121
0122 &cpu_crit {
0123 temperature = <100000>;
0124 };
0125
0126 /* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
0127 &cpu_opp_table {
0128 /delete-node/ opp-312000000;
0129
0130 opp-1512000000 {
0131 opp-microvolt = <1250000>;
0132 };
0133 opp-1608000000 {
0134 opp-microvolt = <1300000>;
0135 };
0136 opp-1704000000 {
0137 opp-hz = /bits/ 64 <1704000000>;
0138 opp-microvolt = <1350000>;
0139 };
0140 opp-1800000000 {
0141 opp-hz = /bits/ 64 <1800000000>;
0142 opp-microvolt = <1400000>;
0143 };
0144 };
0145
0146 &emmc {
0147 status = "okay";
0148
0149 bus-width = <8>;
0150 cap-mmc-highspeed;
0151 rockchip,default-sample-phase = <158>;
0152 disable-wp;
0153 mmc-hs200-1_8v;
0154 mmc-pwrseq = <&emmc_pwrseq>;
0155 non-removable;
0156 pinctrl-names = "default";
0157 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
0158 };
0159
0160 &gpu {
0161 mali-supply = <&vdd_gpu>;
0162 status = "okay";
0163 };
0164
0165 &gpu_alert0 {
0166 temperature = <72500>;
0167 };
0168
0169 &gpu_crit {
0170 temperature = <100000>;
0171 };
0172
0173 &hdmi {
0174 pinctrl-names = "default", "unwedge";
0175 pinctrl-0 = <&hdmi_ddc>;
0176 pinctrl-1 = <&hdmi_ddc_unwedge>;
0177 status = "okay";
0178 };
0179
0180 &i2c0 {
0181 status = "okay";
0182
0183 clock-frequency = <400000>;
0184 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
0185 i2c-scl-rising-time-ns = <100>; /* 45ns measured */
0186
0187 rk808: pmic@1b {
0188 compatible = "rockchip,rk808";
0189 reg = <0x1b>;
0190 clock-output-names = "xin32k", "wifibt_32kin";
0191 interrupt-parent = <&gpio0>;
0192 interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
0193 pinctrl-names = "default";
0194 pinctrl-0 = <&pmic_int_l>;
0195 rockchip,system-power-controller;
0196 wakeup-source;
0197 #clock-cells = <1>;
0198
0199 vcc1-supply = <&vcc33_sys>;
0200 vcc2-supply = <&vcc33_sys>;
0201 vcc3-supply = <&vcc33_sys>;
0202 vcc4-supply = <&vcc33_sys>;
0203 vcc6-supply = <&vcc_5v>;
0204 vcc7-supply = <&vcc33_sys>;
0205 vcc8-supply = <&vcc33_sys>;
0206 vcc12-supply = <&vcc_18>;
0207 vddio-supply = <&vcc33_io>;
0208
0209 regulators {
0210 vdd_cpu: DCDC_REG1 {
0211 regulator-name = "vdd_arm";
0212 regulator-always-on;
0213 regulator-boot-on;
0214 regulator-min-microvolt = <750000>;
0215 regulator-max-microvolt = <1450000>;
0216 regulator-ramp-delay = <6001>;
0217 regulator-state-mem {
0218 regulator-off-in-suspend;
0219 };
0220 };
0221
0222 vdd_gpu: DCDC_REG2 {
0223 regulator-name = "vdd_gpu";
0224 regulator-always-on;
0225 regulator-boot-on;
0226 regulator-min-microvolt = <800000>;
0227 regulator-max-microvolt = <1250000>;
0228 regulator-ramp-delay = <6001>;
0229 regulator-state-mem {
0230 regulator-off-in-suspend;
0231 };
0232 };
0233
0234 vcc135_ddr: DCDC_REG3 {
0235 regulator-name = "vcc135_ddr";
0236 regulator-always-on;
0237 regulator-boot-on;
0238 regulator-state-mem {
0239 regulator-on-in-suspend;
0240 };
0241 };
0242
0243 /*
0244 * vcc_18 has several aliases. (vcc18_flashio and
0245 * vcc18_wl). We'll add those aliases here just to
0246 * make it easier to follow the schematic. The signals
0247 * are actually hooked together and only separated for
0248 * power measurement purposes).
0249 */
0250 vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
0251 regulator-name = "vcc_18";
0252 regulator-always-on;
0253 regulator-boot-on;
0254 regulator-min-microvolt = <1800000>;
0255 regulator-max-microvolt = <1800000>;
0256 regulator-state-mem {
0257 regulator-on-in-suspend;
0258 regulator-suspend-microvolt = <1800000>;
0259 };
0260 };
0261
0262 /*
0263 * Note that both vcc33_io and vcc33_pmuio are always
0264 * powered together. To simplify the logic in the dts
0265 * we just refer to vcc33_io every time something is
0266 * powered from vcc33_pmuio. In fact, on later boards
0267 * (such as danger) they're the same net.
0268 */
0269 vcc33_io: LDO_REG1 {
0270 regulator-name = "vcc33_io";
0271 regulator-always-on;
0272 regulator-boot-on;
0273 regulator-min-microvolt = <3300000>;
0274 regulator-max-microvolt = <3300000>;
0275 regulator-state-mem {
0276 regulator-on-in-suspend;
0277 regulator-suspend-microvolt = <3300000>;
0278 };
0279 };
0280
0281 vdd_10: LDO_REG3 {
0282 regulator-name = "vdd_10";
0283 regulator-always-on;
0284 regulator-boot-on;
0285 regulator-min-microvolt = <1000000>;
0286 regulator-max-microvolt = <1000000>;
0287 regulator-state-mem {
0288 regulator-on-in-suspend;
0289 regulator-suspend-microvolt = <1000000>;
0290 };
0291 };
0292
0293 vdd10_lcd_pwren_h: LDO_REG7 {
0294 regulator-name = "vdd10_lcd_pwren_h";
0295 regulator-always-on;
0296 regulator-boot-on;
0297 regulator-min-microvolt = <2500000>;
0298 regulator-max-microvolt = <2500000>;
0299 regulator-state-mem {
0300 regulator-off-in-suspend;
0301 };
0302 };
0303
0304 vcc33_lcd: SWITCH_REG1 {
0305 regulator-name = "vcc33_lcd";
0306 regulator-always-on;
0307 regulator-boot-on;
0308 regulator-state-mem {
0309 regulator-off-in-suspend;
0310 };
0311 };
0312 };
0313 };
0314 };
0315
0316 &i2c1 {
0317 status = "okay";
0318
0319 clock-frequency = <400000>;
0320 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
0321 i2c-scl-rising-time-ns = <100>; /* 40ns measured */
0322
0323 tpm: tpm@20 {
0324 compatible = "infineon,slb9645tt";
0325 reg = <0x20>;
0326 powered-while-suspended;
0327 };
0328 };
0329
0330 &i2c2 {
0331 status = "okay";
0332
0333 /* 100kHz since 4.7k resistors don't rise fast enough */
0334 clock-frequency = <100000>;
0335 i2c-scl-falling-time-ns = <50>; /* 10ns measured */
0336 i2c-scl-rising-time-ns = <800>; /* 600ns measured */
0337 };
0338
0339 &i2c4 {
0340 status = "okay";
0341
0342 clock-frequency = <400000>;
0343 i2c-scl-falling-time-ns = <50>; /* 11ns measured */
0344 i2c-scl-rising-time-ns = <300>; /* 225ns measured */
0345 };
0346
0347 &io_domains {
0348 status = "okay";
0349
0350 bb-supply = <&vcc33_io>;
0351 dvp-supply = <&vcc_18>;
0352 flash0-supply = <&vcc18_flashio>;
0353 gpio1830-supply = <&vcc33_io>;
0354 gpio30-supply = <&vcc33_io>;
0355 lcdc-supply = <&vcc33_lcd>;
0356 wifi-supply = <&vcc18_wl>;
0357 };
0358
0359 &pwm1 {
0360 status = "okay";
0361 };
0362
0363 &sdio0 {
0364 status = "okay";
0365
0366 bus-width = <4>;
0367 cap-sd-highspeed;
0368 cap-sdio-irq;
0369 keep-power-in-suspend;
0370 mmc-pwrseq = <&sdio_pwrseq>;
0371 non-removable;
0372 pinctrl-names = "default";
0373 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
0374 sd-uhs-sdr12;
0375 sd-uhs-sdr25;
0376 sd-uhs-sdr50;
0377 sd-uhs-sdr104;
0378 vmmc-supply = <&vcc33_sys>;
0379 vqmmc-supply = <&vcc18_wl>;
0380 };
0381
0382 &spi2 {
0383 status = "okay";
0384
0385 rx-sample-delay-ns = <12>;
0386
0387 flash@0 {
0388 compatible = "jedec,spi-nor";
0389 spi-max-frequency = <50000000>;
0390 reg = <0>;
0391 };
0392 };
0393
0394 &tsadc {
0395 status = "okay";
0396
0397 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
0398 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
0399 rockchip,hw-tshut-temp = <125000>;
0400 };
0401
0402 &uart0 {
0403 status = "okay";
0404
0405 /* Pins don't include flow control by default; add that in */
0406 pinctrl-names = "default";
0407 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
0408 };
0409
0410 &uart1 {
0411 status = "okay";
0412 };
0413
0414 &uart2 {
0415 status = "okay";
0416 };
0417
0418 &usbphy {
0419 status = "okay";
0420 };
0421
0422 &usb_host0_ehci {
0423 status = "okay";
0424
0425 needs-reset-on-resume;
0426 };
0427
0428 &usb_host1 {
0429 status = "okay";
0430 snps,need-phy-for-wake;
0431 };
0432
0433 &usb_otg {
0434 status = "okay";
0435
0436 assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
0437 assigned-clock-parents = <&usbphy0>;
0438 dr_mode = "host";
0439 snps,need-phy-for-wake;
0440 };
0441
0442 &vopb {
0443 status = "okay";
0444 };
0445
0446 &vopb_mmu {
0447 status = "okay";
0448 };
0449
0450 &wdt {
0451 status = "okay";
0452 };
0453
0454 &pinctrl {
0455 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
0456 bias-disable;
0457 drive-strength = <8>;
0458 };
0459
0460 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
0461 bias-pull-up;
0462 drive-strength = <8>;
0463 };
0464
0465 pcfg_output_high: pcfg-output-high {
0466 output-high;
0467 };
0468
0469 pcfg_output_low: pcfg-output-low {
0470 output-low;
0471 };
0472
0473 buttons {
0474 pwr_key_l: pwr-key-l {
0475 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
0476 };
0477 };
0478
0479 emmc {
0480 emmc_reset: emmc-reset {
0481 rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
0482 };
0483
0484 /*
0485 * We run eMMC at max speed; bump up drive strength.
0486 * We also have external pulls, so disable the internal ones.
0487 */
0488 emmc_clk: emmc-clk {
0489 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none_drv_8ma>;
0490 };
0491
0492 emmc_cmd: emmc-cmd {
0493 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none_drv_8ma>;
0494 };
0495
0496 emmc_bus8: emmc-bus8 {
0497 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_none_drv_8ma>,
0498 <3 RK_PA1 2 &pcfg_pull_none_drv_8ma>,
0499 <3 RK_PA2 2 &pcfg_pull_none_drv_8ma>,
0500 <3 RK_PA3 2 &pcfg_pull_none_drv_8ma>,
0501 <3 RK_PA4 2 &pcfg_pull_none_drv_8ma>,
0502 <3 RK_PA5 2 &pcfg_pull_none_drv_8ma>,
0503 <3 RK_PA6 2 &pcfg_pull_none_drv_8ma>,
0504 <3 RK_PA7 2 &pcfg_pull_none_drv_8ma>;
0505 };
0506 };
0507
0508 pmic {
0509 pmic_int_l: pmic-int-l {
0510 rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
0511 };
0512 };
0513
0514 reboot {
0515 ap_warm_reset_h: ap-warm-reset-h {
0516 rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
0517 };
0518 };
0519
0520 recovery-switch {
0521 rec_mode_l: rec-mode-l {
0522 rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
0523 };
0524 };
0525
0526 sdio0 {
0527 wifi_enable_h: wifienable-h {
0528 rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
0529 };
0530
0531 /* NOTE: mislabelled on schematic; should be bt_enable_h */
0532 bt_enable_l: bt-enable-l {
0533 rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
0534 };
0535
0536 bt_host_wake: bt-host-wake {
0537 rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>;
0538 };
0539
0540 bt_host_wake_l: bt-host-wake-l {
0541 rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
0542 };
0543
0544 /*
0545 * We run sdio0 at max speed; bump up drive strength.
0546 * We also have external pulls, so disable the internal ones.
0547 */
0548 sdio0_bus4: sdio0-bus4 {
0549 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_none_drv_8ma>,
0550 <4 RK_PC5 1 &pcfg_pull_none_drv_8ma>,
0551 <4 RK_PC6 1 &pcfg_pull_none_drv_8ma>,
0552 <4 RK_PC7 1 &pcfg_pull_none_drv_8ma>;
0553 };
0554
0555 sdio0_cmd: sdio0-cmd {
0556 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_none_drv_8ma>;
0557 };
0558
0559 sdio0_clk: sdio0-clk {
0560 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>;
0561 };
0562
0563 /*
0564 * These pins are only present on very new veyron boards; on
0565 * older boards bt_dev_wake is simply always high. Note that
0566 * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt
0567 * to map this pin everywhere
0568 */
0569 bt_dev_wake_sleep: bt-dev-wake-sleep {
0570 rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>;
0571 };
0572
0573 bt_dev_wake_awake: bt-dev-wake-awake {
0574 rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
0575 };
0576
0577 bt_dev_wake: bt-dev-wake {
0578 rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
0579 };
0580 };
0581
0582 tpm {
0583 tpm_int_h: tpm-int-h {
0584 rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
0585 };
0586 };
0587
0588 write-protect {
0589 fw_wp_ap: fw-wp-ap {
0590 rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
0591 };
0592 };
0593 };
