0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Google Veyron (and derivatives) fragment for sdmmc cards
0004 *
0005 * Copyright 2015 Google, Inc
0006 */
0007
0008 &io_domains {
0009 sdcard-supply = <&vccio_sd>;
0010 };
0011
0012 &pinctrl {
0013 sdmmc {
0014 /*
0015 * We run sdmmc at max speed; bump up drive strength.
0016 * We also have external pulls, so disable the internal ones.
0017 */
0018 sdmmc_bus4: sdmmc-bus4 {
0019 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_none_drv_8ma>,
0020 <6 RK_PC1 1 &pcfg_pull_none_drv_8ma>,
0021 <6 RK_PC2 1 &pcfg_pull_none_drv_8ma>,
0022 <6 RK_PC3 1 &pcfg_pull_none_drv_8ma>;
0023 };
0024
0025 sdmmc_clk: sdmmc-clk {
0026 rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
0027 };
0028
0029 sdmmc_cmd: sdmmc-cmd {
0030 rockchip,pins = <6 RK_PC5 1 &pcfg_pull_none_drv_8ma>;
0031 };
0032
0033 /*
0034 * Builtin CD line is hooked to ground to prevent JTAG at boot
0035 * (and also to get the voltage rail correct).
0036 * Configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
0037 * think there's a card inserted
0038 */
0039 sdmmc_cd_disabled: sdmmc-cd-disabled {
0040 rockchip,pins = <6 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
0041 };
0042
0043 /* This is where we actually hook up CD */
0044 sdmmc_cd_pin: sdmmc-cd-pin {
0045 rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
0046 };
0047 };
0048 };
0049
0050 &rk808 {
0051 vcc9-supply = <&vcc_5v>;
0052
0053 regulators {
0054 vccio_sd: LDO_REG4 {
0055 regulator-name = "vccio_sd";
0056 regulator-min-microvolt = <1800000>;
0057 regulator-max-microvolt = <3300000>;
0058 regulator-state-mem {
0059 regulator-off-in-suspend;
0060 };
0061 };
0062
0063 vcc33_sd: LDO_REG5 {
0064 regulator-name = "vcc33_sd";
0065 regulator-min-microvolt = <3300000>;
0066 regulator-max-microvolt = <3300000>;
0067 regulator-state-mem {
0068 regulator-off-in-suspend;
0069 };
0070 };
0071 };
0072 };
0073
0074 &sdmmc {
0075 status = "okay";
0076
0077 bus-width = <4>;
0078 cap-mmc-highspeed;
0079 cap-sd-highspeed;
0080 card-detect-delay = <200>;
0081 cd-gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>;
0082 rockchip,default-sample-phase = <90>;
0083 sd-uhs-sdr12;
0084 sd-uhs-sdr25;
0085 sd-uhs-sdr50;
0086 sd-uhs-sdr104;
0087 vmmc-supply = <&vcc33_sd>;
0088 vqmmc-supply = <&vccio_sd>;
0089 };
