0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002
0003 #include <dt-bindings/gpio/gpio.h>
0004 #include <dt-bindings/interrupt-controller/irq.h>
0005 #include <dt-bindings/interrupt-controller/arm-gic.h>
0006 #include <dt-bindings/pinctrl/rockchip.h>
0007 #include <dt-bindings/clock/rk3228-cru.h>
0008 #include <dt-bindings/thermal/thermal.h>
0009 #include <dt-bindings/power/rk3228-power.h>
0010
0011 / {
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014
0015 interrupt-parent = <&gic>;
0016
0017 aliases {
0018 serial0 = &uart0;
0019 serial1 = &uart1;
0020 serial2 = &uart2;
0021 spi0 = &spi0;
0022 };
0023
0024 cpus {
0025 #address-cells = <1>;
0026 #size-cells = <0>;
0027
0028 cpu0: cpu@f00 {
0029 device_type = "cpu";
0030 compatible = "arm,cortex-a7";
0031 reg = <0xf00>;
0032 resets = <&cru SRST_CORE0>;
0033 operating-points-v2 = <&cpu0_opp_table>;
0034 #cooling-cells = <2>; /* min followed by max */
0035 clock-latency = <40000>;
0036 clocks = <&cru ARMCLK>;
0037 enable-method = "psci";
0038 };
0039
0040 cpu1: cpu@f01 {
0041 device_type = "cpu";
0042 compatible = "arm,cortex-a7";
0043 reg = <0xf01>;
0044 resets = <&cru SRST_CORE1>;
0045 operating-points-v2 = <&cpu0_opp_table>;
0046 #cooling-cells = <2>; /* min followed by max */
0047 enable-method = "psci";
0048 };
0049
0050 cpu2: cpu@f02 {
0051 device_type = "cpu";
0052 compatible = "arm,cortex-a7";
0053 reg = <0xf02>;
0054 resets = <&cru SRST_CORE2>;
0055 operating-points-v2 = <&cpu0_opp_table>;
0056 #cooling-cells = <2>; /* min followed by max */
0057 enable-method = "psci";
0058 };
0059
0060 cpu3: cpu@f03 {
0061 device_type = "cpu";
0062 compatible = "arm,cortex-a7";
0063 reg = <0xf03>;
0064 resets = <&cru SRST_CORE3>;
0065 operating-points-v2 = <&cpu0_opp_table>;
0066 #cooling-cells = <2>; /* min followed by max */
0067 enable-method = "psci";
0068 };
0069 };
0070
0071 cpu0_opp_table: opp-table-0 {
0072 compatible = "operating-points-v2";
0073 opp-shared;
0074
0075 opp-408000000 {
0076 opp-hz = /bits/ 64 <408000000>;
0077 opp-microvolt = <950000>;
0078 clock-latency-ns = <40000>;
0079 opp-suspend;
0080 };
0081 opp-600000000 {
0082 opp-hz = /bits/ 64 <600000000>;
0083 opp-microvolt = <975000>;
0084 };
0085 opp-816000000 {
0086 opp-hz = /bits/ 64 <816000000>;
0087 opp-microvolt = <1000000>;
0088 };
0089 opp-1008000000 {
0090 opp-hz = /bits/ 64 <1008000000>;
0091 opp-microvolt = <1175000>;
0092 };
0093 opp-1200000000 {
0094 opp-hz = /bits/ 64 <1200000000>;
0095 opp-microvolt = <1275000>;
0096 };
0097 };
0098
0099 arm-pmu {
0100 compatible = "arm,cortex-a7-pmu";
0101 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
0102 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
0103 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
0104 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0105 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0106 };
0107
0108 psci {
0109 compatible = "arm,psci-1.0", "arm,psci-0.2";
0110 method = "smc";
0111 };
0112
0113 timer {
0114 compatible = "arm,armv7-timer";
0115 arm,cpu-registers-not-fw-configured;
0116 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0117 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0118 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
0119 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0120 clock-frequency = <24000000>;
0121 };
0122
0123 xin24m: oscillator {
0124 compatible = "fixed-clock";
0125 clock-frequency = <24000000>;
0126 clock-output-names = "xin24m";
0127 #clock-cells = <0>;
0128 };
0129
0130 display_subsystem: display-subsystem {
0131 compatible = "rockchip,display-subsystem";
0132 ports = <&vop_out>;
0133 };
0134
0135 i2s1: i2s1@100b0000 {
0136 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
0137 reg = <0x100b0000 0x4000>;
0138 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0139 clock-names = "i2s_clk", "i2s_hclk";
0140 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
0141 dmas = <&pdma 14>, <&pdma 15>;
0142 dma-names = "tx", "rx";
0143 pinctrl-names = "default";
0144 pinctrl-0 = <&i2s1_bus>;
0145 status = "disabled";
0146 };
0147
0148 i2s0: i2s0@100c0000 {
0149 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
0150 reg = <0x100c0000 0x4000>;
0151 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0152 clock-names = "i2s_clk", "i2s_hclk";
0153 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
0154 dmas = <&pdma 11>, <&pdma 12>;
0155 dma-names = "tx", "rx";
0156 status = "disabled";
0157 };
0158
0159 spdif: spdif@100d0000 {
0160 compatible = "rockchip,rk3228-spdif";
0161 reg = <0x100d0000 0x1000>;
0162 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0163 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
0164 clock-names = "mclk", "hclk";
0165 dmas = <&pdma 10>;
0166 dma-names = "tx";
0167 pinctrl-names = "default";
0168 pinctrl-0 = <&spdif_tx>;
0169 status = "disabled";
0170 };
0171
0172 i2s2: i2s2@100e0000 {
0173 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
0174 reg = <0x100e0000 0x4000>;
0175 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0176 clock-names = "i2s_clk", "i2s_hclk";
0177 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
0178 dmas = <&pdma 0>, <&pdma 1>;
0179 dma-names = "tx", "rx";
0180 status = "disabled";
0181 };
0182
0183 grf: syscon@11000000 {
0184 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
0185 reg = <0x11000000 0x1000>;
0186 #address-cells = <1>;
0187 #size-cells = <1>;
0188
0189 io_domains: io-domains {
0190 compatible = "rockchip,rk3228-io-voltage-domain";
0191 status = "disabled";
0192 };
0193
0194 power: power-controller {
0195 compatible = "rockchip,rk3228-power-controller";
0196 #power-domain-cells = <1>;
0197 #address-cells = <1>;
0198 #size-cells = <0>;
0199
0200 power-domain@RK3228_PD_VIO {
0201 reg = <RK3228_PD_VIO>;
0202 clocks = <&cru ACLK_HDCP>,
0203 <&cru SCLK_HDCP>,
0204 <&cru ACLK_IEP>,
0205 <&cru HCLK_IEP>,
0206 <&cru ACLK_RGA>,
0207 <&cru HCLK_RGA>,
0208 <&cru SCLK_RGA>;
0209 pm_qos = <&qos_hdcp>,
0210 <&qos_iep>,
0211 <&qos_rga_r>,
0212 <&qos_rga_w>;
0213 #power-domain-cells = <0>;
0214 };
0215
0216 power-domain@RK3228_PD_VOP {
0217 reg = <RK3228_PD_VOP>;
0218 clocks =<&cru ACLK_VOP>,
0219 <&cru DCLK_VOP>,
0220 <&cru HCLK_VOP>;
0221 pm_qos = <&qos_vop>;
0222 #power-domain-cells = <0>;
0223 };
0224
0225 power-domain@RK3228_PD_VPU {
0226 reg = <RK3228_PD_VPU>;
0227 clocks = <&cru ACLK_VPU>,
0228 <&cru HCLK_VPU>;
0229 pm_qos = <&qos_vpu>;
0230 #power-domain-cells = <0>;
0231 };
0232
0233 power-domain@RK3228_PD_RKVDEC {
0234 reg = <RK3228_PD_RKVDEC>;
0235 clocks = <&cru ACLK_RKVDEC>,
0236 <&cru HCLK_RKVDEC>,
0237 <&cru SCLK_VDEC_CABAC>,
0238 <&cru SCLK_VDEC_CORE>;
0239 pm_qos = <&qos_rkvdec_r>,
0240 <&qos_rkvdec_w>;
0241 #power-domain-cells = <0>;
0242 };
0243
0244 power-domain@RK3228_PD_GPU {
0245 reg = <RK3228_PD_GPU>;
0246 clocks = <&cru ACLK_GPU>;
0247 pm_qos = <&qos_gpu>;
0248 #power-domain-cells = <0>;
0249 };
0250 };
0251
0252 u2phy0: usb2phy@760 {
0253 compatible = "rockchip,rk3228-usb2phy";
0254 reg = <0x0760 0x0c>;
0255 clocks = <&cru SCLK_OTGPHY0>;
0256 clock-names = "phyclk";
0257 clock-output-names = "usb480m_phy0";
0258 #clock-cells = <0>;
0259 status = "disabled";
0260
0261 u2phy0_otg: otg-port {
0262 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
0263 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
0264 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0265 interrupt-names = "otg-bvalid", "otg-id",
0266 "linestate";
0267 #phy-cells = <0>;
0268 status = "disabled";
0269 };
0270
0271 u2phy0_host: host-port {
0272 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0273 interrupt-names = "linestate";
0274 #phy-cells = <0>;
0275 status = "disabled";
0276 };
0277 };
0278
0279 u2phy1: usb2phy@800 {
0280 compatible = "rockchip,rk3228-usb2phy";
0281 reg = <0x0800 0x0c>;
0282 clocks = <&cru SCLK_OTGPHY1>;
0283 clock-names = "phyclk";
0284 clock-output-names = "usb480m_phy1";
0285 #clock-cells = <0>;
0286 status = "disabled";
0287
0288 u2phy1_otg: otg-port {
0289 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
0290 interrupt-names = "linestate";
0291 #phy-cells = <0>;
0292 status = "disabled";
0293 };
0294
0295 u2phy1_host: host-port {
0296 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0297 interrupt-names = "linestate";
0298 #phy-cells = <0>;
0299 status = "disabled";
0300 };
0301 };
0302 };
0303
0304 uart0: serial@11010000 {
0305 compatible = "snps,dw-apb-uart";
0306 reg = <0x11010000 0x100>;
0307 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0308 clock-frequency = <24000000>;
0309 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
0310 clock-names = "baudclk", "apb_pclk";
0311 pinctrl-names = "default";
0312 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
0313 reg-shift = <2>;
0314 reg-io-width = <4>;
0315 status = "disabled";
0316 };
0317
0318 uart1: serial@11020000 {
0319 compatible = "snps,dw-apb-uart";
0320 reg = <0x11020000 0x100>;
0321 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0322 clock-frequency = <24000000>;
0323 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
0324 clock-names = "baudclk", "apb_pclk";
0325 pinctrl-names = "default";
0326 pinctrl-0 = <&uart1_xfer>;
0327 reg-shift = <2>;
0328 reg-io-width = <4>;
0329 status = "disabled";
0330 };
0331
0332 uart2: serial@11030000 {
0333 compatible = "snps,dw-apb-uart";
0334 reg = <0x11030000 0x100>;
0335 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0336 clock-frequency = <24000000>;
0337 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
0338 clock-names = "baudclk", "apb_pclk";
0339 pinctrl-names = "default";
0340 pinctrl-0 = <&uart2_xfer>;
0341 reg-shift = <2>;
0342 reg-io-width = <4>;
0343 status = "disabled";
0344 };
0345
0346 efuse: efuse@11040000 {
0347 compatible = "rockchip,rk3228-efuse";
0348 reg = <0x11040000 0x20>;
0349 clocks = <&cru PCLK_EFUSE_256>;
0350 clock-names = "pclk_efuse";
0351 #address-cells = <1>;
0352 #size-cells = <1>;
0353
0354 /* Data cells */
0355 efuse_id: id@7 {
0356 reg = <0x7 0x10>;
0357 };
0358 cpu_leakage: cpu_leakage@17 {
0359 reg = <0x17 0x1>;
0360 };
0361 };
0362
0363 i2c0: i2c@11050000 {
0364 compatible = "rockchip,rk3228-i2c";
0365 reg = <0x11050000 0x1000>;
0366 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0367 #address-cells = <1>;
0368 #size-cells = <0>;
0369 clock-names = "i2c";
0370 clocks = <&cru PCLK_I2C0>;
0371 pinctrl-names = "default";
0372 pinctrl-0 = <&i2c0_xfer>;
0373 status = "disabled";
0374 };
0375
0376 i2c1: i2c@11060000 {
0377 compatible = "rockchip,rk3228-i2c";
0378 reg = <0x11060000 0x1000>;
0379 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0380 #address-cells = <1>;
0381 #size-cells = <0>;
0382 clock-names = "i2c";
0383 clocks = <&cru PCLK_I2C1>;
0384 pinctrl-names = "default";
0385 pinctrl-0 = <&i2c1_xfer>;
0386 status = "disabled";
0387 };
0388
0389 i2c2: i2c@11070000 {
0390 compatible = "rockchip,rk3228-i2c";
0391 reg = <0x11070000 0x1000>;
0392 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0393 #address-cells = <1>;
0394 #size-cells = <0>;
0395 clock-names = "i2c";
0396 clocks = <&cru PCLK_I2C2>;
0397 pinctrl-names = "default";
0398 pinctrl-0 = <&i2c2_xfer>;
0399 status = "disabled";
0400 };
0401
0402 i2c3: i2c@11080000 {
0403 compatible = "rockchip,rk3228-i2c";
0404 reg = <0x11080000 0x1000>;
0405 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0406 #address-cells = <1>;
0407 #size-cells = <0>;
0408 clock-names = "i2c";
0409 clocks = <&cru PCLK_I2C3>;
0410 pinctrl-names = "default";
0411 pinctrl-0 = <&i2c3_xfer>;
0412 status = "disabled";
0413 };
0414
0415 spi0: spi@11090000 {
0416 compatible = "rockchip,rk3228-spi";
0417 reg = <0x11090000 0x1000>;
0418 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0419 #address-cells = <1>;
0420 #size-cells = <0>;
0421 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
0422 clock-names = "spiclk", "apb_pclk";
0423 pinctrl-names = "default";
0424 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
0425 status = "disabled";
0426 };
0427
0428 wdt: watchdog@110a0000 {
0429 compatible = "rockchip,rk3228-wdt", "snps,dw-wdt";
0430 reg = <0x110a0000 0x100>;
0431 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
0432 clocks = <&cru PCLK_CPU>;
0433 status = "disabled";
0434 };
0435
0436 pwm0: pwm@110b0000 {
0437 compatible = "rockchip,rk3288-pwm";
0438 reg = <0x110b0000 0x10>;
0439 #pwm-cells = <3>;
0440 clocks = <&cru PCLK_PWM>;
0441 pinctrl-names = "default";
0442 pinctrl-0 = <&pwm0_pin>;
0443 status = "disabled";
0444 };
0445
0446 pwm1: pwm@110b0010 {
0447 compatible = "rockchip,rk3288-pwm";
0448 reg = <0x110b0010 0x10>;
0449 #pwm-cells = <3>;
0450 clocks = <&cru PCLK_PWM>;
0451 pinctrl-names = "default";
0452 pinctrl-0 = <&pwm1_pin>;
0453 status = "disabled";
0454 };
0455
0456 pwm2: pwm@110b0020 {
0457 compatible = "rockchip,rk3288-pwm";
0458 reg = <0x110b0020 0x10>;
0459 #pwm-cells = <3>;
0460 clocks = <&cru PCLK_PWM>;
0461 pinctrl-names = "default";
0462 pinctrl-0 = <&pwm2_pin>;
0463 status = "disabled";
0464 };
0465
0466 pwm3: pwm@110b0030 {
0467 compatible = "rockchip,rk3288-pwm";
0468 reg = <0x110b0030 0x10>;
0469 #pwm-cells = <2>;
0470 clocks = <&cru PCLK_PWM>;
0471 pinctrl-names = "default";
0472 pinctrl-0 = <&pwm3_pin>;
0473 status = "disabled";
0474 };
0475
0476 timer: timer@110c0000 {
0477 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
0478 reg = <0x110c0000 0x20>;
0479 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
0480 clocks = <&cru PCLK_TIMER>, <&xin24m>;
0481 clock-names = "pclk", "timer";
0482 };
0483
0484 cru: clock-controller@110e0000 {
0485 compatible = "rockchip,rk3228-cru";
0486 reg = <0x110e0000 0x1000>;
0487 clocks = <&xin24m>;
0488 clock-names = "xin24m";
0489 rockchip,grf = <&grf>;
0490 #clock-cells = <1>;
0491 #reset-cells = <1>;
0492 assigned-clocks =
0493 <&cru PLL_GPLL>, <&cru ARMCLK>,
0494 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
0495 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
0496 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
0497 <&cru PCLK_CPU>;
0498 assigned-clock-rates =
0499 <594000000>, <816000000>,
0500 <500000000>, <150000000>,
0501 <150000000>, <75000000>,
0502 <150000000>, <150000000>,
0503 <75000000>;
0504 };
0505
0506 pdma: dma-controller@110f0000 {
0507 compatible = "arm,pl330", "arm,primecell";
0508 reg = <0x110f0000 0x4000>;
0509 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0510 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0511 #dma-cells = <1>;
0512 arm,pl330-periph-burst;
0513 clocks = <&cru ACLK_DMAC>;
0514 clock-names = "apb_pclk";
0515 };
0516
0517 thermal-zones {
0518 cpu_thermal: cpu-thermal {
0519 polling-delay-passive = <100>; /* milliseconds */
0520 polling-delay = <5000>; /* milliseconds */
0521
0522 thermal-sensors = <&tsadc 0>;
0523
0524 trips {
0525 cpu_alert0: cpu_alert0 {
0526 temperature = <70000>; /* millicelsius */
0527 hysteresis = <2000>; /* millicelsius */
0528 type = "passive";
0529 };
0530 cpu_alert1: cpu_alert1 {
0531 temperature = <75000>; /* millicelsius */
0532 hysteresis = <2000>; /* millicelsius */
0533 type = "passive";
0534 };
0535 cpu_crit: cpu_crit {
0536 temperature = <90000>; /* millicelsius */
0537 hysteresis = <2000>; /* millicelsius */
0538 type = "critical";
0539 };
0540 };
0541
0542 cooling-maps {
0543 map0 {
0544 trip = <&cpu_alert0>;
0545 cooling-device =
0546 <&cpu0 THERMAL_NO_LIMIT 6>,
0547 <&cpu1 THERMAL_NO_LIMIT 6>,
0548 <&cpu2 THERMAL_NO_LIMIT 6>,
0549 <&cpu3 THERMAL_NO_LIMIT 6>;
0550 };
0551 map1 {
0552 trip = <&cpu_alert1>;
0553 cooling-device =
0554 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0555 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0556 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0557 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0558 };
0559 };
0560 };
0561 };
0562
0563 tsadc: tsadc@11150000 {
0564 compatible = "rockchip,rk3228-tsadc";
0565 reg = <0x11150000 0x100>;
0566 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0567 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
0568 clock-names = "tsadc", "apb_pclk";
0569 assigned-clocks = <&cru SCLK_TSADC>;
0570 assigned-clock-rates = <32768>;
0571 resets = <&cru SRST_TSADC>;
0572 reset-names = "tsadc-apb";
0573 pinctrl-names = "init", "default", "sleep";
0574 pinctrl-0 = <&otp_pin>;
0575 pinctrl-1 = <&otp_out>;
0576 pinctrl-2 = <&otp_pin>;
0577 #thermal-sensor-cells = <1>;
0578 rockchip,hw-tshut-temp = <95000>;
0579 status = "disabled";
0580 };
0581
0582 hdmi_phy: hdmi-phy@12030000 {
0583 compatible = "rockchip,rk3228-hdmi-phy";
0584 reg = <0x12030000 0x10000>;
0585 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
0586 clock-names = "sysclk", "refoclk", "refpclk";
0587 #clock-cells = <0>;
0588 clock-output-names = "hdmiphy_phy";
0589 #phy-cells = <0>;
0590 status = "disabled";
0591 };
0592
0593 gpu: gpu@20000000 {
0594 compatible = "rockchip,rk3228-mali", "arm,mali-400";
0595 reg = <0x20000000 0x10000>;
0596 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0597 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0598 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0599 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0600 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0601 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0602 interrupt-names = "gp",
0603 "gpmmu",
0604 "pp0",
0605 "ppmmu0",
0606 "pp1",
0607 "ppmmu1";
0608 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
0609 clock-names = "bus", "core";
0610 power-domains = <&power RK3228_PD_GPU>;
0611 resets = <&cru SRST_GPU_A>;
0612 status = "disabled";
0613 };
0614
0615 vpu: video-codec@20020000 {
0616 compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu";
0617 reg = <0x20020000 0x800>;
0618 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0619 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0620 interrupt-names = "vepu", "vdpu";
0621 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
0622 clock-names = "aclk", "hclk";
0623 iommus = <&vpu_mmu>;
0624 power-domains = <&power RK3228_PD_VPU>;
0625 };
0626
0627 vpu_mmu: iommu@20020800 {
0628 compatible = "rockchip,iommu";
0629 reg = <0x20020800 0x100>;
0630 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0631 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
0632 clock-names = "aclk", "iface";
0633 power-domains = <&power RK3228_PD_VPU>;
0634 #iommu-cells = <0>;
0635 };
0636
0637 vdec: video-codec@20030000 {
0638 compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec";
0639 reg = <0x20030000 0x480>;
0640 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0641 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
0642 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
0643 clock-names = "axi", "ahb", "cabac", "core";
0644 assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
0645 assigned-clock-rates = <300000000>, <300000000>;
0646 iommus = <&vdec_mmu>;
0647 power-domains = <&power RK3228_PD_RKVDEC>;
0648 };
0649
0650 vdec_mmu: iommu@20030480 {
0651 compatible = "rockchip,iommu";
0652 reg = <0x20030480 0x40>, <0x200304c0 0x40>;
0653 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0654 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
0655 clock-names = "aclk", "iface";
0656 power-domains = <&power RK3228_PD_RKVDEC>;
0657 #iommu-cells = <0>;
0658 };
0659
0660 vop: vop@20050000 {
0661 compatible = "rockchip,rk3228-vop";
0662 reg = <0x20050000 0x1ffc>;
0663 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0664 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
0665 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
0666 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
0667 reset-names = "axi", "ahb", "dclk";
0668 iommus = <&vop_mmu>;
0669 power-domains = <&power RK3228_PD_VOP>;
0670 status = "disabled";
0671
0672 vop_out: port {
0673 #address-cells = <1>;
0674 #size-cells = <0>;
0675
0676 vop_out_hdmi: endpoint@0 {
0677 reg = <0>;
0678 remote-endpoint = <&hdmi_in_vop>;
0679 };
0680 };
0681 };
0682
0683 vop_mmu: iommu@20053f00 {
0684 compatible = "rockchip,iommu";
0685 reg = <0x20053f00 0x100>;
0686 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0687 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
0688 clock-names = "aclk", "iface";
0689 power-domains = <&power RK3228_PD_VOP>;
0690 #iommu-cells = <0>;
0691 status = "disabled";
0692 };
0693
0694 rga: rga@20060000 {
0695 compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
0696 reg = <0x20060000 0x1000>;
0697 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0698 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
0699 clock-names = "aclk", "hclk", "sclk";
0700 power-domains = <&power RK3228_PD_VIO>;
0701 resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
0702 reset-names = "core", "axi", "ahb";
0703 };
0704
0705 iep_mmu: iommu@20070800 {
0706 compatible = "rockchip,iommu";
0707 reg = <0x20070800 0x100>;
0708 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0709 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
0710 clock-names = "aclk", "iface";
0711 power-domains = <&power RK3228_PD_VIO>;
0712 #iommu-cells = <0>;
0713 status = "disabled";
0714 };
0715
0716 hdmi: hdmi@200a0000 {
0717 compatible = "rockchip,rk3228-dw-hdmi";
0718 reg = <0x200a0000 0x20000>;
0719 reg-io-width = <4>;
0720 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0721 assigned-clocks = <&cru SCLK_HDMI_PHY>;
0722 assigned-clock-parents = <&hdmi_phy>;
0723 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
0724 clock-names = "iahb", "isfr", "cec";
0725 pinctrl-names = "default";
0726 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
0727 resets = <&cru SRST_HDMI_P>;
0728 reset-names = "hdmi";
0729 phys = <&hdmi_phy>;
0730 phy-names = "hdmi";
0731 rockchip,grf = <&grf>;
0732 status = "disabled";
0733
0734 ports {
0735 hdmi_in: port {
0736 #address-cells = <1>;
0737 #size-cells = <0>;
0738 hdmi_in_vop: endpoint@0 {
0739 reg = <0>;
0740 remote-endpoint = <&vop_out_hdmi>;
0741 };
0742 };
0743 };
0744 };
0745
0746 sdmmc: mmc@30000000 {
0747 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
0748 reg = <0x30000000 0x4000>;
0749 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0750 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
0751 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
0752 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
0753 fifo-depth = <0x100>;
0754 pinctrl-names = "default";
0755 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
0756 status = "disabled";
0757 };
0758
0759 sdio: mmc@30010000 {
0760 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
0761 reg = <0x30010000 0x4000>;
0762 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0763 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
0764 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
0765 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
0766 fifo-depth = <0x100>;
0767 pinctrl-names = "default";
0768 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
0769 status = "disabled";
0770 };
0771
0772 emmc: mmc@30020000 {
0773 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
0774 reg = <0x30020000 0x4000>;
0775 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0776 clock-frequency = <37500000>;
0777 max-frequency = <37500000>;
0778 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
0779 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
0780 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
0781 bus-width = <8>;
0782 rockchip,default-sample-phase = <158>;
0783 fifo-depth = <0x100>;
0784 pinctrl-names = "default";
0785 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
0786 resets = <&cru SRST_EMMC>;
0787 reset-names = "reset";
0788 status = "disabled";
0789 };
0790
0791 usb_otg: usb@30040000 {
0792 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
0793 "snps,dwc2";
0794 reg = <0x30040000 0x40000>;
0795 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0796 clocks = <&cru HCLK_OTG>;
0797 clock-names = "otg";
0798 dr_mode = "otg";
0799 g-np-tx-fifo-size = <16>;
0800 g-rx-fifo-size = <280>;
0801 g-tx-fifo-size = <256 128 128 64 32 16>;
0802 phys = <&u2phy0_otg>;
0803 phy-names = "usb2-phy";
0804 status = "disabled";
0805 };
0806
0807 usb_host0_ehci: usb@30080000 {
0808 compatible = "generic-ehci";
0809 reg = <0x30080000 0x20000>;
0810 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0811 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
0812 phys = <&u2phy0_host>;
0813 phy-names = "usb";
0814 status = "disabled";
0815 };
0816
0817 usb_host0_ohci: usb@300a0000 {
0818 compatible = "generic-ohci";
0819 reg = <0x300a0000 0x20000>;
0820 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0821 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
0822 phys = <&u2phy0_host>;
0823 phy-names = "usb";
0824 status = "disabled";
0825 };
0826
0827 usb_host1_ehci: usb@300c0000 {
0828 compatible = "generic-ehci";
0829 reg = <0x300c0000 0x20000>;
0830 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0831 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
0832 phys = <&u2phy1_otg>;
0833 phy-names = "usb";
0834 status = "disabled";
0835 };
0836
0837 usb_host1_ohci: usb@300e0000 {
0838 compatible = "generic-ohci";
0839 reg = <0x300e0000 0x20000>;
0840 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0841 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
0842 phys = <&u2phy1_otg>;
0843 phy-names = "usb";
0844 status = "disabled";
0845 };
0846
0847 usb_host2_ehci: usb@30100000 {
0848 compatible = "generic-ehci";
0849 reg = <0x30100000 0x20000>;
0850 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0851 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
0852 phys = <&u2phy1_host>;
0853 phy-names = "usb";
0854 status = "disabled";
0855 };
0856
0857 usb_host2_ohci: usb@30120000 {
0858 compatible = "generic-ohci";
0859 reg = <0x30120000 0x20000>;
0860 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0861 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
0862 phys = <&u2phy1_host>;
0863 phy-names = "usb";
0864 status = "disabled";
0865 };
0866
0867 gmac: ethernet@30200000 {
0868 compatible = "rockchip,rk3228-gmac";
0869 reg = <0x30200000 0x10000>;
0870 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0871 interrupt-names = "macirq";
0872 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
0873 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
0874 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
0875 <&cru PCLK_GMAC>;
0876 clock-names = "stmmaceth", "mac_clk_rx",
0877 "mac_clk_tx", "clk_mac_ref",
0878 "clk_mac_refout", "aclk_mac",
0879 "pclk_mac";
0880 resets = <&cru SRST_GMAC>;
0881 reset-names = "stmmaceth";
0882 rockchip,grf = <&grf>;
0883 status = "disabled";
0884 };
0885
0886 qos_iep: qos@31030080 {
0887 compatible = "rockchip,rk3228-qos", "syscon";
0888 reg = <0x31030080 0x20>;
0889 };
0890
0891 qos_rga_w: qos@31030100 {
0892 compatible = "rockchip,rk3228-qos", "syscon";
0893 reg = <0x31030100 0x20>;
0894 };
0895
0896 qos_hdcp: qos@31030180 {
0897 compatible = "rockchip,rk3228-qos", "syscon";
0898 reg = <0x31030180 0x20>;
0899 };
0900
0901 qos_rga_r: qos@31030200 {
0902 compatible = "rockchip,rk3228-qos", "syscon";
0903 reg = <0x31030200 0x20>;
0904 };
0905
0906 qos_vpu: qos@31040000 {
0907 compatible = "rockchip,rk3228-qos", "syscon";
0908 reg = <0x31040000 0x20>;
0909 };
0910
0911 qos_gpu: qos@31050000 {
0912 compatible = "rockchip,rk3228-qos", "syscon";
0913 reg = <0x31050000 0x20>;
0914 };
0915
0916 qos_vop: qos@31060000 {
0917 compatible = "rockchip,rk3228-qos", "syscon";
0918 reg = <0x31060000 0x20>;
0919 };
0920
0921 qos_rkvdec_r: qos@31070000 {
0922 compatible = "rockchip,rk3228-qos", "syscon";
0923 reg = <0x31070000 0x20>;
0924 };
0925
0926 qos_rkvdec_w: qos@31070080 {
0927 compatible = "rockchip,rk3228-qos", "syscon";
0928 reg = <0x31070080 0x20>;
0929 };
0930
0931 gic: interrupt-controller@32010000 {
0932 compatible = "arm,gic-400";
0933 interrupt-controller;
0934 #interrupt-cells = <3>;
0935 #address-cells = <0>;
0936
0937 reg = <0x32011000 0x1000>,
0938 <0x32012000 0x2000>,
0939 <0x32014000 0x2000>,
0940 <0x32016000 0x2000>;
0941 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0942 };
0943
0944 pinctrl: pinctrl {
0945 compatible = "rockchip,rk3228-pinctrl";
0946 rockchip,grf = <&grf>;
0947 #address-cells = <1>;
0948 #size-cells = <1>;
0949 ranges;
0950
0951 gpio0: gpio@11110000 {
0952 compatible = "rockchip,gpio-bank";
0953 reg = <0x11110000 0x100>;
0954 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0955 clocks = <&cru PCLK_GPIO0>;
0956
0957 gpio-controller;
0958 #gpio-cells = <2>;
0959
0960 interrupt-controller;
0961 #interrupt-cells = <2>;
0962 };
0963
0964 gpio1: gpio@11120000 {
0965 compatible = "rockchip,gpio-bank";
0966 reg = <0x11120000 0x100>;
0967 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
0968 clocks = <&cru PCLK_GPIO1>;
0969
0970 gpio-controller;
0971 #gpio-cells = <2>;
0972
0973 interrupt-controller;
0974 #interrupt-cells = <2>;
0975 };
0976
0977 gpio2: gpio@11130000 {
0978 compatible = "rockchip,gpio-bank";
0979 reg = <0x11130000 0x100>;
0980 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0981 clocks = <&cru PCLK_GPIO2>;
0982
0983 gpio-controller;
0984 #gpio-cells = <2>;
0985
0986 interrupt-controller;
0987 #interrupt-cells = <2>;
0988 };
0989
0990 gpio3: gpio@11140000 {
0991 compatible = "rockchip,gpio-bank";
0992 reg = <0x11140000 0x100>;
0993 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
0994 clocks = <&cru PCLK_GPIO3>;
0995
0996 gpio-controller;
0997 #gpio-cells = <2>;
0998
0999 interrupt-controller;
1000 #interrupt-cells = <2>;
1001 };
1002
1003 pcfg_pull_up: pcfg-pull-up {
1004 bias-pull-up;
1005 };
1006
1007 pcfg_pull_down: pcfg-pull-down {
1008 bias-pull-down;
1009 };
1010
1011 pcfg_pull_none: pcfg-pull-none {
1012 bias-disable;
1013 };
1014
1015 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1016 drive-strength = <12>;
1017 };
1018
1019 sdmmc {
1020 sdmmc_clk: sdmmc-clk {
1021 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
1022 };
1023
1024 sdmmc_cmd: sdmmc-cmd {
1025 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
1026 };
1027
1028 sdmmc_bus4: sdmmc-bus4 {
1029 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
1030 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
1031 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
1032 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
1033 };
1034 };
1035
1036 sdio {
1037 sdio_clk: sdio-clk {
1038 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
1039 };
1040
1041 sdio_cmd: sdio-cmd {
1042 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
1043 };
1044
1045 sdio_bus4: sdio-bus4 {
1046 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
1047 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
1048 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
1049 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
1050 };
1051 };
1052
1053 emmc {
1054 emmc_clk: emmc-clk {
1055 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
1056 };
1057
1058 emmc_cmd: emmc-cmd {
1059 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>;
1060 };
1061
1062 emmc_bus8: emmc-bus8 {
1063 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
1064 <1 RK_PD1 2 &pcfg_pull_none>,
1065 <1 RK_PD2 2 &pcfg_pull_none>,
1066 <1 RK_PD3 2 &pcfg_pull_none>,
1067 <1 RK_PD4 2 &pcfg_pull_none>,
1068 <1 RK_PD5 2 &pcfg_pull_none>,
1069 <1 RK_PD6 2 &pcfg_pull_none>,
1070 <1 RK_PD7 2 &pcfg_pull_none>;
1071 };
1072 };
1073
1074 gmac {
1075 rgmii_pins: rgmii-pins {
1076 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
1077 <2 RK_PB4 1 &pcfg_pull_none>,
1078 <2 RK_PD1 1 &pcfg_pull_none>,
1079 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
1080 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
1081 <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,
1082 <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,
1083 <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,
1084 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
1085 <2 RK_PC1 1 &pcfg_pull_none>,
1086 <2 RK_PC0 1 &pcfg_pull_none>,
1087 <2 RK_PC5 2 &pcfg_pull_none>,
1088 <2 RK_PC4 2 &pcfg_pull_none>,
1089 <2 RK_PB3 1 &pcfg_pull_none>,
1090 <2 RK_PB0 1 &pcfg_pull_none>;
1091 };
1092
1093 rmii_pins: rmii-pins {
1094 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
1095 <2 RK_PB4 1 &pcfg_pull_none>,
1096 <2 RK_PD1 1 &pcfg_pull_none>,
1097 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
1098 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
1099 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
1100 <2 RK_PC1 1 &pcfg_pull_none>,
1101 <2 RK_PC0 1 &pcfg_pull_none>,
1102 <2 RK_PB0 1 &pcfg_pull_none>,
1103 <2 RK_PB7 1 &pcfg_pull_none>;
1104 };
1105
1106 phy_pins: phy-pins {
1107 rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,
1108 <2 RK_PB0 2 &pcfg_pull_none>;
1109 };
1110 };
1111
1112 hdmi {
1113 hdmi_hpd: hdmi-hpd {
1114 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
1115 };
1116
1117 hdmii2c_xfer: hdmii2c-xfer {
1118 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
1119 <0 RK_PA7 2 &pcfg_pull_none>;
1120 };
1121
1122 hdmi_cec: hdmi-cec {
1123 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1124 };
1125 };
1126
1127 i2c0 {
1128 i2c0_xfer: i2c0-xfer {
1129 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1130 <0 RK_PA1 1 &pcfg_pull_none>;
1131 };
1132 };
1133
1134 i2c1 {
1135 i2c1_xfer: i2c1-xfer {
1136 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1137 <0 RK_PA3 1 &pcfg_pull_none>;
1138 };
1139 };
1140
1141 i2c2 {
1142 i2c2_xfer: i2c2-xfer {
1143 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
1144 <2 RK_PC5 1 &pcfg_pull_none>;
1145 };
1146 };
1147
1148 i2c3 {
1149 i2c3_xfer: i2c3-xfer {
1150 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1151 <0 RK_PA7 1 &pcfg_pull_none>;
1152 };
1153 };
1154
1155 spi0 {
1156 spi0_clk: spi0-clk {
1157 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
1158 };
1159 spi0_cs0: spi0-cs0 {
1160 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
1161 };
1162 spi0_tx: spi0-tx {
1163 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1164 };
1165 spi0_rx: spi0-rx {
1166 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1167 };
1168 spi0_cs1: spi0-cs1 {
1169 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
1170 };
1171 };
1172
1173 spi1 {
1174 spi1_clk: spi1-clk {
1175 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
1176 };
1177 spi1_cs0: spi1-cs0 {
1178 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;
1179 };
1180 spi1_rx: spi1-rx {
1181 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
1182 };
1183 spi1_tx: spi1-tx {
1184 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;
1185 };
1186 spi1_cs1: spi1-cs1 {
1187 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>;
1188 };
1189 };
1190
1191 i2s1 {
1192 i2s1_bus: i2s1-bus {
1193 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1194 <0 RK_PB1 1 &pcfg_pull_none>,
1195 <0 RK_PB3 1 &pcfg_pull_none>,
1196 <0 RK_PB4 1 &pcfg_pull_none>,
1197 <0 RK_PB5 1 &pcfg_pull_none>,
1198 <0 RK_PB6 1 &pcfg_pull_none>,
1199 <1 RK_PA2 2 &pcfg_pull_none>,
1200 <1 RK_PA4 2 &pcfg_pull_none>,
1201 <1 RK_PA5 2 &pcfg_pull_none>;
1202 };
1203 };
1204
1205 pwm0 {
1206 pwm0_pin: pwm0-pin {
1207 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
1208 };
1209 };
1210
1211 pwm1 {
1212 pwm1_pin: pwm1-pin {
1213 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1214 };
1215 };
1216
1217 pwm2 {
1218 pwm2_pin: pwm2-pin {
1219 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;
1220 };
1221 };
1222
1223 pwm3 {
1224 pwm3_pin: pwm3-pin {
1225 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1226 };
1227 };
1228
1229 spdif {
1230 spdif_tx: spdif-tx {
1231 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>;
1232 };
1233 };
1234
1235 tsadc {
1236 otp_pin: otp-pin {
1237 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
1238 };
1239
1240 otp_out: otp-out {
1241 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
1242 };
1243 };
1244
1245 uart0 {
1246 uart0_xfer: uart0-xfer {
1247 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,
1248 <2 RK_PD3 1 &pcfg_pull_none>;
1249 };
1250
1251 uart0_cts: uart0-cts {
1252 rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>;
1253 };
1254
1255 uart0_rts: uart0-rts {
1256 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
1257 };
1258 };
1259
1260 uart1 {
1261 uart1_xfer: uart1-xfer {
1262 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1263 <1 RK_PB2 1 &pcfg_pull_none>;
1264 };
1265
1266 uart1_cts: uart1-cts {
1267 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
1268 };
1269
1270 uart1_rts: uart1-rts {
1271 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1272 };
1273 };
1274
1275 uart2 {
1276 uart2_xfer: uart2-xfer {
1277 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1278 <1 RK_PC3 2 &pcfg_pull_none>;
1279 };
1280
1281 uart21_xfer: uart21-xfer {
1282 rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,
1283 <1 RK_PB1 2 &pcfg_pull_none>;
1284 };
1285
1286 uart2_cts: uart2-cts {
1287 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1288 };
1289
1290 uart2_rts: uart2-rts {
1291 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
1292 };
1293 };
1294 };
1295 };
