0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002
0003 /dts-v1/;
0004
0005 #include "rk322x.dtsi"
0006
0007 / {
0008 model = "Rockchip RK3228 Evaluation board";
0009 compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
0010
0011 aliases {
0012 mmc0 = &emmc;
0013 };
0014
0015 memory@60000000 {
0016 device_type = "memory";
0017 reg = <0x60000000 0x40000000>;
0018 };
0019
0020 vcc_phy: vcc-phy-regulator {
0021 compatible = "regulator-fixed";
0022 enable-active-high;
0023 regulator-name = "vcc_phy";
0024 regulator-min-microvolt = <1800000>;
0025 regulator-max-microvolt = <1800000>;
0026 regulator-always-on;
0027 regulator-boot-on;
0028 };
0029 };
0030
0031 &emmc {
0032 cap-mmc-highspeed;
0033 mmc-ddr-1_8v;
0034 disable-wp;
0035 non-removable;
0036 status = "okay";
0037 };
0038
0039 &gmac {
0040 assigned-clocks = <&cru SCLK_MAC_SRC>;
0041 assigned-clock-rates = <50000000>;
0042 clock_in_out = "output";
0043 phy-supply = <&vcc_phy>;
0044 phy-mode = "rmii";
0045 phy-handle = <&phy>;
0046 status = "okay";
0047
0048 mdio {
0049 compatible = "snps,dwmac-mdio";
0050 #address-cells = <1>;
0051 #size-cells = <0>;
0052
0053 phy: ethernet-phy@0 {
0054 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
0055 reg = <0>;
0056 clocks = <&cru SCLK_MAC_PHY>;
0057 resets = <&cru SRST_MACPHY>;
0058 phy-is-integrated;
0059 };
0060 };
0061 };
0062
0063 &tsadc {
0064 status = "okay";
0065
0066 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
0067 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
0068 };
0069
0070 &uart2 {
0071 status = "okay";
0072 };
