0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Copyright (c) 2013 MundoReader S.L.
0004 * Author: Heiko Stuebner <heiko@sntech.de>
0005 */
0006
0007 #include <dt-bindings/gpio/gpio.h>
0008 #include <dt-bindings/pinctrl/rockchip.h>
0009 #include <dt-bindings/clock/rk3066a-cru.h>
0010 #include <dt-bindings/power/rk3066-power.h>
0011 #include "rk3xxx.dtsi"
0012
0013 / {
0014 compatible = "rockchip,rk3066a";
0015
0016 cpus {
0017 #address-cells = <1>;
0018 #size-cells = <0>;
0019 enable-method = "rockchip,rk3066-smp";
0020
0021 cpu0: cpu@0 {
0022 device_type = "cpu";
0023 compatible = "arm,cortex-a9";
0024 next-level-cache = <&L2>;
0025 reg = <0x0>;
0026 operating-points =
0027 /* kHz uV */
0028 <1416000 1300000>,
0029 <1200000 1175000>,
0030 <1008000 1125000>,
0031 <816000 1125000>,
0032 <600000 1100000>,
0033 <504000 1100000>,
0034 <312000 1075000>;
0035 clock-latency = <40000>;
0036 clocks = <&cru ARMCLK>;
0037 };
0038 cpu1: cpu@1 {
0039 device_type = "cpu";
0040 compatible = "arm,cortex-a9";
0041 next-level-cache = <&L2>;
0042 reg = <0x1>;
0043 };
0044 };
0045
0046 display-subsystem {
0047 compatible = "rockchip,display-subsystem";
0048 ports = <&vop0_out>, <&vop1_out>;
0049 };
0050
0051 sram: sram@10080000 {
0052 compatible = "mmio-sram";
0053 reg = <0x10080000 0x10000>;
0054 #address-cells = <1>;
0055 #size-cells = <1>;
0056 ranges = <0 0x10080000 0x10000>;
0057
0058 smp-sram@0 {
0059 compatible = "rockchip,rk3066-smp-sram";
0060 reg = <0x0 0x50>;
0061 };
0062 };
0063
0064 vop0: vop@1010c000 {
0065 compatible = "rockchip,rk3066-vop";
0066 reg = <0x1010c000 0x19c>;
0067 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0068 clocks = <&cru ACLK_LCDC0>,
0069 <&cru DCLK_LCDC0>,
0070 <&cru HCLK_LCDC0>;
0071 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
0072 power-domains = <&power RK3066_PD_VIO>;
0073 resets = <&cru SRST_LCDC0_AXI>,
0074 <&cru SRST_LCDC0_AHB>,
0075 <&cru SRST_LCDC0_DCLK>;
0076 reset-names = "axi", "ahb", "dclk";
0077 status = "disabled";
0078
0079 vop0_out: port {
0080 #address-cells = <1>;
0081 #size-cells = <0>;
0082
0083 vop0_out_hdmi: endpoint@0 {
0084 reg = <0>;
0085 remote-endpoint = <&hdmi_in_vop0>;
0086 };
0087 };
0088 };
0089
0090 vop1: vop@1010e000 {
0091 compatible = "rockchip,rk3066-vop";
0092 reg = <0x1010e000 0x19c>;
0093 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0094 clocks = <&cru ACLK_LCDC1>,
0095 <&cru DCLK_LCDC1>,
0096 <&cru HCLK_LCDC1>;
0097 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
0098 power-domains = <&power RK3066_PD_VIO>;
0099 resets = <&cru SRST_LCDC1_AXI>,
0100 <&cru SRST_LCDC1_AHB>,
0101 <&cru SRST_LCDC1_DCLK>;
0102 reset-names = "axi", "ahb", "dclk";
0103 status = "disabled";
0104
0105 vop1_out: port {
0106 #address-cells = <1>;
0107 #size-cells = <0>;
0108
0109 vop1_out_hdmi: endpoint@0 {
0110 reg = <0>;
0111 remote-endpoint = <&hdmi_in_vop1>;
0112 };
0113 };
0114 };
0115
0116 hdmi: hdmi@10116000 {
0117 compatible = "rockchip,rk3066-hdmi";
0118 reg = <0x10116000 0x2000>;
0119 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
0120 clocks = <&cru HCLK_HDMI>;
0121 clock-names = "hclk";
0122 pinctrl-names = "default";
0123 pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
0124 power-domains = <&power RK3066_PD_VIO>;
0125 rockchip,grf = <&grf>;
0126 status = "disabled";
0127
0128 ports {
0129 #address-cells = <1>;
0130 #size-cells = <0>;
0131
0132 hdmi_in: port@0 {
0133 reg = <0>;
0134 #address-cells = <1>;
0135 #size-cells = <0>;
0136
0137 hdmi_in_vop0: endpoint@0 {
0138 reg = <0>;
0139 remote-endpoint = <&vop0_out_hdmi>;
0140 };
0141
0142 hdmi_in_vop1: endpoint@1 {
0143 reg = <1>;
0144 remote-endpoint = <&vop1_out_hdmi>;
0145 };
0146 };
0147
0148 hdmi_out: port@1 {
0149 reg = <1>;
0150 };
0151 };
0152 };
0153
0154 i2s0: i2s@10118000 {
0155 compatible = "rockchip,rk3066-i2s";
0156 reg = <0x10118000 0x2000>;
0157 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0158 pinctrl-names = "default";
0159 pinctrl-0 = <&i2s0_bus>;
0160 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
0161 clock-names = "i2s_clk", "i2s_hclk";
0162 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
0163 dma-names = "tx", "rx";
0164 rockchip,playback-channels = <8>;
0165 rockchip,capture-channels = <2>;
0166 #sound-dai-cells = <0>;
0167 status = "disabled";
0168 };
0169
0170 i2s1: i2s@1011a000 {
0171 compatible = "rockchip,rk3066-i2s";
0172 reg = <0x1011a000 0x2000>;
0173 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0174 pinctrl-names = "default";
0175 pinctrl-0 = <&i2s1_bus>;
0176 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
0177 clock-names = "i2s_clk", "i2s_hclk";
0178 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
0179 dma-names = "tx", "rx";
0180 rockchip,playback-channels = <2>;
0181 rockchip,capture-channels = <2>;
0182 #sound-dai-cells = <0>;
0183 status = "disabled";
0184 };
0185
0186 i2s2: i2s@1011c000 {
0187 compatible = "rockchip,rk3066-i2s";
0188 reg = <0x1011c000 0x2000>;
0189 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0190 pinctrl-names = "default";
0191 pinctrl-0 = <&i2s2_bus>;
0192 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
0193 clock-names = "i2s_clk", "i2s_hclk";
0194 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
0195 dma-names = "tx", "rx";
0196 rockchip,playback-channels = <2>;
0197 rockchip,capture-channels = <2>;
0198 #sound-dai-cells = <0>;
0199 status = "disabled";
0200 };
0201
0202 cru: clock-controller@20000000 {
0203 compatible = "rockchip,rk3066a-cru";
0204 reg = <0x20000000 0x1000>;
0205 clocks = <&xin24m>;
0206 clock-names = "xin24m";
0207 rockchip,grf = <&grf>;
0208 #clock-cells = <1>;
0209 #reset-cells = <1>;
0210 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
0211 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
0212 <&cru PCLK_CPU>, <&cru ACLK_PERI>,
0213 <&cru HCLK_PERI>, <&cru PCLK_PERI>;
0214 assigned-clock-rates = <400000000>, <594000000>,
0215 <300000000>, <150000000>,
0216 <75000000>, <300000000>,
0217 <150000000>, <75000000>;
0218 };
0219
0220 timer2: timer@2000e000 {
0221 compatible = "snps,dw-apb-timer";
0222 reg = <0x2000e000 0x100>;
0223 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0224 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
0225 clock-names = "timer", "pclk";
0226 };
0227
0228 efuse: efuse@20010000 {
0229 compatible = "rockchip,rk3066a-efuse";
0230 reg = <0x20010000 0x4000>;
0231 #address-cells = <1>;
0232 #size-cells = <1>;
0233 clocks = <&cru PCLK_EFUSE>;
0234 clock-names = "pclk_efuse";
0235
0236 cpu_leakage: cpu_leakage@17 {
0237 reg = <0x17 0x1>;
0238 };
0239 };
0240
0241 timer0: timer@20038000 {
0242 compatible = "snps,dw-apb-timer";
0243 reg = <0x20038000 0x100>;
0244 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
0245 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
0246 clock-names = "timer", "pclk";
0247 };
0248
0249 timer1: timer@2003a000 {
0250 compatible = "snps,dw-apb-timer";
0251 reg = <0x2003a000 0x100>;
0252 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0253 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
0254 clock-names = "timer", "pclk";
0255 };
0256
0257 tsadc: tsadc@20060000 {
0258 compatible = "rockchip,rk3066-tsadc";
0259 reg = <0x20060000 0x100>;
0260 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
0261 clock-names = "saradc", "apb_pclk";
0262 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0263 #io-channel-cells = <1>;
0264 resets = <&cru SRST_TSADC>;
0265 reset-names = "saradc-apb";
0266 status = "disabled";
0267 };
0268
0269 pinctrl: pinctrl {
0270 compatible = "rockchip,rk3066a-pinctrl";
0271 rockchip,grf = <&grf>;
0272 #address-cells = <1>;
0273 #size-cells = <1>;
0274 ranges;
0275
0276 gpio0: gpio@20034000 {
0277 compatible = "rockchip,gpio-bank";
0278 reg = <0x20034000 0x100>;
0279 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
0280 clocks = <&cru PCLK_GPIO0>;
0281
0282 gpio-controller;
0283 #gpio-cells = <2>;
0284
0285 interrupt-controller;
0286 #interrupt-cells = <2>;
0287 };
0288
0289 gpio1: gpio@2003c000 {
0290 compatible = "rockchip,gpio-bank";
0291 reg = <0x2003c000 0x100>;
0292 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0293 clocks = <&cru PCLK_GPIO1>;
0294
0295 gpio-controller;
0296 #gpio-cells = <2>;
0297
0298 interrupt-controller;
0299 #interrupt-cells = <2>;
0300 };
0301
0302 gpio2: gpio@2003e000 {
0303 compatible = "rockchip,gpio-bank";
0304 reg = <0x2003e000 0x100>;
0305 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0306 clocks = <&cru PCLK_GPIO2>;
0307
0308 gpio-controller;
0309 #gpio-cells = <2>;
0310
0311 interrupt-controller;
0312 #interrupt-cells = <2>;
0313 };
0314
0315 gpio3: gpio@20080000 {
0316 compatible = "rockchip,gpio-bank";
0317 reg = <0x20080000 0x100>;
0318 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0319 clocks = <&cru PCLK_GPIO3>;
0320
0321 gpio-controller;
0322 #gpio-cells = <2>;
0323
0324 interrupt-controller;
0325 #interrupt-cells = <2>;
0326 };
0327
0328 gpio4: gpio@20084000 {
0329 compatible = "rockchip,gpio-bank";
0330 reg = <0x20084000 0x100>;
0331 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0332 clocks = <&cru PCLK_GPIO4>;
0333
0334 gpio-controller;
0335 #gpio-cells = <2>;
0336
0337 interrupt-controller;
0338 #interrupt-cells = <2>;
0339 };
0340
0341 gpio6: gpio@2000a000 {
0342 compatible = "rockchip,gpio-bank";
0343 reg = <0x2000a000 0x100>;
0344 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0345 clocks = <&cru PCLK_GPIO6>;
0346
0347 gpio-controller;
0348 #gpio-cells = <2>;
0349
0350 interrupt-controller;
0351 #interrupt-cells = <2>;
0352 };
0353
0354 pcfg_pull_default: pcfg-pull-default {
0355 bias-pull-pin-default;
0356 };
0357
0358 pcfg_pull_none: pcfg-pull-none {
0359 bias-disable;
0360 };
0361
0362 emac {
0363 emac_xfer: emac-xfer {
0364 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */
0365 <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */
0366 <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */
0367 <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */
0368 <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */
0369 <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */
0370 <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */
0371 <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */
0372 };
0373
0374 emac_mdio: emac-mdio {
0375 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */
0376 <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */
0377 };
0378 };
0379
0380 emmc {
0381 emmc_clk: emmc-clk {
0382 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>;
0383 };
0384
0385 emmc_cmd: emmc-cmd {
0386 rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>;
0387 };
0388
0389 emmc_rst: emmc-rst {
0390 rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>;
0391 };
0392
0393 /*
0394 * The data pins are shared between nandc and emmc and
0395 * not accessible through pinctrl. Also they should've
0396 * been already set correctly by firmware, as
0397 * flash/emmc is the boot-device.
0398 */
0399 };
0400
0401 hdmi {
0402 hdmi_hpd: hdmi-hpd {
0403 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
0404 };
0405
0406 hdmii2c_xfer: hdmii2c-xfer {
0407 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
0408 <0 RK_PA2 1 &pcfg_pull_none>;
0409 };
0410 };
0411
0412 i2c0 {
0413 i2c0_xfer: i2c0-xfer {
0414 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>,
0415 <2 RK_PD5 1 &pcfg_pull_none>;
0416 };
0417 };
0418
0419 i2c1 {
0420 i2c1_xfer: i2c1-xfer {
0421 rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>,
0422 <2 RK_PD7 1 &pcfg_pull_none>;
0423 };
0424 };
0425
0426 i2c2 {
0427 i2c2_xfer: i2c2-xfer {
0428 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>,
0429 <3 RK_PA1 1 &pcfg_pull_none>;
0430 };
0431 };
0432
0433 i2c3 {
0434 i2c3_xfer: i2c3-xfer {
0435 rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>,
0436 <3 RK_PA3 2 &pcfg_pull_none>;
0437 };
0438 };
0439
0440 i2c4 {
0441 i2c4_xfer: i2c4-xfer {
0442 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
0443 <3 RK_PA5 1 &pcfg_pull_none>;
0444 };
0445 };
0446
0447 pwm0 {
0448 pwm0_out: pwm0-out {
0449 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
0450 };
0451 };
0452
0453 pwm1 {
0454 pwm1_out: pwm1-out {
0455 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
0456 };
0457 };
0458
0459 pwm2 {
0460 pwm2_out: pwm2-out {
0461 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
0462 };
0463 };
0464
0465 pwm3 {
0466 pwm3_out: pwm3-out {
0467 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
0468 };
0469 };
0470
0471 spi0 {
0472 spi0_clk: spi0-clk {
0473 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>;
0474 };
0475 spi0_cs0: spi0-cs0 {
0476 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>;
0477 };
0478 spi0_tx: spi0-tx {
0479 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>;
0480 };
0481 spi0_rx: spi0-rx {
0482 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>;
0483 };
0484 spi0_cs1: spi0-cs1 {
0485 rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>;
0486 };
0487 };
0488
0489 spi1 {
0490 spi1_clk: spi1-clk {
0491 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>;
0492 };
0493 spi1_cs0: spi1-cs0 {
0494 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>;
0495 };
0496 spi1_rx: spi1-rx {
0497 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>;
0498 };
0499 spi1_tx: spi1-tx {
0500 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>;
0501 };
0502 spi1_cs1: spi1-cs1 {
0503 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>;
0504 };
0505 };
0506
0507 uart0 {
0508 uart0_xfer: uart0-xfer {
0509 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
0510 <1 RK_PA1 1 &pcfg_pull_default>;
0511 };
0512
0513 uart0_cts: uart0-cts {
0514 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>;
0515 };
0516
0517 uart0_rts: uart0-rts {
0518 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>;
0519 };
0520 };
0521
0522 uart1 {
0523 uart1_xfer: uart1-xfer {
0524 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>,
0525 <1 RK_PA5 1 &pcfg_pull_default>;
0526 };
0527
0528 uart1_cts: uart1-cts {
0529 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>;
0530 };
0531
0532 uart1_rts: uart1-rts {
0533 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
0534 };
0535 };
0536
0537 uart2 {
0538 uart2_xfer: uart2-xfer {
0539 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
0540 <1 RK_PB1 1 &pcfg_pull_default>;
0541 };
0542 /* no rts / cts for uart2 */
0543 };
0544
0545 uart3 {
0546 uart3_xfer: uart3-xfer {
0547 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>,
0548 <3 RK_PD4 1 &pcfg_pull_default>;
0549 };
0550
0551 uart3_cts: uart3-cts {
0552 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>;
0553 };
0554
0555 uart3_rts: uart3-rts {
0556 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>;
0557 };
0558 };
0559
0560 sd0 {
0561 sd0_clk: sd0-clk {
0562 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>;
0563 };
0564
0565 sd0_cmd: sd0-cmd {
0566 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>;
0567 };
0568
0569 sd0_cd: sd0-cd {
0570 rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>;
0571 };
0572
0573 sd0_wp: sd0-wp {
0574 rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>;
0575 };
0576
0577 sd0_bus1: sd0-bus-width1 {
0578 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>;
0579 };
0580
0581 sd0_bus4: sd0-bus-width4 {
0582 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>,
0583 <3 RK_PB3 1 &pcfg_pull_default>,
0584 <3 RK_PB4 1 &pcfg_pull_default>,
0585 <3 RK_PB5 1 &pcfg_pull_default>;
0586 };
0587 };
0588
0589 sd1 {
0590 sd1_clk: sd1-clk {
0591 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>;
0592 };
0593
0594 sd1_cmd: sd1-cmd {
0595 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>;
0596 };
0597
0598 sd1_cd: sd1-cd {
0599 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>;
0600 };
0601
0602 sd1_wp: sd1-wp {
0603 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>;
0604 };
0605
0606 sd1_bus1: sd1-bus-width1 {
0607 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>;
0608 };
0609
0610 sd1_bus4: sd1-bus-width4 {
0611 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>,
0612 <3 RK_PC2 1 &pcfg_pull_default>,
0613 <3 RK_PC3 1 &pcfg_pull_default>,
0614 <3 RK_PC4 1 &pcfg_pull_default>;
0615 };
0616 };
0617
0618 i2s0 {
0619 i2s0_bus: i2s0-bus {
0620 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>,
0621 <0 RK_PB0 1 &pcfg_pull_default>,
0622 <0 RK_PB1 1 &pcfg_pull_default>,
0623 <0 RK_PB2 1 &pcfg_pull_default>,
0624 <0 RK_PB3 1 &pcfg_pull_default>,
0625 <0 RK_PB4 1 &pcfg_pull_default>,
0626 <0 RK_PB5 1 &pcfg_pull_default>,
0627 <0 RK_PB6 1 &pcfg_pull_default>,
0628 <0 RK_PB7 1 &pcfg_pull_default>;
0629 };
0630 };
0631
0632 i2s1 {
0633 i2s1_bus: i2s1-bus {
0634 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
0635 <0 RK_PC1 1 &pcfg_pull_default>,
0636 <0 RK_PC2 1 &pcfg_pull_default>,
0637 <0 RK_PC3 1 &pcfg_pull_default>,
0638 <0 RK_PC4 1 &pcfg_pull_default>,
0639 <0 RK_PC5 1 &pcfg_pull_default>;
0640 };
0641 };
0642
0643 i2s2 {
0644 i2s2_bus: i2s2-bus {
0645 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>,
0646 <0 RK_PD1 1 &pcfg_pull_default>,
0647 <0 RK_PD2 1 &pcfg_pull_default>,
0648 <0 RK_PD3 1 &pcfg_pull_default>,
0649 <0 RK_PD4 1 &pcfg_pull_default>,
0650 <0 RK_PD5 1 &pcfg_pull_default>;
0651 };
0652 };
0653 };
0654 };
0655
0656 &gpu {
0657 compatible = "rockchip,rk3066-mali", "arm,mali-400";
0658 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0659 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0660 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0661 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0662 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0663 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0664 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0665 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0666 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0667 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0668 interrupt-names = "gp",
0669 "gpmmu",
0670 "pp0",
0671 "ppmmu0",
0672 "pp1",
0673 "ppmmu1",
0674 "pp2",
0675 "ppmmu2",
0676 "pp3",
0677 "ppmmu3";
0678 power-domains = <&power RK3066_PD_GPU>;
0679 };
0680
0681 &grf {
0682 compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd";
0683
0684 usbphy: usbphy {
0685 compatible = "rockchip,rk3066a-usb-phy";
0686 #address-cells = <1>;
0687 #size-cells = <0>;
0688 status = "disabled";
0689
0690 usbphy0: usb-phy@17c {
0691 reg = <0x17c>;
0692 clocks = <&cru SCLK_OTGPHY0>;
0693 clock-names = "phyclk";
0694 #clock-cells = <0>;
0695 #phy-cells = <0>;
0696 };
0697
0698 usbphy1: usb-phy@188 {
0699 reg = <0x188>;
0700 clocks = <&cru SCLK_OTGPHY1>;
0701 clock-names = "phyclk";
0702 #clock-cells = <0>;
0703 #phy-cells = <0>;
0704 };
0705 };
0706 };
0707
0708 &i2c0 {
0709 pinctrl-names = "default";
0710 pinctrl-0 = <&i2c0_xfer>;
0711 };
0712
0713 &i2c1 {
0714 pinctrl-names = "default";
0715 pinctrl-0 = <&i2c1_xfer>;
0716 };
0717
0718 &i2c2 {
0719 pinctrl-names = "default";
0720 pinctrl-0 = <&i2c2_xfer>;
0721 };
0722
0723 &i2c3 {
0724 pinctrl-names = "default";
0725 pinctrl-0 = <&i2c3_xfer>;
0726 };
0727
0728 &i2c4 {
0729 pinctrl-names = "default";
0730 pinctrl-0 = <&i2c4_xfer>;
0731 };
0732
0733 &mmc0 {
0734 clock-frequency = <50000000>;
0735 dmas = <&dmac2 1>;
0736 dma-names = "rx-tx";
0737 max-frequency = <50000000>;
0738 pinctrl-names = "default";
0739 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
0740 };
0741
0742 &mmc1 {
0743 dmas = <&dmac2 3>;
0744 dma-names = "rx-tx";
0745 pinctrl-names = "default";
0746 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
0747 };
0748
0749 &emmc {
0750 dmas = <&dmac2 4>;
0751 dma-names = "rx-tx";
0752 };
0753
0754 &pmu {
0755 power: power-controller {
0756 compatible = "rockchip,rk3066-power-controller";
0757 #power-domain-cells = <1>;
0758 #address-cells = <1>;
0759 #size-cells = <0>;
0760
0761 power-domain@RK3066_PD_VIO {
0762 reg = <RK3066_PD_VIO>;
0763 clocks = <&cru ACLK_LCDC0>,
0764 <&cru ACLK_LCDC1>,
0765 <&cru DCLK_LCDC0>,
0766 <&cru DCLK_LCDC1>,
0767 <&cru HCLK_LCDC0>,
0768 <&cru HCLK_LCDC1>,
0769 <&cru SCLK_CIF1>,
0770 <&cru ACLK_CIF1>,
0771 <&cru HCLK_CIF1>,
0772 <&cru SCLK_CIF0>,
0773 <&cru ACLK_CIF0>,
0774 <&cru HCLK_CIF0>,
0775 <&cru HCLK_HDMI>,
0776 <&cru ACLK_IPP>,
0777 <&cru HCLK_IPP>,
0778 <&cru ACLK_RGA>,
0779 <&cru HCLK_RGA>;
0780 pm_qos = <&qos_lcdc0>,
0781 <&qos_lcdc1>,
0782 <&qos_cif0>,
0783 <&qos_cif1>,
0784 <&qos_ipp>,
0785 <&qos_rga>;
0786 #power-domain-cells = <0>;
0787 };
0788
0789 power-domain@RK3066_PD_VIDEO {
0790 reg = <RK3066_PD_VIDEO>;
0791 clocks = <&cru ACLK_VDPU>,
0792 <&cru ACLK_VEPU>,
0793 <&cru HCLK_VDPU>,
0794 <&cru HCLK_VEPU>;
0795 pm_qos = <&qos_vpu>;
0796 #power-domain-cells = <0>;
0797 };
0798
0799 power-domain@RK3066_PD_GPU {
0800 reg = <RK3066_PD_GPU>;
0801 clocks = <&cru ACLK_GPU>;
0802 pm_qos = <&qos_gpu>;
0803 #power-domain-cells = <0>;
0804 };
0805 };
0806 };
0807
0808 &pwm0 {
0809 pinctrl-names = "default";
0810 pinctrl-0 = <&pwm0_out>;
0811 };
0812
0813 &pwm1 {
0814 pinctrl-names = "default";
0815 pinctrl-0 = <&pwm1_out>;
0816 };
0817
0818 &pwm2 {
0819 pinctrl-names = "default";
0820 pinctrl-0 = <&pwm2_out>;
0821 };
0822
0823 &pwm3 {
0824 pinctrl-names = "default";
0825 pinctrl-0 = <&pwm3_out>;
0826 };
0827
0828 &spi0 {
0829 pinctrl-names = "default";
0830 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
0831 };
0832
0833 &spi1 {
0834 pinctrl-names = "default";
0835 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
0836 };
0837
0838 &uart0 {
0839 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
0840 dmas = <&dmac1_s 0>, <&dmac1_s 1>;
0841 dma-names = "tx", "rx";
0842 pinctrl-names = "default";
0843 pinctrl-0 = <&uart0_xfer>;
0844 };
0845
0846 &uart1 {
0847 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
0848 dmas = <&dmac1_s 2>, <&dmac1_s 3>;
0849 dma-names = "tx", "rx";
0850 pinctrl-names = "default";
0851 pinctrl-0 = <&uart1_xfer>;
0852 };
0853
0854 &uart2 {
0855 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
0856 dmas = <&dmac2 6>, <&dmac2 7>;
0857 dma-names = "tx", "rx";
0858 pinctrl-names = "default";
0859 pinctrl-0 = <&uart2_xfer>;
0860 };
0861
0862 &uart3 {
0863 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
0864 dmas = <&dmac2 8>, <&dmac2 9>;
0865 dma-names = "tx", "rx";
0866 pinctrl-names = "default";
0867 pinctrl-0 = <&uart3_xfer>;
0868 };
0869
0870 &vpu {
0871 power-domains = <&power RK3066_PD_VIDEO>;
0872 };
0873
0874 &wdt {
0875 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
0876 };
0877
0878 &emac {
0879 compatible = "rockchip,rk3066-emac";
0880 };
