0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002
0003 #include <dt-bindings/gpio/gpio.h>
0004 #include <dt-bindings/interrupt-controller/irq.h>
0005 #include <dt-bindings/interrupt-controller/arm-gic.h>
0006 #include <dt-bindings/pinctrl/rockchip.h>
0007 #include <dt-bindings/clock/rk3036-cru.h>
0008 #include <dt-bindings/soc/rockchip,boot-mode.h>
0009 #include <dt-bindings/power/rk3036-power.h>
0010
0011 / {
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014
0015 compatible = "rockchip,rk3036";
0016
0017 interrupt-parent = <&gic>;
0018
0019 aliases {
0020 i2c0 = &i2c0;
0021 i2c1 = &i2c1;
0022 i2c2 = &i2c2;
0023 mshc0 = &emmc;
0024 mshc1 = &sdmmc;
0025 mshc2 = &sdio;
0026 serial0 = &uart0;
0027 serial1 = &uart1;
0028 serial2 = &uart2;
0029 spi = &spi;
0030 };
0031
0032 cpus {
0033 #address-cells = <1>;
0034 #size-cells = <0>;
0035 enable-method = "rockchip,rk3036-smp";
0036
0037 cpu0: cpu@f00 {
0038 device_type = "cpu";
0039 compatible = "arm,cortex-a7";
0040 reg = <0xf00>;
0041 resets = <&cru SRST_CORE0>;
0042 operating-points = <
0043 /* KHz uV */
0044 816000 1000000
0045 >;
0046 clock-latency = <40000>;
0047 clocks = <&cru ARMCLK>;
0048 };
0049
0050 cpu1: cpu@f01 {
0051 device_type = "cpu";
0052 compatible = "arm,cortex-a7";
0053 reg = <0xf01>;
0054 resets = <&cru SRST_CORE1>;
0055 };
0056 };
0057
0058 arm-pmu {
0059 compatible = "arm,cortex-a7-pmu";
0060 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
0061 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0062 interrupt-affinity = <&cpu0>, <&cpu1>;
0063 };
0064
0065 display-subsystem {
0066 compatible = "rockchip,display-subsystem";
0067 ports = <&vop_out>;
0068 };
0069
0070 timer {
0071 compatible = "arm,armv7-timer";
0072 arm,cpu-registers-not-fw-configured;
0073 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
0074 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
0075 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
0076 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
0077 clock-frequency = <24000000>;
0078 };
0079
0080 xin24m: oscillator {
0081 compatible = "fixed-clock";
0082 clock-frequency = <24000000>;
0083 clock-output-names = "xin24m";
0084 #clock-cells = <0>;
0085 };
0086
0087 bus_intmem: sram@10080000 {
0088 compatible = "mmio-sram";
0089 reg = <0x10080000 0x2000>;
0090 #address-cells = <1>;
0091 #size-cells = <1>;
0092 ranges = <0 0x10080000 0x2000>;
0093
0094 smp-sram@0 {
0095 compatible = "rockchip,rk3066-smp-sram";
0096 reg = <0x00 0x10>;
0097 };
0098 };
0099
0100 gpu: gpu@10090000 {
0101 compatible = "rockchip,rk3036-mali", "arm,mali-400";
0102 reg = <0x10090000 0x10000>;
0103 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0104 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0105 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0106 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0107 interrupt-names = "gp",
0108 "gpmmu",
0109 "pp0",
0110 "ppmmu0";
0111 assigned-clocks = <&cru SCLK_GPU>;
0112 assigned-clock-rates = <100000000>;
0113 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
0114 clock-names = "bus", "core";
0115 power-domains = <&power RK3036_PD_GPU>;
0116 resets = <&cru SRST_GPU>;
0117 status = "disabled";
0118 };
0119
0120 vpu: video-codec@10108000 {
0121 compatible = "rockchip,rk3036-vpu";
0122 reg = <0x10108000 0x800>;
0123 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0124 interrupt-names = "vdpu";
0125 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
0126 clock-names = "aclk", "hclk";
0127 iommus = <&vpu_mmu>;
0128 power-domains = <&power RK3036_PD_VPU>;
0129 };
0130
0131 vpu_mmu: iommu@10108800 {
0132 compatible = "rockchip,iommu";
0133 reg = <0x10108800 0x100>;
0134 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0135 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
0136 clock-names = "aclk", "iface";
0137 power-domains = <&power RK3036_PD_VPU>;
0138 #iommu-cells = <0>;
0139 };
0140
0141 vop: vop@10118000 {
0142 compatible = "rockchip,rk3036-vop";
0143 reg = <0x10118000 0x19c>;
0144 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
0145 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
0146 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
0147 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
0148 reset-names = "axi", "ahb", "dclk";
0149 iommus = <&vop_mmu>;
0150 power-domains = <&power RK3036_PD_VIO>;
0151 status = "disabled";
0152
0153 vop_out: port {
0154 #address-cells = <1>;
0155 #size-cells = <0>;
0156 vop_out_hdmi: endpoint@0 {
0157 reg = <0>;
0158 remote-endpoint = <&hdmi_in_vop>;
0159 };
0160 };
0161 };
0162
0163 vop_mmu: iommu@10118300 {
0164 compatible = "rockchip,iommu";
0165 reg = <0x10118300 0x100>;
0166 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
0167 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
0168 clock-names = "aclk", "iface";
0169 power-domains = <&power RK3036_PD_VIO>;
0170 #iommu-cells = <0>;
0171 status = "disabled";
0172 };
0173
0174 qos_gpu: qos@1012d000 {
0175 compatible = "rockchip,rk3036-qos", "syscon";
0176 reg = <0x1012d000 0x20>;
0177 };
0178
0179 qos_vpu: qos@1012e000 {
0180 compatible = "rockchip,rk3036-qos", "syscon";
0181 reg = <0x1012e000 0x20>;
0182 };
0183
0184 qos_vio: qos@1012f000 {
0185 compatible = "rockchip,rk3036-qos", "syscon";
0186 reg = <0x1012f000 0x20>;
0187 };
0188
0189 gic: interrupt-controller@10139000 {
0190 compatible = "arm,gic-400";
0191 interrupt-controller;
0192 #interrupt-cells = <3>;
0193 #address-cells = <0>;
0194
0195 reg = <0x10139000 0x1000>,
0196 <0x1013a000 0x2000>,
0197 <0x1013c000 0x2000>,
0198 <0x1013e000 0x2000>;
0199 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
0200 };
0201
0202 usb_otg: usb@10180000 {
0203 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
0204 "snps,dwc2";
0205 reg = <0x10180000 0x40000>;
0206 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0207 clocks = <&cru HCLK_OTG0>;
0208 clock-names = "otg";
0209 dr_mode = "otg";
0210 g-np-tx-fifo-size = <16>;
0211 g-rx-fifo-size = <275>;
0212 g-tx-fifo-size = <256 128 128 64 64 32>;
0213 status = "disabled";
0214 };
0215
0216 usb_host: usb@101c0000 {
0217 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
0218 "snps,dwc2";
0219 reg = <0x101c0000 0x40000>;
0220 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0221 clocks = <&cru HCLK_OTG1>;
0222 clock-names = "otg";
0223 dr_mode = "host";
0224 status = "disabled";
0225 };
0226
0227 emac: ethernet@10200000 {
0228 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
0229 reg = <0x10200000 0x4000>;
0230 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0231 #address-cells = <1>;
0232 #size-cells = <0>;
0233 rockchip,grf = <&grf>;
0234 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
0235 clock-names = "hclk", "macref", "macclk";
0236 /*
0237 * Fix the emac parent clock is DPLL instead of APLL.
0238 * since that will cause some unstable things if the cpufreq
0239 * is working. (e.g: the accurate 50MHz what mac_ref need)
0240 */
0241 assigned-clocks = <&cru SCLK_MACPLL>;
0242 assigned-clock-parents = <&cru PLL_DPLL>;
0243 max-speed = <100>;
0244 phy-mode = "rmii";
0245 status = "disabled";
0246 };
0247
0248 sdmmc: mmc@10214000 {
0249 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
0250 reg = <0x10214000 0x4000>;
0251 clock-frequency = <37500000>;
0252 max-frequency = <37500000>;
0253 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
0254 clock-names = "biu", "ciu";
0255 fifo-depth = <0x100>;
0256 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0257 resets = <&cru SRST_MMC0>;
0258 reset-names = "reset";
0259 status = "disabled";
0260 };
0261
0262 sdio: mmc@10218000 {
0263 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
0264 reg = <0x10218000 0x4000>;
0265 max-frequency = <37500000>;
0266 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
0267 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
0268 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
0269 fifo-depth = <0x100>;
0270 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0271 resets = <&cru SRST_SDIO>;
0272 reset-names = "reset";
0273 status = "disabled";
0274 };
0275
0276 emmc: mmc@1021c000 {
0277 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
0278 reg = <0x1021c000 0x4000>;
0279 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0280 bus-width = <8>;
0281 cap-mmc-highspeed;
0282 clock-frequency = <37500000>;
0283 max-frequency = <37500000>;
0284 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
0285 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
0286 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
0287 rockchip,default-sample-phase = <158>;
0288 disable-wp;
0289 dmas = <&pdma 12>;
0290 dma-names = "rx-tx";
0291 fifo-depth = <0x100>;
0292 mmc-ddr-1_8v;
0293 non-removable;
0294 pinctrl-names = "default";
0295 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
0296 resets = <&cru SRST_EMMC>;
0297 reset-names = "reset";
0298 status = "disabled";
0299 };
0300
0301 i2s: i2s@10220000 {
0302 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
0303 reg = <0x10220000 0x4000>;
0304 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0305 clock-names = "i2s_clk", "i2s_hclk";
0306 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
0307 dmas = <&pdma 0>, <&pdma 1>;
0308 dma-names = "tx", "rx";
0309 pinctrl-names = "default";
0310 pinctrl-0 = <&i2s_bus>;
0311 #sound-dai-cells = <0>;
0312 status = "disabled";
0313 };
0314
0315 nfc: nand-controller@10500000 {
0316 compatible = "rockchip,rk3036-nfc",
0317 "rockchip,rk2928-nfc";
0318 reg = <0x10500000 0x4000>;
0319 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0320 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
0321 clock-names = "ahb", "nfc";
0322 assigned-clocks = <&cru SCLK_NANDC>;
0323 assigned-clock-rates = <150000000>;
0324 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
0325 &flash_rdn &flash_rdy &flash_wrn>;
0326 pinctrl-names = "default";
0327 status = "disabled";
0328 };
0329
0330 cru: clock-controller@20000000 {
0331 compatible = "rockchip,rk3036-cru";
0332 reg = <0x20000000 0x1000>;
0333 clocks = <&xin24m>;
0334 clock-names = "xin24m";
0335 rockchip,grf = <&grf>;
0336 #clock-cells = <1>;
0337 #reset-cells = <1>;
0338 assigned-clocks = <&cru PLL_GPLL>;
0339 assigned-clock-rates = <594000000>;
0340 };
0341
0342 grf: syscon@20008000 {
0343 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
0344 reg = <0x20008000 0x1000>;
0345
0346 power: power-controller {
0347 compatible = "rockchip,rk3036-power-controller";
0348 #power-domain-cells = <1>;
0349 #address-cells = <1>;
0350 #size-cells = <0>;
0351
0352 power-domain@RK3036_PD_VIO {
0353 reg = <RK3036_PD_VIO>;
0354 clocks = <&cru ACLK_LCDC>,
0355 <&cru HCLK_LCDC>,
0356 <&cru SCLK_LCDC>;
0357 pm_qos = <&qos_vio>;
0358 #power-domain-cells = <0>;
0359 };
0360
0361 power-domain@RK3036_PD_VPU {
0362 reg = <RK3036_PD_VPU>;
0363 clocks = <&cru ACLK_VCODEC>,
0364 <&cru HCLK_VCODEC>;
0365 pm_qos = <&qos_vpu>;
0366 #power-domain-cells = <0>;
0367 };
0368
0369 power-domain@RK3036_PD_GPU {
0370 reg = <RK3036_PD_GPU>;
0371 clocks = <&cru SCLK_GPU>;
0372 pm_qos = <&qos_gpu>;
0373 #power-domain-cells = <0>;
0374 };
0375 };
0376
0377 reboot-mode {
0378 compatible = "syscon-reboot-mode";
0379 offset = <0x1d8>;
0380 mode-normal = <BOOT_NORMAL>;
0381 mode-recovery = <BOOT_RECOVERY>;
0382 mode-bootloader = <BOOT_FASTBOOT>;
0383 mode-loader = <BOOT_BL_DOWNLOAD>;
0384 };
0385 };
0386
0387 acodec: acodec-ana@20030000 {
0388 compatible = "rk3036-codec";
0389 reg = <0x20030000 0x4000>;
0390 rockchip,grf = <&grf>;
0391 clock-names = "acodec_pclk";
0392 clocks = <&cru PCLK_ACODEC>;
0393 status = "disabled";
0394 };
0395
0396 hdmi: hdmi@20034000 {
0397 compatible = "rockchip,rk3036-inno-hdmi";
0398 reg = <0x20034000 0x4000>;
0399 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0400 clocks = <&cru PCLK_HDMI>;
0401 clock-names = "pclk";
0402 rockchip,grf = <&grf>;
0403 pinctrl-names = "default";
0404 pinctrl-0 = <&hdmi_ctl>;
0405 status = "disabled";
0406
0407 hdmi_in: port {
0408 #address-cells = <1>;
0409 #size-cells = <0>;
0410 hdmi_in_vop: endpoint@0 {
0411 reg = <0>;
0412 remote-endpoint = <&vop_out_hdmi>;
0413 };
0414 };
0415 };
0416
0417 timer: timer@20044000 {
0418 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
0419 reg = <0x20044000 0x20>;
0420 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0421 clocks = <&cru PCLK_TIMER>, <&xin24m>;
0422 clock-names = "pclk", "timer";
0423 };
0424
0425 pwm0: pwm@20050000 {
0426 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
0427 reg = <0x20050000 0x10>;
0428 #pwm-cells = <3>;
0429 clocks = <&cru PCLK_PWM>;
0430 pinctrl-names = "default";
0431 pinctrl-0 = <&pwm0_pin>;
0432 status = "disabled";
0433 };
0434
0435 pwm1: pwm@20050010 {
0436 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
0437 reg = <0x20050010 0x10>;
0438 #pwm-cells = <3>;
0439 clocks = <&cru PCLK_PWM>;
0440 pinctrl-names = "default";
0441 pinctrl-0 = <&pwm1_pin>;
0442 status = "disabled";
0443 };
0444
0445 pwm2: pwm@20050020 {
0446 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
0447 reg = <0x20050020 0x10>;
0448 #pwm-cells = <3>;
0449 clocks = <&cru PCLK_PWM>;
0450 pinctrl-names = "default";
0451 pinctrl-0 = <&pwm2_pin>;
0452 status = "disabled";
0453 };
0454
0455 pwm3: pwm@20050030 {
0456 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
0457 reg = <0x20050030 0x10>;
0458 #pwm-cells = <2>;
0459 clocks = <&cru PCLK_PWM>;
0460 pinctrl-names = "default";
0461 pinctrl-0 = <&pwm3_pin>;
0462 status = "disabled";
0463 };
0464
0465 i2c1: i2c@20056000 {
0466 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
0467 reg = <0x20056000 0x1000>;
0468 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0469 #address-cells = <1>;
0470 #size-cells = <0>;
0471 clock-names = "i2c";
0472 clocks = <&cru PCLK_I2C1>;
0473 pinctrl-names = "default";
0474 pinctrl-0 = <&i2c1_xfer>;
0475 status = "disabled";
0476 };
0477
0478 i2c2: i2c@2005a000 {
0479 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
0480 reg = <0x2005a000 0x1000>;
0481 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0482 #address-cells = <1>;
0483 #size-cells = <0>;
0484 clock-names = "i2c";
0485 clocks = <&cru PCLK_I2C2>;
0486 pinctrl-names = "default";
0487 pinctrl-0 = <&i2c2_xfer>;
0488 status = "disabled";
0489 };
0490
0491 uart0: serial@20060000 {
0492 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
0493 reg = <0x20060000 0x100>;
0494 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0495 reg-shift = <2>;
0496 reg-io-width = <4>;
0497 clock-frequency = <24000000>;
0498 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
0499 clock-names = "baudclk", "apb_pclk";
0500 pinctrl-names = "default";
0501 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
0502 status = "disabled";
0503 };
0504
0505 uart1: serial@20064000 {
0506 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
0507 reg = <0x20064000 0x100>;
0508 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0509 reg-shift = <2>;
0510 reg-io-width = <4>;
0511 clock-frequency = <24000000>;
0512 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
0513 clock-names = "baudclk", "apb_pclk";
0514 pinctrl-names = "default";
0515 pinctrl-0 = <&uart1_xfer>;
0516 status = "disabled";
0517 };
0518
0519 uart2: serial@20068000 {
0520 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
0521 reg = <0x20068000 0x100>;
0522 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0523 reg-shift = <2>;
0524 reg-io-width = <4>;
0525 clock-frequency = <24000000>;
0526 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
0527 clock-names = "baudclk", "apb_pclk";
0528 pinctrl-names = "default";
0529 pinctrl-0 = <&uart2_xfer>;
0530 status = "disabled";
0531 };
0532
0533 i2c0: i2c@20072000 {
0534 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
0535 reg = <0x20072000 0x1000>;
0536 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0537 #address-cells = <1>;
0538 #size-cells = <0>;
0539 clock-names = "i2c";
0540 clocks = <&cru PCLK_I2C0>;
0541 pinctrl-names = "default";
0542 pinctrl-0 = <&i2c0_xfer>;
0543 status = "disabled";
0544 };
0545
0546 spi: spi@20074000 {
0547 compatible = "rockchip,rockchip-spi";
0548 reg = <0x20074000 0x1000>;
0549 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0550 clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
0551 clock-names = "apb-pclk","spi_pclk";
0552 dmas = <&pdma 8>, <&pdma 9>;
0553 dma-names = "tx", "rx";
0554 pinctrl-names = "default";
0555 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
0556 #address-cells = <1>;
0557 #size-cells = <0>;
0558 status = "disabled";
0559 };
0560
0561 pdma: dma-controller@20078000 {
0562 compatible = "arm,pl330", "arm,primecell";
0563 reg = <0x20078000 0x4000>;
0564 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0565 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0566 #dma-cells = <1>;
0567 arm,pl330-broken-no-flushp;
0568 arm,pl330-periph-burst;
0569 clocks = <&cru ACLK_DMAC2>;
0570 clock-names = "apb_pclk";
0571 };
0572
0573 pinctrl: pinctrl {
0574 compatible = "rockchip,rk3036-pinctrl";
0575 rockchip,grf = <&grf>;
0576 #address-cells = <1>;
0577 #size-cells = <1>;
0578 ranges;
0579
0580 gpio0: gpio@2007c000 {
0581 compatible = "rockchip,gpio-bank";
0582 reg = <0x2007c000 0x100>;
0583 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0584 clocks = <&cru PCLK_GPIO0>;
0585
0586 gpio-controller;
0587 #gpio-cells = <2>;
0588
0589 interrupt-controller;
0590 #interrupt-cells = <2>;
0591 };
0592
0593 gpio1: gpio@20080000 {
0594 compatible = "rockchip,gpio-bank";
0595 reg = <0x20080000 0x100>;
0596 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0597 clocks = <&cru PCLK_GPIO1>;
0598
0599 gpio-controller;
0600 #gpio-cells = <2>;
0601
0602 interrupt-controller;
0603 #interrupt-cells = <2>;
0604 };
0605
0606 gpio2: gpio@20084000 {
0607 compatible = "rockchip,gpio-bank";
0608 reg = <0x20084000 0x100>;
0609 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0610 clocks = <&cru PCLK_GPIO2>;
0611
0612 gpio-controller;
0613 #gpio-cells = <2>;
0614
0615 interrupt-controller;
0616 #interrupt-cells = <2>;
0617 };
0618
0619 pcfg_pull_default: pcfg-pull-default {
0620 bias-pull-pin-default;
0621 };
0622
0623 pcfg_pull_none: pcfg-pull-none {
0624 bias-disable;
0625 };
0626
0627 pwm0 {
0628 pwm0_pin: pwm0-pin {
0629 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
0630 };
0631 };
0632
0633 pwm1 {
0634 pwm1_pin: pwm1-pin {
0635 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
0636 };
0637 };
0638
0639 pwm2 {
0640 pwm2_pin: pwm2-pin {
0641 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
0642 };
0643 };
0644
0645 pwm3 {
0646 pwm3_pin: pwm3-pin {
0647 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
0648 };
0649 };
0650
0651 sdmmc {
0652 sdmmc_clk: sdmmc-clk {
0653 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
0654 };
0655
0656 sdmmc_cmd: sdmmc-cmd {
0657 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
0658 };
0659
0660 sdmmc_cd: sdmmc-cd {
0661 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
0662 };
0663
0664 sdmmc_bus1: sdmmc-bus1 {
0665 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
0666 };
0667
0668 sdmmc_bus4: sdmmc-bus4 {
0669 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
0670 <1 RK_PC3 1 &pcfg_pull_default>,
0671 <1 RK_PC4 1 &pcfg_pull_default>,
0672 <1 RK_PC5 1 &pcfg_pull_default>;
0673 };
0674 };
0675
0676 sdio {
0677 sdio_bus1: sdio-bus1 {
0678 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
0679 };
0680
0681 sdio_bus4: sdio-bus4 {
0682 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
0683 <0 RK_PB4 1 &pcfg_pull_default>,
0684 <0 RK_PB5 1 &pcfg_pull_default>,
0685 <0 RK_PB6 1 &pcfg_pull_default>;
0686 };
0687
0688 sdio_cmd: sdio-cmd {
0689 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
0690 };
0691
0692 sdio_clk: sdio-clk {
0693 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
0694 };
0695 };
0696
0697 emmc {
0698 /*
0699 * We run eMMC at max speed; bump up drive strength.
0700 * We also have external pulls, so disable the internal ones.
0701 */
0702 emmc_clk: emmc-clk {
0703 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
0704 };
0705
0706 emmc_cmd: emmc-cmd {
0707 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
0708 };
0709
0710 emmc_bus8: emmc-bus8 {
0711 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
0712 <1 RK_PD1 2 &pcfg_pull_default>,
0713 <1 RK_PD2 2 &pcfg_pull_default>,
0714 <1 RK_PD3 2 &pcfg_pull_default>,
0715 <1 RK_PD4 2 &pcfg_pull_default>,
0716 <1 RK_PD5 2 &pcfg_pull_default>,
0717 <1 RK_PD6 2 &pcfg_pull_default>,
0718 <1 RK_PD7 2 &pcfg_pull_default>;
0719 };
0720 };
0721
0722 nfc {
0723 flash_ale: flash-ale {
0724 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>;
0725 };
0726
0727 flash_bus8: flash-bus8 {
0728 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>,
0729 <1 RK_PD1 1 &pcfg_pull_default>,
0730 <1 RK_PD2 1 &pcfg_pull_default>,
0731 <1 RK_PD3 1 &pcfg_pull_default>,
0732 <1 RK_PD4 1 &pcfg_pull_default>,
0733 <1 RK_PD5 1 &pcfg_pull_default>,
0734 <1 RK_PD6 1 &pcfg_pull_default>,
0735 <1 RK_PD7 1 &pcfg_pull_default>;
0736 };
0737
0738 flash_cle: flash-cle {
0739 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>;
0740 };
0741
0742 flash_csn0: flash-csn0 {
0743 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>;
0744 };
0745
0746 flash_rdn: flash-rdn {
0747 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>;
0748 };
0749
0750 flash_rdy: flash-rdy {
0751 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>;
0752 };
0753
0754 flash_wrn: flash-wrn {
0755 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>;
0756 };
0757 };
0758
0759 emac {
0760 emac_xfer: emac-xfer {
0761 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
0762 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */
0763 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */
0764 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */
0765 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */
0766 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */
0767 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */
0768 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */
0769 };
0770
0771 emac_mdio: emac-mdio {
0772 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
0773 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */
0774 };
0775 };
0776
0777 i2c0 {
0778 i2c0_xfer: i2c0-xfer {
0779 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
0780 <0 RK_PA1 1 &pcfg_pull_none>;
0781 };
0782 };
0783
0784 i2c1 {
0785 i2c1_xfer: i2c1-xfer {
0786 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
0787 <0 RK_PA3 1 &pcfg_pull_none>;
0788 };
0789 };
0790
0791 i2c2 {
0792 i2c2_xfer: i2c2-xfer {
0793 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
0794 <2 RK_PC5 1 &pcfg_pull_none>;
0795 };
0796 };
0797
0798 i2s {
0799 i2s_bus: i2s-bus {
0800 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
0801 <1 RK_PA1 1 &pcfg_pull_default>,
0802 <1 RK_PA2 1 &pcfg_pull_default>,
0803 <1 RK_PA3 1 &pcfg_pull_default>,
0804 <1 RK_PA4 1 &pcfg_pull_default>,
0805 <1 RK_PA5 1 &pcfg_pull_default>;
0806 };
0807 };
0808
0809 hdmi {
0810 hdmi_ctl: hdmi-ctl {
0811 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
0812 <1 RK_PB1 1 &pcfg_pull_none>,
0813 <1 RK_PB2 1 &pcfg_pull_none>,
0814 <1 RK_PB3 1 &pcfg_pull_none>;
0815 };
0816 };
0817
0818 uart0 {
0819 uart0_xfer: uart0-xfer {
0820 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
0821 <0 RK_PC1 1 &pcfg_pull_none>;
0822 };
0823
0824 uart0_cts: uart0-cts {
0825 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
0826 };
0827
0828 uart0_rts: uart0-rts {
0829 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
0830 };
0831 };
0832
0833 uart1 {
0834 uart1_xfer: uart1-xfer {
0835 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
0836 <2 RK_PC7 1 &pcfg_pull_none>;
0837 };
0838 /* no rts / cts for uart1 */
0839 };
0840
0841 uart2 {
0842 uart2_xfer: uart2-xfer {
0843 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
0844 <1 RK_PC3 2 &pcfg_pull_none>;
0845 };
0846 /* no rts / cts for uart2 */
0847 };
0848
0849 spi-pins {
0850 spi_txd:spi-txd {
0851 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
0852 };
0853
0854 spi_rxd:spi-rxd {
0855 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
0856 };
0857
0858 spi_clk:spi-clk {
0859 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
0860 };
0861
0862 spi_cs0:spi-cs0 {
0863 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
0864
0865 };
0866
0867 spi_cs1:spi-cs1 {
0868 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
0869
0870 };
0871 };
0872 };
0873 };
