0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
0004 *
0005 * Copyright (C) 2018 Renesas Electronics Europe Limited
0006 *
0007 */
0008
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
0011
0012 / {
0013 compatible = "renesas,r9a06g032";
0014 #address-cells = <1>;
0015 #size-cells = <1>;
0016
0017 cpus {
0018 #address-cells = <1>;
0019 #size-cells = <0>;
0020
0021 cpu@0 {
0022 device_type = "cpu";
0023 compatible = "arm,cortex-a7";
0024 reg = <0>;
0025 clocks = <&sysctrl R9A06G032_CLK_A7MP>;
0026 };
0027
0028 cpu@1 {
0029 device_type = "cpu";
0030 compatible = "arm,cortex-a7";
0031 reg = <1>;
0032 clocks = <&sysctrl R9A06G032_CLK_A7MP>;
0033 enable-method = "renesas,r9a06g032-smp";
0034 cpu-release-addr = <0 0x4000c204>;
0035 };
0036 };
0037
0038 ext_jtag_clk: extjtagclk {
0039 #clock-cells = <0>;
0040 compatible = "fixed-clock";
0041 clock-frequency = <0>;
0042 };
0043
0044 ext_mclk: extmclk {
0045 #clock-cells = <0>;
0046 compatible = "fixed-clock";
0047 clock-frequency = <40000000>;
0048 };
0049
0050 ext_rgmii_ref: extrgmiiref {
0051 #clock-cells = <0>;
0052 compatible = "fixed-clock";
0053 clock-frequency = <0>;
0054 };
0055
0056 ext_rtc_clk: extrtcclk {
0057 #clock-cells = <0>;
0058 compatible = "fixed-clock";
0059 clock-frequency = <0>;
0060 };
0061
0062 soc {
0063 compatible = "simple-bus";
0064 #address-cells = <1>;
0065 #size-cells = <1>;
0066 interrupt-parent = <&gic>;
0067 ranges;
0068
0069 rtc0: rtc@40006000 {
0070 compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
0071 reg = <0x40006000 0x1000>;
0072 interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
0073 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
0074 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
0075 interrupt-names = "alarm", "timer", "pps";
0076 clocks = <&sysctrl R9A06G032_HCLK_RTC>;
0077 clock-names = "hclk";
0078 power-domains = <&sysctrl>;
0079 status = "disabled";
0080 };
0081
0082 wdt0: watchdog@40008000 {
0083 compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
0084 reg = <0x40008000 0x1000>;
0085 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
0086 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
0087 status = "disabled";
0088 };
0089
0090 wdt1: watchdog@40009000 {
0091 compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
0092 reg = <0x40009000 0x1000>;
0093 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
0094 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
0095 status = "disabled";
0096 };
0097
0098 sysctrl: system-controller@4000c000 {
0099 compatible = "renesas,r9a06g032-sysctrl";
0100 reg = <0x4000c000 0x1000>;
0101 status = "okay";
0102 #clock-cells = <1>;
0103 #power-domain-cells = <0>;
0104
0105 clocks = <&ext_mclk>, <&ext_rtc_clk>,
0106 <&ext_jtag_clk>, <&ext_rgmii_ref>;
0107 clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
0108 #address-cells = <1>;
0109 #size-cells = <1>;
0110
0111 dmamux: dma-router@a0 {
0112 compatible = "renesas,rzn1-dmamux";
0113 reg = <0xa0 4>;
0114 #dma-cells = <6>;
0115 dma-requests = <32>;
0116 dma-masters = <&dma0 &dma1>;
0117 };
0118 };
0119
0120 pci_usb: pci@40030000 {
0121 compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
0122 device_type = "pci";
0123 clocks = <&sysctrl R9A06G032_HCLK_USBH>,
0124 <&sysctrl R9A06G032_HCLK_USBPM>,
0125 <&sysctrl R9A06G032_CLK_PCI_USB>;
0126 clock-names = "hclkh", "hclkpm", "pciclk";
0127 power-domains = <&sysctrl>;
0128 reg = <0x40030000 0xc00>,
0129 <0x40020000 0x1100>;
0130 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0131 status = "disabled";
0132
0133 bus-range = <0 0>;
0134 #address-cells = <3>;
0135 #size-cells = <2>;
0136 #interrupt-cells = <1>;
0137 ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
0138 /* Should map all possible DDR as inbound ranges, but
0139 * the IP only supports a 256MB, 512MB, or 1GB window.
0140 * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
0141 */
0142 dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
0143 interrupt-map-mask = <0xf800 0 0 0x7>;
0144 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
0145 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
0146 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0147
0148 usb@1,0 {
0149 reg = <0x800 0 0 0 0>;
0150 phys = <&usbphy>;
0151 phy-names = "usb";
0152 };
0153
0154 usb@2,0 {
0155 reg = <0x1000 0 0 0 0>;
0156 phys = <&usbphy>;
0157 phy-names = "usb";
0158 };
0159 };
0160
0161 uart0: serial@40060000 {
0162 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
0163 reg = <0x40060000 0x400>;
0164 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0165 reg-shift = <2>;
0166 reg-io-width = <4>;
0167 clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
0168 clock-names = "baudclk", "apb_pclk";
0169 status = "disabled";
0170 };
0171
0172 uart1: serial@40061000 {
0173 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
0174 reg = <0x40061000 0x400>;
0175 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0176 reg-shift = <2>;
0177 reg-io-width = <4>;
0178 clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
0179 clock-names = "baudclk", "apb_pclk";
0180 status = "disabled";
0181 };
0182
0183 uart2: serial@40062000 {
0184 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
0185 reg = <0x40062000 0x400>;
0186 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0187 reg-shift = <2>;
0188 reg-io-width = <4>;
0189 clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
0190 clock-names = "baudclk", "apb_pclk";
0191 status = "disabled";
0192 };
0193
0194 uart3: serial@50000000 {
0195 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
0196 reg = <0x50000000 0x400>;
0197 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0198 reg-shift = <2>;
0199 reg-io-width = <4>;
0200 clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
0201 clock-names = "baudclk", "apb_pclk";
0202 dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>;
0203 dma-names = "rx", "tx";
0204 status = "disabled";
0205 };
0206
0207 uart4: serial@50001000 {
0208 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
0209 reg = <0x50001000 0x400>;
0210 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0211 reg-shift = <2>;
0212 reg-io-width = <4>;
0213 clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
0214 clock-names = "baudclk", "apb_pclk";
0215 dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>;
0216 dma-names = "rx", "tx";
0217 status = "disabled";
0218 };
0219
0220 uart5: serial@50002000 {
0221 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
0222 reg = <0x50002000 0x400>;
0223 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0224 reg-shift = <2>;
0225 reg-io-width = <4>;
0226 clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
0227 clock-names = "baudclk", "apb_pclk";
0228 dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>;
0229 dma-names = "rx", "tx";
0230 status = "disabled";
0231 };
0232
0233 uart6: serial@50003000 {
0234 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
0235 reg = <0x50003000 0x400>;
0236 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0237 reg-shift = <2>;
0238 reg-io-width = <4>;
0239 clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
0240 clock-names = "baudclk", "apb_pclk";
0241 dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>;
0242 dma-names = "rx", "tx";
0243 status = "disabled";
0244 };
0245
0246 uart7: serial@50004000 {
0247 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
0248 reg = <0x50004000 0x400>;
0249 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0250 reg-shift = <2>;
0251 reg-io-width = <4>;
0252 clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
0253 clock-names = "baudclk", "apb_pclk";
0254 dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>;
0255 dma-names = "rx", "tx";
0256 status = "disabled";
0257 };
0258
0259 pinctrl: pinctrl@40067000 {
0260 compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
0261 reg = <0x40067000 0x1000>, <0x51000000 0x480>;
0262 clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
0263 clock-names = "bus";
0264 status = "okay";
0265 };
0266
0267 nand_controller: nand-controller@40102000 {
0268 compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
0269 reg = <0x40102000 0x2000>;
0270 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0271 clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
0272 clock-names = "hclk", "eclk";
0273 power-domains = <&sysctrl>;
0274 #address-cells = <1>;
0275 #size-cells = <0>;
0276 status = "disabled";
0277 };
0278
0279 dma0: dma-controller@40104000 {
0280 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
0281 reg = <0x40104000 0x1000>;
0282 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0283 clock-names = "hclk";
0284 clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
0285 dma-channels = <8>;
0286 dma-requests = <16>;
0287 dma-masters = <1>;
0288 #dma-cells = <3>;
0289 block_size = <0xfff>;
0290 data-width = <8>;
0291 };
0292
0293 dma1: dma-controller@40105000 {
0294 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
0295 reg = <0x40105000 0x1000>;
0296 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0297 clock-names = "hclk";
0298 clocks = <&sysctrl R9A06G032_HCLK_DMA1>;
0299 dma-channels = <8>;
0300 dma-requests = <16>;
0301 dma-masters = <1>;
0302 #dma-cells = <3>;
0303 block_size = <0xfff>;
0304 data-width = <8>;
0305 };
0306
0307 gmac2: ethernet@44002000 {
0308 compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";
0309 reg = <0x44002000 0x2000>;
0310 interrupt-parent = <&gic>;
0311 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
0312 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
0313 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0314 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
0315 clocks = <&sysctrl R9A06G032_HCLK_GMAC1>;
0316 clock-names = "stmmaceth";
0317 power-domains = <&sysctrl>;
0318 snps,multicast-filter-bins = <256>;
0319 snps,perfect-filter-entries = <128>;
0320 tx-fifo-depth = <2048>;
0321 rx-fifo-depth = <4096>;
0322 status = "disabled";
0323 };
0324
0325 eth_miic: eth-miic@44030000 {
0326 compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic";
0327 #address-cells = <1>;
0328 #size-cells = <0>;
0329 reg = <0x44030000 0x10000>;
0330 clocks = <&sysctrl R9A06G032_CLK_MII_REF>,
0331 <&sysctrl R9A06G032_CLK_RGMII_REF>,
0332 <&sysctrl R9A06G032_CLK_RMII_REF>,
0333 <&sysctrl R9A06G032_HCLK_SWITCH_RG>;
0334 clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
0335 power-domains = <&sysctrl>;
0336 status = "disabled";
0337
0338 mii_conv1: mii-conv@1 {
0339 reg = <1>;
0340 status = "disabled";
0341 };
0342
0343 mii_conv2: mii-conv@2 {
0344 reg = <2>;
0345 status = "disabled";
0346 };
0347
0348 mii_conv3: mii-conv@3 {
0349 reg = <3>;
0350 status = "disabled";
0351 };
0352
0353 mii_conv4: mii-conv@4 {
0354 reg = <4>;
0355 status = "disabled";
0356 };
0357
0358 mii_conv5: mii-conv@5 {
0359 reg = <5>;
0360 status = "disabled";
0361 };
0362 };
0363
0364 switch: switch@44050000 {
0365 compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";
0366 reg = <0x44050000 0x10000>;
0367 clocks = <&sysctrl R9A06G032_HCLK_SWITCH>,
0368 <&sysctrl R9A06G032_CLK_SWITCH>;
0369 clock-names = "hclk", "clk";
0370 power-domains = <&sysctrl>;
0371 status = "disabled";
0372
0373 ethernet-ports {
0374 #address-cells = <1>;
0375 #size-cells = <0>;
0376
0377 switch_port0: port@0 {
0378 reg = <0>;
0379 pcs-handle = <&mii_conv5>;
0380 status = "disabled";
0381 };
0382
0383 switch_port1: port@1 {
0384 reg = <1>;
0385 pcs-handle = <&mii_conv4>;
0386 status = "disabled";
0387 };
0388
0389 switch_port2: port@2 {
0390 reg = <2>;
0391 pcs-handle = <&mii_conv3>;
0392 status = "disabled";
0393 };
0394
0395 switch_port3: port@3 {
0396 reg = <3>;
0397 pcs-handle = <&mii_conv2>;
0398 status = "disabled";
0399 };
0400
0401 switch_port4: port@4 {
0402 reg = <4>;
0403 ethernet = <&gmac2>;
0404 label = "cpu";
0405 phy-mode = "internal";
0406 status = "disabled";
0407 fixed-link {
0408 speed = <1000>;
0409 full-duplex;
0410 };
0411 };
0412 };
0413 };
0414
0415 gic: interrupt-controller@44101000 {
0416 compatible = "arm,gic-400", "arm,cortex-a7-gic";
0417 interrupt-controller;
0418 #interrupt-cells = <3>;
0419 reg = <0x44101000 0x1000>, /* Distributer */
0420 <0x44102000 0x2000>, /* CPU interface */
0421 <0x44104000 0x2000>, /* Virt interface control */
0422 <0x44106000 0x2000>; /* Virt CPU interface */
0423 interrupts =
0424 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
0425 };
0426 };
0427
0428 timer {
0429 compatible = "arm,armv7-timer";
0430 interrupt-parent = <&gic>;
0431 arm,cpu-registers-not-fw-configured;
0432 always-on;
0433 interrupts =
0434 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0435 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0436 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0437 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
0438 };
0439
0440 usbphy: usb-phy {
0441 #phy-cells = <0>;
0442 compatible = "usb-nop-xceiv";
0443 status = "disabled";
0444 };
0445 };
