boot/dts/r9a06g032-rzn1d400-db.dts

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Device Tree Source for the RZN1D-DB Board
0004  *
0005  * Copyright (C) 2018 Renesas Electronics Europe Limited
0006  *
0007  */
0008
0009 /dts-v1/;
0010
0011 #include <dt-bindings/pinctrl/rzn1-pinctrl.h>
0012 #include <dt-bindings/net/pcs-rzn1-miic.h>
0013
0014 #include "r9a06g032.dtsi"
0015
0016 / {
0017         model = "RZN1D-DB Board";
0018         compatible = "renesas,rzn1d400-db", "renesas,r9a06g032";
0019
0020         chosen {
0021                 stdout-path = "serial0:115200n8";
0022         };
0023
0024         aliases {
0025                 serial0 = &uart0;
0026         };
0027 };
0028
0029 &eth_miic {
0030         status = "okay";
0031         renesas,miic-switch-portin = <MIIC_GMAC2_PORT>;
0032 };
0033
0034 &gmac2 {
0035         status = "okay";
0036         phy-mode = "gmii";
0037
0038         fixed-link {
0039                 speed = <1000>;
0040                 full-duplex;
0041         };
0042 };
0043
0044 &mii_conv4 {
0045         renesas,miic-input = <MIIC_SWITCH_PORTB>;
0046         status = "okay";
0047 };
0048
0049 &mii_conv5 {
0050         renesas,miic-input = <MIIC_SWITCH_PORTA>;
0051         status = "okay";
0052 };
0053
0054 &pinctrl{
0055         pins_eth3: pins_eth3 {
0056                 pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0057                          <RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0058                          <RZN1_PINMUX(38, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0059                          <RZN1_PINMUX(39, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0060                          <RZN1_PINMUX(40, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0061                          <RZN1_PINMUX(41, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0062                          <RZN1_PINMUX(42, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0063                          <RZN1_PINMUX(43, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0064                          <RZN1_PINMUX(44, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0065                          <RZN1_PINMUX(45, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0066                          <RZN1_PINMUX(46, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0067                          <RZN1_PINMUX(47, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
0068                 drive-strength = <6>;
0069                 bias-disable;
0070         };
0071
0072         pins_eth4: pins_eth4 {
0073                 pinmux = <RZN1_PINMUX(48, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0074                          <RZN1_PINMUX(49, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0075                          <RZN1_PINMUX(50, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0076                          <RZN1_PINMUX(51, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0077                          <RZN1_PINMUX(52, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0078                          <RZN1_PINMUX(53, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0079                          <RZN1_PINMUX(54, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0080                          <RZN1_PINMUX(55, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0081                          <RZN1_PINMUX(56, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0082                          <RZN1_PINMUX(57, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0083                          <RZN1_PINMUX(58, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
0084                          <RZN1_PINMUX(59, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
0085                 drive-strength = <6>;
0086                 bias-disable;
0087         };
0088
0089         pins_mdio1: pins_mdio1 {
0090                 pinmux = <RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH)>,
0091                          <RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH)>;
0092         };
0093 };
0094
0095 &rtc0 {
0096         status = "okay";
0097 };
0098
0099 &switch {
0100         status = "okay";
0101         #address-cells = <1>;
0102         #size-cells = <0>;
0103
0104         pinctrl-names = "default";
0105         pinctrl-0 = <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>;
0106
0107         dsa,member = <0 0>;
0108
0109         mdio {
0110                 clock-frequency = <2500000>;
0111
0112                 #address-cells = <1>;
0113                 #size-cells = <0>;
0114
0115                 switch0phy4: ethernet-phy@4 {
0116                         reg = <4>;
0117                         micrel,led-mode = <1>;
0118                 };
0119
0120                 switch0phy5: ethernet-phy@5 {
0121                         reg = <5>;
0122                         micrel,led-mode = <1>;
0123                 };
0124         };
0125 };
0126
0127 &switch_port0 {
0128         label = "lan0";
0129         phy-mode = "mii";
0130         phy-handle = <&switch0phy5>;
0131         status = "okay";
0132 };
0133
0134 &switch_port1 {
0135         label = "lan1";
0136         phy-mode = "mii";
0137         phy-handle = <&switch0phy4>;
0138         status = "okay";
0139 };
0140
0141 &switch_port4 {
0142         status = "okay";
0143 };
0144
0145 &uart0 {
0146         status = "okay";
0147 };
0148
0149 &wdt0 {
0150         timeout-sec = <60>;
0151         status = "okay";
0152 };