0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for the R-Car V2H (R8A77920) SoC
0004 *
0005 * Copyright (C) 2016 Cogent Embedded Inc.
0006 */
0007
0008 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
0009 #include <dt-bindings/interrupt-controller/irq.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/power/r8a7792-sysc.h>
0012
0013 / {
0014 compatible = "renesas,r8a7792";
0015 #address-cells = <2>;
0016 #size-cells = <2>;
0017
0018 aliases {
0019 i2c0 = &i2c0;
0020 i2c1 = &i2c1;
0021 i2c2 = &i2c2;
0022 i2c3 = &i2c3;
0023 i2c4 = &i2c4;
0024 i2c5 = &i2c5;
0025 i2c6 = &iic3;
0026 spi0 = &qspi;
0027 spi1 = &msiof0;
0028 spi2 = &msiof1;
0029 vin0 = &vin0;
0030 vin1 = &vin1;
0031 vin2 = &vin2;
0032 vin3 = &vin3;
0033 vin4 = &vin4;
0034 vin5 = &vin5;
0035 };
0036
0037 /* External CAN clock */
0038 can_clk: can {
0039 compatible = "fixed-clock";
0040 #clock-cells = <0>;
0041 /* This value must be overridden by the board. */
0042 clock-frequency = <0>;
0043 };
0044
0045 cpus {
0046 #address-cells = <1>;
0047 #size-cells = <0>;
0048
0049 cpu0: cpu@0 {
0050 device_type = "cpu";
0051 compatible = "arm,cortex-a15";
0052 reg = <0>;
0053 clock-frequency = <1000000000>;
0054 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
0055 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
0056 enable-method = "renesas,apmu";
0057 next-level-cache = <&L2_CA15>;
0058 };
0059
0060 cpu1: cpu@1 {
0061 device_type = "cpu";
0062 compatible = "arm,cortex-a15";
0063 reg = <1>;
0064 clock-frequency = <1000000000>;
0065 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
0066 power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
0067 enable-method = "renesas,apmu";
0068 next-level-cache = <&L2_CA15>;
0069 };
0070
0071 L2_CA15: cache-controller-0 {
0072 compatible = "cache";
0073 cache-unified;
0074 cache-level = <2>;
0075 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
0076 };
0077 };
0078
0079 /* External root clock */
0080 extal_clk: extal {
0081 compatible = "fixed-clock";
0082 #clock-cells = <0>;
0083 /* This value must be overridden by the board. */
0084 clock-frequency = <0>;
0085 };
0086
0087 pmu {
0088 compatible = "arm,cortex-a15-pmu";
0089 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
0090 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0091 interrupt-affinity = <&cpu0>, <&cpu1>;
0092 };
0093
0094 /* External SCIF clock */
0095 scif_clk: scif {
0096 compatible = "fixed-clock";
0097 #clock-cells = <0>;
0098 /* This value must be overridden by the board. */
0099 clock-frequency = <0>;
0100 };
0101
0102 soc {
0103 compatible = "simple-bus";
0104 interrupt-parent = <&gic>;
0105
0106 #address-cells = <2>;
0107 #size-cells = <2>;
0108 ranges;
0109
0110 rwdt: watchdog@e6020000 {
0111 compatible = "renesas,r8a7792-wdt",
0112 "renesas,rcar-gen2-wdt";
0113 reg = <0 0xe6020000 0 0x0c>;
0114 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
0115 clocks = <&cpg CPG_MOD 402>;
0116 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0117 resets = <&cpg 402>;
0118 status = "disabled";
0119 };
0120
0121 gpio0: gpio@e6050000 {
0122 compatible = "renesas,gpio-r8a7792",
0123 "renesas,rcar-gen2-gpio";
0124 reg = <0 0xe6050000 0 0x50>;
0125 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0126 #gpio-cells = <2>;
0127 gpio-controller;
0128 gpio-ranges = <&pfc 0 0 29>;
0129 #interrupt-cells = <2>;
0130 interrupt-controller;
0131 clocks = <&cpg CPG_MOD 912>;
0132 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0133 resets = <&cpg 912>;
0134 };
0135
0136 gpio1: gpio@e6051000 {
0137 compatible = "renesas,gpio-r8a7792",
0138 "renesas,rcar-gen2-gpio";
0139 reg = <0 0xe6051000 0 0x50>;
0140 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0141 #gpio-cells = <2>;
0142 gpio-controller;
0143 gpio-ranges = <&pfc 0 32 23>;
0144 #interrupt-cells = <2>;
0145 interrupt-controller;
0146 clocks = <&cpg CPG_MOD 911>;
0147 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0148 resets = <&cpg 911>;
0149 };
0150
0151 gpio2: gpio@e6052000 {
0152 compatible = "renesas,gpio-r8a7792",
0153 "renesas,rcar-gen2-gpio";
0154 reg = <0 0xe6052000 0 0x50>;
0155 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0156 #gpio-cells = <2>;
0157 gpio-controller;
0158 gpio-ranges = <&pfc 0 64 32>;
0159 #interrupt-cells = <2>;
0160 interrupt-controller;
0161 clocks = <&cpg CPG_MOD 910>;
0162 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0163 resets = <&cpg 910>;
0164 };
0165
0166 gpio3: gpio@e6053000 {
0167 compatible = "renesas,gpio-r8a7792",
0168 "renesas,rcar-gen2-gpio";
0169 reg = <0 0xe6053000 0 0x50>;
0170 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0171 #gpio-cells = <2>;
0172 gpio-controller;
0173 gpio-ranges = <&pfc 0 96 28>;
0174 #interrupt-cells = <2>;
0175 interrupt-controller;
0176 clocks = <&cpg CPG_MOD 909>;
0177 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0178 resets = <&cpg 909>;
0179 };
0180
0181 gpio4: gpio@e6054000 {
0182 compatible = "renesas,gpio-r8a7792",
0183 "renesas,rcar-gen2-gpio";
0184 reg = <0 0xe6054000 0 0x50>;
0185 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0186 #gpio-cells = <2>;
0187 gpio-controller;
0188 gpio-ranges = <&pfc 0 128 17>;
0189 #interrupt-cells = <2>;
0190 interrupt-controller;
0191 clocks = <&cpg CPG_MOD 908>;
0192 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0193 resets = <&cpg 908>;
0194 };
0195
0196 gpio5: gpio@e6055000 {
0197 compatible = "renesas,gpio-r8a7792",
0198 "renesas,rcar-gen2-gpio";
0199 reg = <0 0xe6055000 0 0x50>;
0200 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0201 #gpio-cells = <2>;
0202 gpio-controller;
0203 gpio-ranges = <&pfc 0 160 17>;
0204 #interrupt-cells = <2>;
0205 interrupt-controller;
0206 clocks = <&cpg CPG_MOD 907>;
0207 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0208 resets = <&cpg 907>;
0209 };
0210
0211 gpio6: gpio@e6055100 {
0212 compatible = "renesas,gpio-r8a7792",
0213 "renesas,rcar-gen2-gpio";
0214 reg = <0 0xe6055100 0 0x50>;
0215 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0216 #gpio-cells = <2>;
0217 gpio-controller;
0218 gpio-ranges = <&pfc 0 192 17>;
0219 #interrupt-cells = <2>;
0220 interrupt-controller;
0221 clocks = <&cpg CPG_MOD 905>;
0222 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0223 resets = <&cpg 905>;
0224 };
0225
0226 gpio7: gpio@e6055200 {
0227 compatible = "renesas,gpio-r8a7792",
0228 "renesas,rcar-gen2-gpio";
0229 reg = <0 0xe6055200 0 0x50>;
0230 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0231 #gpio-cells = <2>;
0232 gpio-controller;
0233 gpio-ranges = <&pfc 0 224 17>;
0234 #interrupt-cells = <2>;
0235 interrupt-controller;
0236 clocks = <&cpg CPG_MOD 904>;
0237 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0238 resets = <&cpg 904>;
0239 };
0240
0241 gpio8: gpio@e6055300 {
0242 compatible = "renesas,gpio-r8a7792",
0243 "renesas,rcar-gen2-gpio";
0244 reg = <0 0xe6055300 0 0x50>;
0245 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0246 #gpio-cells = <2>;
0247 gpio-controller;
0248 gpio-ranges = <&pfc 0 256 17>;
0249 #interrupt-cells = <2>;
0250 interrupt-controller;
0251 clocks = <&cpg CPG_MOD 921>;
0252 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0253 resets = <&cpg 921>;
0254 };
0255
0256 gpio9: gpio@e6055400 {
0257 compatible = "renesas,gpio-r8a7792",
0258 "renesas,rcar-gen2-gpio";
0259 reg = <0 0xe6055400 0 0x50>;
0260 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0261 #gpio-cells = <2>;
0262 gpio-controller;
0263 gpio-ranges = <&pfc 0 288 17>;
0264 #interrupt-cells = <2>;
0265 interrupt-controller;
0266 clocks = <&cpg CPG_MOD 919>;
0267 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0268 resets = <&cpg 919>;
0269 };
0270
0271 gpio10: gpio@e6055500 {
0272 compatible = "renesas,gpio-r8a7792",
0273 "renesas,rcar-gen2-gpio";
0274 reg = <0 0xe6055500 0 0x50>;
0275 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0276 #gpio-cells = <2>;
0277 gpio-controller;
0278 gpio-ranges = <&pfc 0 320 32>;
0279 #interrupt-cells = <2>;
0280 interrupt-controller;
0281 clocks = <&cpg CPG_MOD 914>;
0282 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0283 resets = <&cpg 914>;
0284 };
0285
0286 gpio11: gpio@e6055600 {
0287 compatible = "renesas,gpio-r8a7792",
0288 "renesas,rcar-gen2-gpio";
0289 reg = <0 0xe6055600 0 0x50>;
0290 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0291 #gpio-cells = <2>;
0292 gpio-controller;
0293 gpio-ranges = <&pfc 0 352 30>;
0294 #interrupt-cells = <2>;
0295 interrupt-controller;
0296 clocks = <&cpg CPG_MOD 913>;
0297 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0298 resets = <&cpg 913>;
0299 };
0300
0301 pfc: pinctrl@e6060000 {
0302 compatible = "renesas,pfc-r8a7792";
0303 reg = <0 0xe6060000 0 0x144>;
0304 };
0305
0306 cpg: clock-controller@e6150000 {
0307 compatible = "renesas,r8a7792-cpg-mssr";
0308 reg = <0 0xe6150000 0 0x1000>;
0309 clocks = <&extal_clk>;
0310 clock-names = "extal";
0311 #clock-cells = <2>;
0312 #power-domain-cells = <0>;
0313 #reset-cells = <1>;
0314 };
0315
0316 apmu@e6152000 {
0317 compatible = "renesas,r8a7792-apmu", "renesas,apmu";
0318 reg = <0 0xe6152000 0 0x188>;
0319 cpus = <&cpu0>, <&cpu1>;
0320 };
0321
0322 rst: reset-controller@e6160000 {
0323 compatible = "renesas,r8a7792-rst";
0324 reg = <0 0xe6160000 0 0x0100>;
0325 };
0326
0327 sysc: system-controller@e6180000 {
0328 compatible = "renesas,r8a7792-sysc";
0329 reg = <0 0xe6180000 0 0x0200>;
0330 #power-domain-cells = <1>;
0331 };
0332
0333 irqc: interrupt-controller@e61c0000 {
0334 compatible = "renesas,irqc-r8a7792", "renesas,irqc";
0335 #interrupt-cells = <2>;
0336 interrupt-controller;
0337 reg = <0 0xe61c0000 0 0x200>;
0338 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0339 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0340 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0341 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0342 clocks = <&cpg CPG_MOD 407>;
0343 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0344 resets = <&cpg 407>;
0345 };
0346
0347 icram0: sram@e63a0000 {
0348 compatible = "mmio-sram";
0349 reg = <0 0xe63a0000 0 0x12000>;
0350 #address-cells = <1>;
0351 #size-cells = <1>;
0352 ranges = <0 0 0xe63a0000 0x12000>;
0353 };
0354
0355 icram1: sram@e63c0000 {
0356 compatible = "mmio-sram";
0357 reg = <0 0xe63c0000 0 0x1000>;
0358 #address-cells = <1>;
0359 #size-cells = <1>;
0360 ranges = <0 0 0xe63c0000 0x1000>;
0361
0362 smp-sram@0 {
0363 compatible = "renesas,smp-sram";
0364 reg = <0 0x100>;
0365 };
0366 };
0367
0368 /* I2C doesn't need pinmux */
0369 i2c0: i2c@e6508000 {
0370 compatible = "renesas,i2c-r8a7792",
0371 "renesas,rcar-gen2-i2c";
0372 reg = <0 0xe6508000 0 0x40>;
0373 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
0374 clocks = <&cpg CPG_MOD 931>;
0375 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0376 resets = <&cpg 931>;
0377 i2c-scl-internal-delay-ns = <6>;
0378 #address-cells = <1>;
0379 #size-cells = <0>;
0380 status = "disabled";
0381 };
0382
0383 i2c1: i2c@e6518000 {
0384 compatible = "renesas,i2c-r8a7792",
0385 "renesas,rcar-gen2-i2c";
0386 reg = <0 0xe6518000 0 0x40>;
0387 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
0388 clocks = <&cpg CPG_MOD 930>;
0389 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0390 resets = <&cpg 930>;
0391 i2c-scl-internal-delay-ns = <6>;
0392 #address-cells = <1>;
0393 #size-cells = <0>;
0394 status = "disabled";
0395 };
0396
0397 i2c2: i2c@e6530000 {
0398 compatible = "renesas,i2c-r8a7792",
0399 "renesas,rcar-gen2-i2c";
0400 reg = <0 0xe6530000 0 0x40>;
0401 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
0402 clocks = <&cpg CPG_MOD 929>;
0403 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0404 resets = <&cpg 929>;
0405 i2c-scl-internal-delay-ns = <6>;
0406 #address-cells = <1>;
0407 #size-cells = <0>;
0408 status = "disabled";
0409 };
0410
0411 i2c3: i2c@e6540000 {
0412 compatible = "renesas,i2c-r8a7792",
0413 "renesas,rcar-gen2-i2c";
0414 reg = <0 0xe6540000 0 0x40>;
0415 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
0416 clocks = <&cpg CPG_MOD 928>;
0417 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0418 resets = <&cpg 928>;
0419 i2c-scl-internal-delay-ns = <6>;
0420 #address-cells = <1>;
0421 #size-cells = <0>;
0422 status = "disabled";
0423 };
0424
0425 i2c4: i2c@e6520000 {
0426 compatible = "renesas,i2c-r8a7792",
0427 "renesas,rcar-gen2-i2c";
0428 reg = <0 0xe6520000 0 0x40>;
0429 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0430 clocks = <&cpg CPG_MOD 927>;
0431 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0432 resets = <&cpg 927>;
0433 i2c-scl-internal-delay-ns = <6>;
0434 #address-cells = <1>;
0435 #size-cells = <0>;
0436 status = "disabled";
0437 };
0438
0439 i2c5: i2c@e6528000 {
0440 compatible = "renesas,i2c-r8a7792",
0441 "renesas,rcar-gen2-i2c";
0442 reg = <0 0xe6528000 0 0x40>;
0443 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0444 clocks = <&cpg CPG_MOD 925>;
0445 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0446 resets = <&cpg 925>;
0447 i2c-scl-internal-delay-ns = <110>;
0448 #address-cells = <1>;
0449 #size-cells = <0>;
0450 status = "disabled";
0451 };
0452
0453 iic3: i2c@e60b0000 {
0454 #address-cells = <1>;
0455 #size-cells = <0>;
0456 compatible = "renesas,iic-r8a7792",
0457 "renesas,rcar-gen2-iic",
0458 "renesas,rmobile-iic";
0459 reg = <0 0xe60b0000 0 0x425>;
0460 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
0461 clocks = <&cpg CPG_MOD 926>;
0462 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
0463 <&dmac1 0x77>, <&dmac1 0x78>;
0464 dma-names = "tx", "rx", "tx", "rx";
0465 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0466 resets = <&cpg 926>;
0467 status = "disabled";
0468 };
0469
0470 dmac0: dma-controller@e6700000 {
0471 compatible = "renesas,dmac-r8a7792",
0472 "renesas,rcar-dmac";
0473 reg = <0 0xe6700000 0 0x20000>;
0474 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
0475 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
0476 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
0477 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
0478 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
0479 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
0480 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
0481 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
0482 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
0483 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
0484 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
0485 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
0486 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
0487 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
0488 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
0489 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
0490 interrupt-names = "error",
0491 "ch0", "ch1", "ch2", "ch3",
0492 "ch4", "ch5", "ch6", "ch7",
0493 "ch8", "ch9", "ch10", "ch11",
0494 "ch12", "ch13", "ch14";
0495 clocks = <&cpg CPG_MOD 219>;
0496 clock-names = "fck";
0497 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0498 resets = <&cpg 219>;
0499 #dma-cells = <1>;
0500 dma-channels = <15>;
0501 };
0502
0503 dmac1: dma-controller@e6720000 {
0504 compatible = "renesas,dmac-r8a7792",
0505 "renesas,rcar-dmac";
0506 reg = <0 0xe6720000 0 0x20000>;
0507 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
0508 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
0509 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
0510 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
0511 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
0512 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
0513 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
0514 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
0515 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
0516 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
0517 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
0518 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
0519 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
0520 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
0521 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
0522 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
0523 interrupt-names = "error",
0524 "ch0", "ch1", "ch2", "ch3",
0525 "ch4", "ch5", "ch6", "ch7",
0526 "ch8", "ch9", "ch10", "ch11",
0527 "ch12", "ch13", "ch14";
0528 clocks = <&cpg CPG_MOD 218>;
0529 clock-names = "fck";
0530 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0531 resets = <&cpg 218>;
0532 #dma-cells = <1>;
0533 dma-channels = <15>;
0534 };
0535
0536 avb: ethernet@e6800000 {
0537 compatible = "renesas,etheravb-r8a7792",
0538 "renesas,etheravb-rcar-gen2";
0539 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
0540 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
0541 clocks = <&cpg CPG_MOD 812>;
0542 clock-names = "fck";
0543 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0544 resets = <&cpg 812>;
0545 #address-cells = <1>;
0546 #size-cells = <0>;
0547 status = "disabled";
0548 };
0549
0550 qspi: spi@e6b10000 {
0551 compatible = "renesas,qspi-r8a7792", "renesas,qspi";
0552 reg = <0 0xe6b10000 0 0x2c>;
0553 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
0554 clocks = <&cpg CPG_MOD 917>;
0555 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
0556 <&dmac1 0x17>, <&dmac1 0x18>;
0557 dma-names = "tx", "rx", "tx", "rx";
0558 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0559 resets = <&cpg 917>;
0560 num-cs = <1>;
0561 #address-cells = <1>;
0562 #size-cells = <0>;
0563 status = "disabled";
0564 };
0565
0566 scif0: serial@e6e60000 {
0567 compatible = "renesas,scif-r8a7792",
0568 "renesas,rcar-gen2-scif", "renesas,scif";
0569 reg = <0 0xe6e60000 0 64>;
0570 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
0571 clocks = <&cpg CPG_MOD 721>,
0572 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
0573 clock-names = "fck", "brg_int", "scif_clk";
0574 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
0575 <&dmac1 0x29>, <&dmac1 0x2a>;
0576 dma-names = "tx", "rx", "tx", "rx";
0577 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0578 resets = <&cpg 721>;
0579 status = "disabled";
0580 };
0581
0582 scif1: serial@e6e68000 {
0583 compatible = "renesas,scif-r8a7792",
0584 "renesas,rcar-gen2-scif", "renesas,scif";
0585 reg = <0 0xe6e68000 0 64>;
0586 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
0587 clocks = <&cpg CPG_MOD 720>,
0588 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
0589 clock-names = "fck", "brg_int", "scif_clk";
0590 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
0591 <&dmac1 0x2d>, <&dmac1 0x2e>;
0592 dma-names = "tx", "rx", "tx", "rx";
0593 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0594 resets = <&cpg 720>;
0595 status = "disabled";
0596 };
0597
0598 scif2: serial@e6e58000 {
0599 compatible = "renesas,scif-r8a7792",
0600 "renesas,rcar-gen2-scif", "renesas,scif";
0601 reg = <0 0xe6e58000 0 64>;
0602 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0603 clocks = <&cpg CPG_MOD 719>,
0604 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
0605 clock-names = "fck", "brg_int", "scif_clk";
0606 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
0607 <&dmac1 0x2b>, <&dmac1 0x2c>;
0608 dma-names = "tx", "rx", "tx", "rx";
0609 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0610 resets = <&cpg 719>;
0611 status = "disabled";
0612 };
0613
0614 scif3: serial@e6ea8000 {
0615 compatible = "renesas,scif-r8a7792",
0616 "renesas,rcar-gen2-scif", "renesas,scif";
0617 reg = <0 0xe6ea8000 0 64>;
0618 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0619 clocks = <&cpg CPG_MOD 718>,
0620 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
0621 clock-names = "fck", "brg_int", "scif_clk";
0622 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
0623 <&dmac1 0x2f>, <&dmac1 0x30>;
0624 dma-names = "tx", "rx", "tx", "rx";
0625 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0626 resets = <&cpg 718>;
0627 status = "disabled";
0628 };
0629
0630 hscif0: serial@e62c0000 {
0631 compatible = "renesas,hscif-r8a7792",
0632 "renesas,rcar-gen2-hscif", "renesas,hscif";
0633 reg = <0 0xe62c0000 0 96>;
0634 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
0635 clocks = <&cpg CPG_MOD 717>,
0636 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
0637 clock-names = "fck", "brg_int", "scif_clk";
0638 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
0639 <&dmac1 0x39>, <&dmac1 0x3a>;
0640 dma-names = "tx", "rx", "tx", "rx";
0641 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0642 resets = <&cpg 717>;
0643 status = "disabled";
0644 };
0645
0646 hscif1: serial@e62c8000 {
0647 compatible = "renesas,hscif-r8a7792",
0648 "renesas,rcar-gen2-hscif", "renesas,hscif";
0649 reg = <0 0xe62c8000 0 96>;
0650 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
0651 clocks = <&cpg CPG_MOD 716>,
0652 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
0653 clock-names = "fck", "brg_int", "scif_clk";
0654 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
0655 <&dmac1 0x4d>, <&dmac1 0x4e>;
0656 dma-names = "tx", "rx", "tx", "rx";
0657 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0658 resets = <&cpg 716>;
0659 status = "disabled";
0660 };
0661
0662 msiof0: spi@e6e20000 {
0663 compatible = "renesas,msiof-r8a7792",
0664 "renesas,rcar-gen2-msiof";
0665 reg = <0 0xe6e20000 0 0x0064>;
0666 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
0667 clocks = <&cpg CPG_MOD 000>;
0668 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
0669 <&dmac1 0x51>, <&dmac1 0x52>;
0670 dma-names = "tx", "rx", "tx", "rx";
0671 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0672 resets = <&cpg 000>;
0673 #address-cells = <1>;
0674 #size-cells = <0>;
0675 status = "disabled";
0676 };
0677
0678 msiof1: spi@e6e10000 {
0679 compatible = "renesas,msiof-r8a7792",
0680 "renesas,rcar-gen2-msiof";
0681 reg = <0 0xe6e10000 0 0x0064>;
0682 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
0683 clocks = <&cpg CPG_MOD 208>;
0684 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
0685 <&dmac1 0x55>, <&dmac1 0x56>;
0686 dma-names = "tx", "rx", "tx", "rx";
0687 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0688 resets = <&cpg 208>;
0689 #address-cells = <1>;
0690 #size-cells = <0>;
0691 status = "disabled";
0692 };
0693
0694 can0: can@e6e80000 {
0695 compatible = "renesas,can-r8a7792",
0696 "renesas,rcar-gen2-can";
0697 reg = <0 0xe6e80000 0 0x1000>;
0698 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
0699 clocks = <&cpg CPG_MOD 916>,
0700 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
0701 clock-names = "clkp1", "clkp2", "can_clk";
0702 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0703 resets = <&cpg 916>;
0704 status = "disabled";
0705 };
0706
0707 can1: can@e6e88000 {
0708 compatible = "renesas,can-r8a7792",
0709 "renesas,rcar-gen2-can";
0710 reg = <0 0xe6e88000 0 0x1000>;
0711 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
0712 clocks = <&cpg CPG_MOD 915>,
0713 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
0714 clock-names = "clkp1", "clkp2", "can_clk";
0715 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0716 resets = <&cpg 915>;
0717 status = "disabled";
0718 };
0719
0720 vin0: video@e6ef0000 {
0721 compatible = "renesas,vin-r8a7792",
0722 "renesas,rcar-gen2-vin";
0723 reg = <0 0xe6ef0000 0 0x1000>;
0724 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
0725 clocks = <&cpg CPG_MOD 811>;
0726 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0727 resets = <&cpg 811>;
0728 status = "disabled";
0729 };
0730
0731 vin1: video@e6ef1000 {
0732 compatible = "renesas,vin-r8a7792",
0733 "renesas,rcar-gen2-vin";
0734 reg = <0 0xe6ef1000 0 0x1000>;
0735 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
0736 clocks = <&cpg CPG_MOD 810>;
0737 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0738 resets = <&cpg 810>;
0739 status = "disabled";
0740 };
0741
0742 vin2: video@e6ef2000 {
0743 compatible = "renesas,vin-r8a7792",
0744 "renesas,rcar-gen2-vin";
0745 reg = <0 0xe6ef2000 0 0x1000>;
0746 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
0747 clocks = <&cpg CPG_MOD 809>;
0748 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0749 resets = <&cpg 809>;
0750 status = "disabled";
0751 };
0752
0753 vin3: video@e6ef3000 {
0754 compatible = "renesas,vin-r8a7792",
0755 "renesas,rcar-gen2-vin";
0756 reg = <0 0xe6ef3000 0 0x1000>;
0757 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
0758 clocks = <&cpg CPG_MOD 808>;
0759 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0760 resets = <&cpg 808>;
0761 status = "disabled";
0762 };
0763
0764 vin4: video@e6ef4000 {
0765 compatible = "renesas,vin-r8a7792",
0766 "renesas,rcar-gen2-vin";
0767 reg = <0 0xe6ef4000 0 0x1000>;
0768 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
0769 clocks = <&cpg CPG_MOD 805>;
0770 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0771 resets = <&cpg 805>;
0772 status = "disabled";
0773 };
0774
0775 vin5: video@e6ef5000 {
0776 compatible = "renesas,vin-r8a7792",
0777 "renesas,rcar-gen2-vin";
0778 reg = <0 0xe6ef5000 0 0x1000>;
0779 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
0780 clocks = <&cpg CPG_MOD 804>;
0781 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0782 resets = <&cpg 804>;
0783 status = "disabled";
0784 };
0785
0786 sdhi0: mmc@ee100000 {
0787 compatible = "renesas,sdhi-r8a7792",
0788 "renesas,rcar-gen2-sdhi";
0789 reg = <0 0xee100000 0 0x328>;
0790 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
0791 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
0792 <&dmac1 0xcd>, <&dmac1 0xce>;
0793 dma-names = "tx", "rx", "tx", "rx";
0794 clocks = <&cpg CPG_MOD 314>;
0795 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0796 resets = <&cpg 314>;
0797 status = "disabled";
0798 };
0799
0800 gic: interrupt-controller@f1001000 {
0801 compatible = "arm,gic-400";
0802 #interrupt-cells = <3>;
0803 interrupt-controller;
0804 reg = <0 0xf1001000 0 0x1000>,
0805 <0 0xf1002000 0 0x2000>,
0806 <0 0xf1004000 0 0x2000>,
0807 <0 0xf1006000 0 0x2000>;
0808 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
0809 IRQ_TYPE_LEVEL_HIGH)>;
0810 clocks = <&cpg CPG_MOD 408>;
0811 clock-names = "clk";
0812 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0813 resets = <&cpg 408>;
0814 };
0815
0816 vsp@fe928000 {
0817 compatible = "renesas,vsp1";
0818 reg = <0 0xfe928000 0 0x8000>;
0819 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
0820 clocks = <&cpg CPG_MOD 131>;
0821 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0822 resets = <&cpg 131>;
0823 };
0824
0825 vsp@fe930000 {
0826 compatible = "renesas,vsp1";
0827 reg = <0 0xfe930000 0 0x8000>;
0828 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
0829 clocks = <&cpg CPG_MOD 128>;
0830 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0831 resets = <&cpg 128>;
0832 };
0833
0834 vsp@fe938000 {
0835 compatible = "renesas,vsp1";
0836 reg = <0 0xfe938000 0 0x8000>;
0837 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
0838 clocks = <&cpg CPG_MOD 127>;
0839 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0840 resets = <&cpg 127>;
0841 };
0842
0843 jpu: jpeg-codec@fe980000 {
0844 compatible = "renesas,jpu-r8a7792",
0845 "renesas,rcar-gen2-jpu";
0846 reg = <0 0xfe980000 0 0x10300>;
0847 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
0848 clocks = <&cpg CPG_MOD 106>;
0849 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0850 resets = <&cpg 106>;
0851 };
0852
0853 du: display@feb00000 {
0854 compatible = "renesas,du-r8a7792";
0855 reg = <0 0xfeb00000 0 0x40000>;
0856 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
0857 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
0858 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
0859 clock-names = "du.0", "du.1";
0860 resets = <&cpg 724>;
0861 reset-names = "du.0";
0862 status = "disabled";
0863
0864 ports {
0865 #address-cells = <1>;
0866 #size-cells = <0>;
0867
0868 port@0 {
0869 reg = <0>;
0870 du_out_rgb0: endpoint {
0871 };
0872 };
0873 port@1 {
0874 reg = <1>;
0875 du_out_rgb1: endpoint {
0876 };
0877 };
0878 };
0879 };
0880
0881 prr: chipid@ff000044 {
0882 compatible = "renesas,prr";
0883 reg = <0 0xff000044 0 4>;
0884 };
0885
0886 cmt0: timer@ffca0000 {
0887 compatible = "renesas,r8a7792-cmt0",
0888 "renesas,rcar-gen2-cmt0";
0889 reg = <0 0xffca0000 0 0x1004>;
0890 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
0891 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0892 clocks = <&cpg CPG_MOD 124>;
0893 clock-names = "fck";
0894 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0895 resets = <&cpg 124>;
0896
0897 status = "disabled";
0898 };
0899
0900 cmt1: timer@e6130000 {
0901 compatible = "renesas,r8a7792-cmt1",
0902 "renesas,rcar-gen2-cmt1";
0903 reg = <0 0xe6130000 0 0x1004>;
0904 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0905 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
0906 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
0907 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
0908 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
0909 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
0910 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
0911 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
0912 clocks = <&cpg CPG_MOD 329>;
0913 clock-names = "fck";
0914 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
0915 resets = <&cpg 329>;
0916
0917 status = "disabled";
0918 };
0919 };
0920
0921 timer {
0922 compatible = "arm,armv7-timer";
0923 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0924 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0925 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0926 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
0927 };
0928 };
