0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for the R-Car H1 (R8A77790) SoC
0004 *
0005 * Copyright (C) 2013 Renesas Solutions Corp.
0006 * Copyright (C) 2013 Simon Horman
0007 */
0008
0009 #include <dt-bindings/clock/r8a7779-clock.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/interrupt-controller/irq.h>
0012 #include <dt-bindings/power/r8a7779-sysc.h>
0013
0014 / {
0015 compatible = "renesas,r8a7779";
0016 interrupt-parent = <&gic>;
0017 #address-cells = <1>;
0018 #size-cells = <1>;
0019
0020 cpus {
0021 #address-cells = <1>;
0022 #size-cells = <0>;
0023
0024 cpu@0 {
0025 device_type = "cpu";
0026 compatible = "arm,cortex-a9";
0027 reg = <0>;
0028 clock-frequency = <1000000000>;
0029 clocks = <&cpg_clocks R8A7779_CLK_Z>;
0030 };
0031 cpu@1 {
0032 device_type = "cpu";
0033 compatible = "arm,cortex-a9";
0034 reg = <1>;
0035 clock-frequency = <1000000000>;
0036 clocks = <&cpg_clocks R8A7779_CLK_Z>;
0037 power-domains = <&sysc R8A7779_PD_ARM1>;
0038 };
0039 cpu@2 {
0040 device_type = "cpu";
0041 compatible = "arm,cortex-a9";
0042 reg = <2>;
0043 clock-frequency = <1000000000>;
0044 clocks = <&cpg_clocks R8A7779_CLK_Z>;
0045 power-domains = <&sysc R8A7779_PD_ARM2>;
0046 };
0047 cpu@3 {
0048 device_type = "cpu";
0049 compatible = "arm,cortex-a9";
0050 reg = <3>;
0051 clock-frequency = <1000000000>;
0052 clocks = <&cpg_clocks R8A7779_CLK_Z>;
0053 power-domains = <&sysc R8A7779_PD_ARM3>;
0054 };
0055 };
0056
0057 aliases {
0058 spi0 = &hspi0;
0059 spi1 = &hspi1;
0060 spi2 = &hspi2;
0061 };
0062
0063 gic: interrupt-controller@f0001000 {
0064 compatible = "arm,cortex-a9-gic";
0065 #interrupt-cells = <3>;
0066 interrupt-controller;
0067 reg = <0xf0001000 0x1000>,
0068 <0xf0000100 0x100>;
0069 };
0070
0071 timer@f0000200 {
0072 compatible = "arm,cortex-a9-global-timer";
0073 reg = <0xf0000200 0x100>;
0074 interrupts = <GIC_PPI 11
0075 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
0076 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
0077 };
0078
0079 timer@f0000600 {
0080 compatible = "arm,cortex-a9-twd-timer";
0081 reg = <0xf0000600 0x20>;
0082 interrupts = <GIC_PPI 13
0083 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
0084 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
0085 };
0086
0087 gpio0: gpio@ffc40000 {
0088 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
0089 reg = <0xffc40000 0x2c>;
0090 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
0091 #gpio-cells = <2>;
0092 gpio-controller;
0093 gpio-ranges = <&pfc 0 0 32>;
0094 #interrupt-cells = <2>;
0095 interrupt-controller;
0096 };
0097
0098 gpio1: gpio@ffc41000 {
0099 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
0100 reg = <0xffc41000 0x2c>;
0101 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
0102 #gpio-cells = <2>;
0103 gpio-controller;
0104 gpio-ranges = <&pfc 0 32 32>;
0105 #interrupt-cells = <2>;
0106 interrupt-controller;
0107 };
0108
0109 gpio2: gpio@ffc42000 {
0110 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
0111 reg = <0xffc42000 0x2c>;
0112 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0113 #gpio-cells = <2>;
0114 gpio-controller;
0115 gpio-ranges = <&pfc 0 64 32>;
0116 #interrupt-cells = <2>;
0117 interrupt-controller;
0118 };
0119
0120 gpio3: gpio@ffc43000 {
0121 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
0122 reg = <0xffc43000 0x2c>;
0123 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
0124 #gpio-cells = <2>;
0125 gpio-controller;
0126 gpio-ranges = <&pfc 0 96 32>;
0127 #interrupt-cells = <2>;
0128 interrupt-controller;
0129 };
0130
0131 gpio4: gpio@ffc44000 {
0132 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
0133 reg = <0xffc44000 0x2c>;
0134 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
0135 #gpio-cells = <2>;
0136 gpio-controller;
0137 gpio-ranges = <&pfc 0 128 32>;
0138 #interrupt-cells = <2>;
0139 interrupt-controller;
0140 };
0141
0142 gpio5: gpio@ffc45000 {
0143 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
0144 reg = <0xffc45000 0x2c>;
0145 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
0146 #gpio-cells = <2>;
0147 gpio-controller;
0148 gpio-ranges = <&pfc 0 160 32>;
0149 #interrupt-cells = <2>;
0150 interrupt-controller;
0151 };
0152
0153 gpio6: gpio@ffc46000 {
0154 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
0155 reg = <0xffc46000 0x2c>;
0156 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
0157 #gpio-cells = <2>;
0158 gpio-controller;
0159 gpio-ranges = <&pfc 0 192 9>;
0160 #interrupt-cells = <2>;
0161 interrupt-controller;
0162 };
0163
0164 irqpin0: interrupt-controller@fe78001c {
0165 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
0166 #interrupt-cells = <2>;
0167 status = "disabled";
0168 interrupt-controller;
0169 reg = <0xfe78001c 4>,
0170 <0xfe780010 4>,
0171 <0xfe780024 4>,
0172 <0xfe780044 4>,
0173 <0xfe780064 4>,
0174 <0xfe780000 4>;
0175 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
0176 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
0177 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
0178 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0179 sense-bitfield-width = <2>;
0180 };
0181
0182 i2c0: i2c@ffc70000 {
0183 #address-cells = <1>;
0184 #size-cells = <0>;
0185 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
0186 reg = <0xffc70000 0x1000>;
0187 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0188 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
0189 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0190 status = "disabled";
0191 };
0192
0193 i2c1: i2c@ffc71000 {
0194 #address-cells = <1>;
0195 #size-cells = <0>;
0196 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
0197 reg = <0xffc71000 0x1000>;
0198 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0199 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
0200 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0201 i2c-scl-internal-delay-ns = <5>;
0202 status = "disabled";
0203 };
0204
0205 i2c2: i2c@ffc72000 {
0206 #address-cells = <1>;
0207 #size-cells = <0>;
0208 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
0209 reg = <0xffc72000 0x1000>;
0210 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0211 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
0212 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0213 i2c-scl-internal-delay-ns = <5>;
0214 status = "disabled";
0215 };
0216
0217 i2c3: i2c@ffc73000 {
0218 #address-cells = <1>;
0219 #size-cells = <0>;
0220 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
0221 reg = <0xffc73000 0x1000>;
0222 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0223 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
0224 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0225 i2c-scl-internal-delay-ns = <5>;
0226 status = "disabled";
0227 };
0228
0229 scif0: serial@ffe40000 {
0230 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
0231 "renesas,scif";
0232 reg = <0xffe40000 0x100>;
0233 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0234 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
0235 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
0236 clock-names = "fck", "brg_int", "scif_clk";
0237 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0238 status = "disabled";
0239 };
0240
0241 scif1: serial@ffe41000 {
0242 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
0243 "renesas,scif";
0244 reg = <0xffe41000 0x100>;
0245 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0246 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
0247 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
0248 clock-names = "fck", "brg_int", "scif_clk";
0249 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0250 status = "disabled";
0251 };
0252
0253 scif2: serial@ffe42000 {
0254 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
0255 "renesas,scif";
0256 reg = <0xffe42000 0x100>;
0257 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0258 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
0259 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
0260 clock-names = "fck", "brg_int", "scif_clk";
0261 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0262 status = "disabled";
0263 };
0264
0265 scif3: serial@ffe43000 {
0266 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
0267 "renesas,scif";
0268 reg = <0xffe43000 0x100>;
0269 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0270 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
0271 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
0272 clock-names = "fck", "brg_int", "scif_clk";
0273 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0274 status = "disabled";
0275 };
0276
0277 scif4: serial@ffe44000 {
0278 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
0279 "renesas,scif";
0280 reg = <0xffe44000 0x100>;
0281 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0282 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
0283 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
0284 clock-names = "fck", "brg_int", "scif_clk";
0285 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0286 status = "disabled";
0287 };
0288
0289 scif5: serial@ffe45000 {
0290 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
0291 "renesas,scif";
0292 reg = <0xffe45000 0x100>;
0293 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
0294 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
0295 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
0296 clock-names = "fck", "brg_int", "scif_clk";
0297 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0298 status = "disabled";
0299 };
0300
0301 hscif0: serial@ffe48000 {
0302 compatible = "renesas,hscif-r8a7779",
0303 "renesas,rcar-gen1-hscif", "renesas,hscif";
0304 reg = <0xffe48000 96>;
0305 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0306 clocks = <&mstp0_clks R8A7779_CLK_HSCIF0>,
0307 <&cpg_clocks R8A7779_CLK_S>,
0308 <&scif_clk>;
0309 clock-names = "fck", "brg_int", "scif_clk";
0310 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0311 status = "disabled";
0312 };
0313
0314 hscif1: serial@ffe49000 {
0315 compatible = "renesas,hscif-r8a7779",
0316 "renesas,rcar-gen1-hscif", "renesas,hscif";
0317 reg = <0xffe49000 96>;
0318 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0319 clocks = <&mstp0_clks R8A7779_CLK_HSCIF1>,
0320 <&cpg_clocks R8A7779_CLK_S>,
0321 <&scif_clk>;
0322 clock-names = "fck", "brg_int", "scif_clk";
0323 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0324 status = "disabled";
0325 };
0326
0327 pfc: pinctrl@fffc0000 {
0328 compatible = "renesas,pfc-r8a7779";
0329 reg = <0xfffc0000 0x23c>;
0330 };
0331
0332 thermal@ffc48000 {
0333 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
0334 reg = <0xffc48000 0x38>;
0335 };
0336
0337 tmu0: timer@ffd80000 {
0338 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
0339 reg = <0xffd80000 0x30>;
0340 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
0341 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0342 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0343 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
0344 clock-names = "fck";
0345 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0346
0347 #renesas,channels = <3>;
0348
0349 status = "disabled";
0350 };
0351
0352 tmu1: timer@ffd81000 {
0353 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
0354 reg = <0xffd81000 0x30>;
0355 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
0356 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
0357 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0358 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
0359 clock-names = "fck";
0360 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0361
0362 #renesas,channels = <3>;
0363
0364 status = "disabled";
0365 };
0366
0367 tmu2: timer@ffd82000 {
0368 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
0369 reg = <0xffd82000 0x30>;
0370 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
0371 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
0372 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0373 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
0374 clock-names = "fck";
0375 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0376
0377 #renesas,channels = <3>;
0378
0379 status = "disabled";
0380 };
0381
0382 sata: sata@fc600000 {
0383 compatible = "renesas,sata-r8a7779";
0384 reg = <0xfc600000 0x200000>;
0385 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0386 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
0387 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0388 status = "disabled";
0389 };
0390
0391 sdhi0: mmc@ffe4c000 {
0392 compatible = "renesas,sdhi-r8a7779",
0393 "renesas,rcar-gen1-sdhi";
0394 reg = <0xffe4c000 0x100>;
0395 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
0396 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
0397 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0398 status = "disabled";
0399 };
0400
0401 sdhi1: mmc@ffe4d000 {
0402 compatible = "renesas,sdhi-r8a7779",
0403 "renesas,rcar-gen1-sdhi";
0404 reg = <0xffe4d000 0x100>;
0405 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0406 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
0407 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0408 status = "disabled";
0409 };
0410
0411 sdhi2: mmc@ffe4e000 {
0412 compatible = "renesas,sdhi-r8a7779",
0413 "renesas,rcar-gen1-sdhi";
0414 reg = <0xffe4e000 0x100>;
0415 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0416 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
0417 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0418 status = "disabled";
0419 };
0420
0421 sdhi3: mmc@ffe4f000 {
0422 compatible = "renesas,sdhi-r8a7779",
0423 "renesas,rcar-gen1-sdhi";
0424 reg = <0xffe4f000 0x100>;
0425 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0426 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
0427 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0428 status = "disabled";
0429 };
0430
0431 hspi0: spi@fffc7000 {
0432 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
0433 reg = <0xfffc7000 0x18>;
0434 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0435 #address-cells = <1>;
0436 #size-cells = <0>;
0437 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
0438 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0439 status = "disabled";
0440 };
0441
0442 hspi1: spi@fffc8000 {
0443 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
0444 reg = <0xfffc8000 0x18>;
0445 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0446 #address-cells = <1>;
0447 #size-cells = <0>;
0448 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
0449 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0450 status = "disabled";
0451 };
0452
0453 hspi2: spi@fffc6000 {
0454 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
0455 reg = <0xfffc6000 0x18>;
0456 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0457 #address-cells = <1>;
0458 #size-cells = <0>;
0459 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
0460 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0461 status = "disabled";
0462 };
0463
0464 du: display@fff80000 {
0465 compatible = "renesas,du-r8a7779";
0466 reg = <0xfff80000 0x40000>;
0467 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0468 clocks = <&mstp1_clks R8A7779_CLK_DU>;
0469 clock-names = "du.0";
0470 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
0471 status = "disabled";
0472
0473 ports {
0474 #address-cells = <1>;
0475 #size-cells = <0>;
0476
0477 port@0 {
0478 reg = <0>;
0479 du_out_rgb0: endpoint {
0480 };
0481 };
0482 port@1 {
0483 reg = <1>;
0484 du_out_rgb1: endpoint {
0485 };
0486 };
0487 };
0488 };
0489
0490 clocks {
0491 #address-cells = <1>;
0492 #size-cells = <1>;
0493 ranges;
0494
0495 /* External root clock */
0496 extal_clk: extal {
0497 compatible = "fixed-clock";
0498 #clock-cells = <0>;
0499 /* This value must be overriden by the board. */
0500 clock-frequency = <0>;
0501 };
0502
0503 /* External SCIF clock */
0504 scif_clk: scif {
0505 compatible = "fixed-clock";
0506 #clock-cells = <0>;
0507 /* This value must be overridden by the board. */
0508 clock-frequency = <0>;
0509 };
0510
0511 /* Special CPG clocks */
0512 cpg_clocks: clocks@ffc80000 {
0513 compatible = "renesas,r8a7779-cpg-clocks";
0514 reg = <0xffc80000 0x30>;
0515 clocks = <&extal_clk>;
0516 #clock-cells = <1>;
0517 clock-output-names = "plla", "z", "zs", "s",
0518 "s1", "p", "b", "out";
0519 #power-domain-cells = <0>;
0520 };
0521
0522 /* Fixed factor clocks */
0523 i_clk: i {
0524 compatible = "fixed-factor-clock";
0525 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
0526 #clock-cells = <0>;
0527 clock-div = <2>;
0528 clock-mult = <1>;
0529 };
0530 s3_clk: s3 {
0531 compatible = "fixed-factor-clock";
0532 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
0533 #clock-cells = <0>;
0534 clock-div = <8>;
0535 clock-mult = <1>;
0536 };
0537 s4_clk: s4 {
0538 compatible = "fixed-factor-clock";
0539 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
0540 #clock-cells = <0>;
0541 clock-div = <16>;
0542 clock-mult = <1>;
0543 };
0544 g_clk: g {
0545 compatible = "fixed-factor-clock";
0546 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
0547 #clock-cells = <0>;
0548 clock-div = <24>;
0549 clock-mult = <1>;
0550 };
0551
0552 /* Gate clocks */
0553 mstp0_clks: clocks@ffc80030 {
0554 compatible = "renesas,r8a7779-mstp-clocks",
0555 "renesas,cpg-mstp-clocks";
0556 reg = <0xffc80030 4>;
0557 clocks = <&cpg_clocks R8A7779_CLK_S>,
0558 <&cpg_clocks R8A7779_CLK_P>,
0559 <&cpg_clocks R8A7779_CLK_P>,
0560 <&cpg_clocks R8A7779_CLK_P>,
0561 <&cpg_clocks R8A7779_CLK_S>,
0562 <&cpg_clocks R8A7779_CLK_S>,
0563 <&cpg_clocks R8A7779_CLK_P>,
0564 <&cpg_clocks R8A7779_CLK_P>,
0565 <&cpg_clocks R8A7779_CLK_P>,
0566 <&cpg_clocks R8A7779_CLK_P>,
0567 <&cpg_clocks R8A7779_CLK_P>,
0568 <&cpg_clocks R8A7779_CLK_P>,
0569 <&cpg_clocks R8A7779_CLK_P>,
0570 <&cpg_clocks R8A7779_CLK_P>,
0571 <&cpg_clocks R8A7779_CLK_P>,
0572 <&cpg_clocks R8A7779_CLK_P>;
0573 #clock-cells = <1>;
0574 clock-indices = <
0575 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
0576 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
0577 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
0578 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
0579 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
0580 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
0581 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
0582 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
0583 >;
0584 clock-output-names =
0585 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
0586 "hscif0", "scif5", "scif4", "scif3", "scif2",
0587 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
0588 "i2c0";
0589 };
0590 mstp1_clks: clocks@ffc80034 {
0591 compatible = "renesas,r8a7779-mstp-clocks",
0592 "renesas,cpg-mstp-clocks";
0593 reg = <0xffc80034 4>, <0xffc80044 4>;
0594 clocks = <&cpg_clocks R8A7779_CLK_P>,
0595 <&cpg_clocks R8A7779_CLK_P>,
0596 <&cpg_clocks R8A7779_CLK_S>,
0597 <&cpg_clocks R8A7779_CLK_S>,
0598 <&cpg_clocks R8A7779_CLK_S>,
0599 <&cpg_clocks R8A7779_CLK_S>,
0600 <&cpg_clocks R8A7779_CLK_P>,
0601 <&cpg_clocks R8A7779_CLK_P>,
0602 <&cpg_clocks R8A7779_CLK_P>,
0603 <&cpg_clocks R8A7779_CLK_S>;
0604 #clock-cells = <1>;
0605 clock-indices = <
0606 R8A7779_CLK_USB01 R8A7779_CLK_USB2
0607 R8A7779_CLK_DU R8A7779_CLK_VIN2
0608 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
0609 R8A7779_CLK_ETHER R8A7779_CLK_SATA
0610 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
0611 >;
0612 clock-output-names =
0613 "usb01", "usb2",
0614 "du", "vin2",
0615 "vin1", "vin0",
0616 "ether", "sata",
0617 "pcie", "vin3";
0618 };
0619 mstp3_clks: clocks@ffc8003c {
0620 compatible = "renesas,r8a7779-mstp-clocks",
0621 "renesas,cpg-mstp-clocks";
0622 reg = <0xffc8003c 4>;
0623 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
0624 <&s4_clk>, <&s4_clk>;
0625 #clock-cells = <1>;
0626 clock-indices = <
0627 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
0628 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
0629 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
0630 >;
0631 clock-output-names =
0632 "sdhi3", "sdhi2", "sdhi1", "sdhi0",
0633 "mmc1", "mmc0";
0634 };
0635 };
0636
0637 prr: chipid@ff000044 {
0638 compatible = "renesas,prr";
0639 reg = <0xff000044 4>;
0640 };
0641
0642 rst: reset-controller@ffcc0000 {
0643 compatible = "renesas,r8a7779-reset-wdt";
0644 reg = <0xffcc0000 0x48>;
0645 };
0646
0647 sysc: system-controller@ffd85000 {
0648 compatible = "renesas,r8a7779-sysc";
0649 reg = <0xffd85000 0x0200>;
0650 #power-domain-cells = <1>;
0651 };
0652 };
