0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for the R-Car H1 (R8A77790) Marzen board
0004 *
0005 * Copyright (C) 2013 Renesas Solutions Corp.
0006 * Copyright (C) 2013 Simon Horman
0007 */
0008
0009 /dts-v1/;
0010 #include "r8a7779.dtsi"
0011 #include <dt-bindings/gpio/gpio.h>
0012 #include <dt-bindings/interrupt-controller/irq.h>
0013
0014 / {
0015 model = "marzen";
0016 compatible = "renesas,marzen", "renesas,r8a7779";
0017
0018 aliases {
0019 serial0 = &scif2;
0020 serial1 = &scif4;
0021 };
0022
0023 chosen {
0024 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
0025 stdout-path = "serial0:115200n8";
0026 };
0027
0028 memory@60000000 {
0029 device_type = "memory";
0030 reg = <0x60000000 0x40000000>;
0031 };
0032
0033 fixedregulator3v3: regulator-3v3 {
0034 compatible = "regulator-fixed";
0035 regulator-name = "fixed-3.3V";
0036 regulator-min-microvolt = <3300000>;
0037 regulator-max-microvolt = <3300000>;
0038 regulator-boot-on;
0039 regulator-always-on;
0040 };
0041
0042 vccq_sdhi0: regulator-vccq-sdhi0 {
0043 compatible = "regulator-gpio";
0044
0045 regulator-name = "SDHI0 VccQ";
0046 regulator-min-microvolt = <1800000>;
0047 regulator-max-microvolt = <3300000>;
0048
0049 gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
0050 gpios-states = <1>;
0051 states = <3300000 1>, <1800000 0>;
0052 };
0053
0054 ethernet@18000000 {
0055 compatible = "smsc,lan89218", "smsc,lan9115";
0056 reg = <0x18000000 0x100>;
0057 pinctrl-0 = <ðernet_pins>;
0058 pinctrl-names = "default";
0059
0060 phy-mode = "mii";
0061 interrupt-parent = <&irqpin0>;
0062 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
0063 smsc,irq-push-pull;
0064 reg-io-width = <4>;
0065 vddvario-supply = <&fixedregulator3v3>;
0066 vdd33a-supply = <&fixedregulator3v3>;
0067 };
0068
0069 leds {
0070 compatible = "gpio-leds";
0071 led2 {
0072 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
0073 };
0074 led3 {
0075 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
0076 };
0077 led4 {
0078 gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
0079 };
0080 };
0081
0082 vga-encoder {
0083 compatible = "adi,adv7123";
0084
0085 ports {
0086 #address-cells = <1>;
0087 #size-cells = <0>;
0088
0089 port@0 {
0090 reg = <0>;
0091 vga_enc_in: endpoint {
0092 remote-endpoint = <&du_out_rgb0>;
0093 };
0094 };
0095 port@1 {
0096 reg = <1>;
0097 vga_enc_out: endpoint {
0098 remote-endpoint = <&vga_in>;
0099 };
0100 };
0101 };
0102 };
0103
0104 vga {
0105 compatible = "vga-connector";
0106
0107 port {
0108 vga_in: endpoint {
0109 remote-endpoint = <&vga_enc_out>;
0110 };
0111 };
0112 };
0113
0114 lvds-encoder {
0115 compatible = "thine,thc63lvdm83d";
0116
0117 ports {
0118 #address-cells = <1>;
0119 #size-cells = <0>;
0120
0121 port@0 {
0122 reg = <0>;
0123 lvds_enc_in: endpoint {
0124 remote-endpoint = <&du_out_rgb1>;
0125 };
0126 };
0127 port@1 {
0128 reg = <1>;
0129 lvds_connector: endpoint {
0130 };
0131 };
0132 };
0133 };
0134
0135 x3_clk: x3-clock {
0136 compatible = "fixed-clock";
0137 #clock-cells = <0>;
0138 clock-frequency = <65000000>;
0139 };
0140 };
0141
0142 &du {
0143 pinctrl-0 = <&du_pins>;
0144 pinctrl-names = "default";
0145 status = "okay";
0146
0147 clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>;
0148 clock-names = "du.0", "dclkin.0";
0149
0150 ports {
0151 port@0 {
0152 endpoint {
0153 remote-endpoint = <&vga_enc_in>;
0154 };
0155 };
0156 port@1 {
0157 endpoint {
0158 remote-endpoint = <&lvds_enc_in>;
0159 };
0160 };
0161 };
0162 };
0163
0164 &irqpin0 {
0165 status = "okay";
0166 };
0167
0168 &extal_clk {
0169 clock-frequency = <31250000>;
0170 };
0171
0172 &tmu0 {
0173 status = "okay";
0174 };
0175
0176 &pfc {
0177 pinctrl-0 = <&scif_clk_pins>;
0178 pinctrl-names = "default";
0179
0180 du_pins: du {
0181 du0 {
0182 groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0", "du0_clk_in";
0183 function = "du0";
0184 };
0185 du1 {
0186 groups = "du1_rgb666", "du1_sync_1", "du1_clk_out";
0187 function = "du1";
0188 };
0189 };
0190
0191 scif_clk_pins: scif_clk {
0192 groups = "scif_clk_b";
0193 function = "scif_clk";
0194 };
0195
0196 ethernet_pins: ethernet {
0197 intc {
0198 groups = "intc_irq1_b";
0199 function = "intc";
0200 };
0201 lbsc {
0202 groups = "lbsc_ex_cs0";
0203 function = "lbsc";
0204 };
0205 };
0206
0207 scif2_pins: scif2 {
0208 groups = "scif2_data_c";
0209 function = "scif2";
0210 };
0211
0212 scif4_pins: scif4 {
0213 groups = "scif4_data";
0214 function = "scif4";
0215 };
0216
0217 sdhi0_pins: sd0 {
0218 groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
0219 function = "sdhi0";
0220 };
0221
0222 hspi0_pins: hspi0 {
0223 groups = "hspi0";
0224 function = "hspi0";
0225 };
0226 };
0227
0228 &sata {
0229 status = "okay";
0230 };
0231
0232 &scif2 {
0233 pinctrl-0 = <&scif2_pins>;
0234 pinctrl-names = "default";
0235
0236 status = "okay";
0237 };
0238
0239 &scif4 {
0240 pinctrl-0 = <&scif4_pins>;
0241 pinctrl-names = "default";
0242
0243 status = "okay";
0244 };
0245
0246 &scif_clk {
0247 clock-frequency = <14745600>;
0248 };
0249
0250 &sdhi0 {
0251 pinctrl-0 = <&sdhi0_pins>;
0252 pinctrl-names = "default";
0253
0254 vmmc-supply = <&fixedregulator3v3>;
0255 vqmmc-supply = <&vccq_sdhi0>;
0256 bus-width = <4>;
0257 status = "okay";
0258 };
0259
0260 &hspi0 {
0261 pinctrl-0 = <&hspi0_pins>;
0262 pinctrl-names = "default";
0263 status = "okay";
0264 };
