0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for the R-Car M1A (R8A77781) SoC
0004 *
0005 * Copyright (C) 2013 Renesas Solutions Corp.
0006 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
0007 *
0008 * based on r8a7779
0009 *
0010 * Copyright (C) 2013 Renesas Solutions Corp.
0011 * Copyright (C) 2013 Simon Horman
0012 */
0013
0014 #include <dt-bindings/clock/r8a7778-clock.h>
0015 #include <dt-bindings/interrupt-controller/arm-gic.h>
0016 #include <dt-bindings/interrupt-controller/irq.h>
0017
0018 / {
0019 compatible = "renesas,r8a7778";
0020 interrupt-parent = <&gic>;
0021 #address-cells = <1>;
0022 #size-cells = <1>;
0023
0024 cpus {
0025 #address-cells = <1>;
0026 #size-cells = <0>;
0027
0028 cpu@0 {
0029 device_type = "cpu";
0030 compatible = "arm,cortex-a9";
0031 reg = <0>;
0032 clock-frequency = <800000000>;
0033 clocks = <&z_clk>;
0034 };
0035 };
0036
0037 aliases {
0038 spi0 = &hspi0;
0039 spi1 = &hspi1;
0040 spi2 = &hspi2;
0041 };
0042
0043 bsc: bus@1c000000 {
0044 compatible = "simple-bus";
0045 #address-cells = <1>;
0046 #size-cells = <1>;
0047 ranges = <0 0 0x1c000000>;
0048 };
0049
0050 ether: ethernet@fde00000 {
0051 compatible = "renesas,ether-r8a7778",
0052 "renesas,rcar-gen1-ether";
0053 reg = <0xfde00000 0x400>;
0054 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0055 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
0056 power-domains = <&cpg_clocks>;
0057 phy-mode = "rmii";
0058 #address-cells = <1>;
0059 #size-cells = <0>;
0060 status = "disabled";
0061 };
0062
0063 gic: interrupt-controller@fe438000 {
0064 compatible = "arm,pl390";
0065 #interrupt-cells = <3>;
0066 interrupt-controller;
0067 reg = <0xfe438000 0x1000>,
0068 <0xfe430000 0x100>;
0069 };
0070
0071 /* irqpin: IRQ0 - IRQ3 */
0072 irqpin: interrupt-controller@fe78001c {
0073 compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
0074 #interrupt-cells = <2>;
0075 interrupt-controller;
0076 status = "disabled"; /* default off */
0077 reg = <0xfe78001c 4>,
0078 <0xfe780010 4>,
0079 <0xfe780024 4>,
0080 <0xfe780044 4>,
0081 <0xfe780064 4>,
0082 <0xfe780000 4>;
0083 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
0084 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
0085 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
0086 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0087 sense-bitfield-width = <2>;
0088 };
0089
0090 gpio0: gpio@ffc40000 {
0091 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
0092 reg = <0xffc40000 0x2c>;
0093 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0094 #gpio-cells = <2>;
0095 gpio-controller;
0096 gpio-ranges = <&pfc 0 0 32>;
0097 #interrupt-cells = <2>;
0098 interrupt-controller;
0099 };
0100
0101 gpio1: gpio@ffc41000 {
0102 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
0103 reg = <0xffc41000 0x2c>;
0104 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0105 #gpio-cells = <2>;
0106 gpio-controller;
0107 gpio-ranges = <&pfc 0 32 32>;
0108 #interrupt-cells = <2>;
0109 interrupt-controller;
0110 };
0111
0112 gpio2: gpio@ffc42000 {
0113 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
0114 reg = <0xffc42000 0x2c>;
0115 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0116 #gpio-cells = <2>;
0117 gpio-controller;
0118 gpio-ranges = <&pfc 0 64 32>;
0119 #interrupt-cells = <2>;
0120 interrupt-controller;
0121 };
0122
0123 gpio3: gpio@ffc43000 {
0124 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
0125 reg = <0xffc43000 0x2c>;
0126 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0127 #gpio-cells = <2>;
0128 gpio-controller;
0129 gpio-ranges = <&pfc 0 96 32>;
0130 #interrupt-cells = <2>;
0131 interrupt-controller;
0132 };
0133
0134 gpio4: gpio@ffc44000 {
0135 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
0136 reg = <0xffc44000 0x2c>;
0137 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0138 #gpio-cells = <2>;
0139 gpio-controller;
0140 gpio-ranges = <&pfc 0 128 27>;
0141 #interrupt-cells = <2>;
0142 interrupt-controller;
0143 };
0144
0145 pfc: pinctrl@fffc0000 {
0146 compatible = "renesas,pfc-r8a7778";
0147 reg = <0xfffc0000 0x118>;
0148 };
0149
0150 i2c0: i2c@ffc70000 {
0151 #address-cells = <1>;
0152 #size-cells = <0>;
0153 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
0154 reg = <0xffc70000 0x1000>;
0155 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0156 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
0157 power-domains = <&cpg_clocks>;
0158 status = "disabled";
0159 };
0160
0161 i2c1: i2c@ffc71000 {
0162 #address-cells = <1>;
0163 #size-cells = <0>;
0164 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
0165 reg = <0xffc71000 0x1000>;
0166 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
0167 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
0168 power-domains = <&cpg_clocks>;
0169 i2c-scl-internal-delay-ns = <5>;
0170 status = "disabled";
0171 };
0172
0173 i2c2: i2c@ffc72000 {
0174 #address-cells = <1>;
0175 #size-cells = <0>;
0176 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
0177 reg = <0xffc72000 0x1000>;
0178 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0179 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
0180 power-domains = <&cpg_clocks>;
0181 i2c-scl-internal-delay-ns = <5>;
0182 status = "disabled";
0183 };
0184
0185 i2c3: i2c@ffc73000 {
0186 #address-cells = <1>;
0187 #size-cells = <0>;
0188 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
0189 reg = <0xffc73000 0x1000>;
0190 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0191 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
0192 power-domains = <&cpg_clocks>;
0193 i2c-scl-internal-delay-ns = <5>;
0194 status = "disabled";
0195 };
0196
0197 tmu0: timer@ffd80000 {
0198 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
0199 reg = <0xffd80000 0x30>;
0200 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
0201 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0202 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0203 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
0204 clock-names = "fck";
0205 power-domains = <&cpg_clocks>;
0206
0207 #renesas,channels = <3>;
0208
0209 status = "disabled";
0210 };
0211
0212 tmu1: timer@ffd81000 {
0213 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
0214 reg = <0xffd81000 0x30>;
0215 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
0216 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
0217 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0218 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
0219 clock-names = "fck";
0220 power-domains = <&cpg_clocks>;
0221
0222 #renesas,channels = <3>;
0223
0224 status = "disabled";
0225 };
0226
0227 tmu2: timer@ffd82000 {
0228 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
0229 reg = <0xffd82000 0x30>;
0230 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
0231 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
0232 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0233 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
0234 clock-names = "fck";
0235 power-domains = <&cpg_clocks>;
0236
0237 #renesas,channels = <3>;
0238
0239 status = "disabled";
0240 };
0241
0242 rcar_sound: sound@ffd90000 {
0243 /*
0244 * #sound-dai-cells is required
0245 *
0246 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
0247 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
0248 */
0249 compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
0250 reg = <0xffd90000 0x1000>, /* SRU */
0251 <0xffd91000 0x240>, /* SSI */
0252 <0xfffe0000 0x24>; /* ADG */
0253 clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
0254 <&mstp3_clks R8A7778_CLK_SSI7>,
0255 <&mstp3_clks R8A7778_CLK_SSI6>,
0256 <&mstp3_clks R8A7778_CLK_SSI5>,
0257 <&mstp3_clks R8A7778_CLK_SSI4>,
0258 <&mstp0_clks R8A7778_CLK_SSI3>,
0259 <&mstp0_clks R8A7778_CLK_SSI2>,
0260 <&mstp0_clks R8A7778_CLK_SSI1>,
0261 <&mstp0_clks R8A7778_CLK_SSI0>,
0262 <&mstp5_clks R8A7778_CLK_SRU_SRC8>,
0263 <&mstp5_clks R8A7778_CLK_SRU_SRC7>,
0264 <&mstp5_clks R8A7778_CLK_SRU_SRC6>,
0265 <&mstp5_clks R8A7778_CLK_SRU_SRC5>,
0266 <&mstp5_clks R8A7778_CLK_SRU_SRC4>,
0267 <&mstp5_clks R8A7778_CLK_SRU_SRC3>,
0268 <&mstp5_clks R8A7778_CLK_SRU_SRC2>,
0269 <&mstp5_clks R8A7778_CLK_SRU_SRC1>,
0270 <&mstp5_clks R8A7778_CLK_SRU_SRC0>,
0271 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
0272 <&cpg_clocks R8A7778_CLK_S1>;
0273 clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
0274 "ssi.3", "ssi.2", "ssi.1", "ssi.0",
0275 "src.8", "src.7", "src.6", "src.5", "src.4",
0276 "src.3", "src.2", "src.1", "src.0",
0277 "clk_a", "clk_b", "clk_c", "clk_i";
0278
0279 status = "disabled";
0280
0281 rcar_sound,src {
0282 src3: src-3 { };
0283 src4: src-4 { };
0284 src5: src-5 { };
0285 src6: src-6 { };
0286 src7: src-7 { };
0287 src8: src-8 { };
0288 src9: src-9 { };
0289 };
0290
0291 rcar_sound,ssi {
0292 ssi3: ssi-3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
0293 ssi4: ssi-4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
0294 ssi5: ssi-5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
0295 ssi6: ssi-6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
0296 ssi7: ssi-7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
0297 ssi8: ssi-8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
0298 ssi9: ssi-9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
0299 };
0300 };
0301
0302 scif0: serial@ffe40000 {
0303 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
0304 "renesas,scif";
0305 reg = <0xffe40000 0x100>;
0306 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
0307 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>,
0308 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
0309 clock-names = "fck", "brg_int", "scif_clk";
0310 power-domains = <&cpg_clocks>;
0311 status = "disabled";
0312 };
0313
0314 scif1: serial@ffe41000 {
0315 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
0316 "renesas,scif";
0317 reg = <0xffe41000 0x100>;
0318 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0319 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>,
0320 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
0321 clock-names = "fck", "brg_int", "scif_clk";
0322 power-domains = <&cpg_clocks>;
0323 status = "disabled";
0324 };
0325
0326 scif2: serial@ffe42000 {
0327 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
0328 "renesas,scif";
0329 reg = <0xffe42000 0x100>;
0330 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0331 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>,
0332 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
0333 clock-names = "fck", "brg_int", "scif_clk";
0334 power-domains = <&cpg_clocks>;
0335 status = "disabled";
0336 };
0337
0338 scif3: serial@ffe43000 {
0339 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
0340 "renesas,scif";
0341 reg = <0xffe43000 0x100>;
0342 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0343 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>,
0344 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
0345 clock-names = "fck", "brg_int", "scif_clk";
0346 power-domains = <&cpg_clocks>;
0347 status = "disabled";
0348 };
0349
0350 scif4: serial@ffe44000 {
0351 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
0352 "renesas,scif";
0353 reg = <0xffe44000 0x100>;
0354 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0355 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>,
0356 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
0357 clock-names = "fck", "brg_int", "scif_clk";
0358 power-domains = <&cpg_clocks>;
0359 status = "disabled";
0360 };
0361
0362 scif5: serial@ffe45000 {
0363 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
0364 "renesas,scif";
0365 reg = <0xffe45000 0x100>;
0366 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0367 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>,
0368 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
0369 clock-names = "fck", "brg_int", "scif_clk";
0370 power-domains = <&cpg_clocks>;
0371 status = "disabled";
0372 };
0373
0374 hscif0: serial@ffe48000 {
0375 compatible = "renesas,hscif-r8a7778",
0376 "renesas,rcar-gen1-hscif", "renesas,hscif";
0377 reg = <0xffe48000 96>;
0378 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
0379 clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>,
0380 <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
0381 clock-names = "fck", "brg_int", "scif_clk";
0382 power-domains = <&cpg_clocks>;
0383 status = "disabled";
0384 };
0385
0386 hscif1: serial@ffe49000 {
0387 compatible = "renesas,hscif-r8a7778",
0388 "renesas,rcar-gen1-hscif", "renesas,hscif";
0389 reg = <0xffe49000 96>;
0390 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
0391 clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>,
0392 <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
0393 clock-names = "fck", "brg_int", "scif_clk";
0394 power-domains = <&cpg_clocks>;
0395 status = "disabled";
0396 };
0397
0398 mmcif: mmc@ffe4e000 {
0399 compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
0400 reg = <0xffe4e000 0x100>;
0401 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0402 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
0403 power-domains = <&cpg_clocks>;
0404 status = "disabled";
0405 };
0406
0407 sdhi0: mmc@ffe4c000 {
0408 compatible = "renesas,sdhi-r8a7778",
0409 "renesas,rcar-gen1-sdhi";
0410 reg = <0xffe4c000 0x100>;
0411 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0412 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
0413 power-domains = <&cpg_clocks>;
0414 status = "disabled";
0415 };
0416
0417 sdhi1: mmc@ffe4d000 {
0418 compatible = "renesas,sdhi-r8a7778",
0419 "renesas,rcar-gen1-sdhi";
0420 reg = <0xffe4d000 0x100>;
0421 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0422 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
0423 power-domains = <&cpg_clocks>;
0424 status = "disabled";
0425 };
0426
0427 sdhi2: mmc@ffe4f000 {
0428 compatible = "renesas,sdhi-r8a7778",
0429 "renesas,rcar-gen1-sdhi";
0430 reg = <0xffe4f000 0x100>;
0431 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0432 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
0433 power-domains = <&cpg_clocks>;
0434 status = "disabled";
0435 };
0436
0437 hspi0: spi@fffc7000 {
0438 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
0439 reg = <0xfffc7000 0x18>;
0440 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0441 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
0442 power-domains = <&cpg_clocks>;
0443 #address-cells = <1>;
0444 #size-cells = <0>;
0445 status = "disabled";
0446 };
0447
0448 hspi1: spi@fffc8000 {
0449 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
0450 reg = <0xfffc8000 0x18>;
0451 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0452 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
0453 power-domains = <&cpg_clocks>;
0454 #address-cells = <1>;
0455 #size-cells = <0>;
0456 status = "disabled";
0457 };
0458
0459 hspi2: spi@fffc6000 {
0460 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
0461 reg = <0xfffc6000 0x18>;
0462 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0463 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
0464 power-domains = <&cpg_clocks>;
0465 #address-cells = <1>;
0466 #size-cells = <0>;
0467 status = "disabled";
0468 };
0469
0470 clocks {
0471 #address-cells = <1>;
0472 #size-cells = <1>;
0473 ranges;
0474
0475 /* External input clock */
0476 extal_clk: extal {
0477 compatible = "fixed-clock";
0478 #clock-cells = <0>;
0479 clock-frequency = <0>;
0480 };
0481
0482 /* External SCIF clock */
0483 scif_clk: scif {
0484 compatible = "fixed-clock";
0485 #clock-cells = <0>;
0486 /* This value must be overridden by the board. */
0487 clock-frequency = <0>;
0488 };
0489
0490 /* Special CPG clocks */
0491 cpg_clocks: cpg_clocks@ffc80000 {
0492 compatible = "renesas,r8a7778-cpg-clocks";
0493 reg = <0xffc80000 0x80>;
0494 #clock-cells = <1>;
0495 clocks = <&extal_clk>;
0496 clock-output-names = "plla", "pllb", "b",
0497 "out", "p", "s", "s1";
0498 #power-domain-cells = <0>;
0499 };
0500
0501 /* Audio clocks; frequencies are set by boards if applicable. */
0502 audio_clk_a: audio_clk_a {
0503 compatible = "fixed-clock";
0504 #clock-cells = <0>;
0505 clock-frequency = <0>;
0506 };
0507 audio_clk_b: audio_clk_b {
0508 compatible = "fixed-clock";
0509 #clock-cells = <0>;
0510 clock-frequency = <0>;
0511 };
0512 audio_clk_c: audio_clk_c {
0513 compatible = "fixed-clock";
0514 #clock-cells = <0>;
0515 clock-frequency = <0>;
0516 };
0517
0518 /* Fixed ratio clocks */
0519 g_clk: g {
0520 compatible = "fixed-factor-clock";
0521 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
0522 #clock-cells = <0>;
0523 clock-div = <12>;
0524 clock-mult = <1>;
0525 };
0526 i_clk: i {
0527 compatible = "fixed-factor-clock";
0528 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
0529 #clock-cells = <0>;
0530 clock-div = <1>;
0531 clock-mult = <1>;
0532 };
0533 s3_clk: s3 {
0534 compatible = "fixed-factor-clock";
0535 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
0536 #clock-cells = <0>;
0537 clock-div = <4>;
0538 clock-mult = <1>;
0539 };
0540 s4_clk: s4 {
0541 compatible = "fixed-factor-clock";
0542 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
0543 #clock-cells = <0>;
0544 clock-div = <8>;
0545 clock-mult = <1>;
0546 };
0547 z_clk: z {
0548 compatible = "fixed-factor-clock";
0549 clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
0550 #clock-cells = <0>;
0551 clock-div = <1>;
0552 clock-mult = <1>;
0553 };
0554
0555 /* Gate clocks */
0556 mstp0_clks: mstp0_clks@ffc80030 {
0557 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
0558 reg = <0xffc80030 4>;
0559 clocks = <&cpg_clocks R8A7778_CLK_P>,
0560 <&cpg_clocks R8A7778_CLK_P>,
0561 <&cpg_clocks R8A7778_CLK_P>,
0562 <&cpg_clocks R8A7778_CLK_P>,
0563 <&cpg_clocks R8A7778_CLK_P>,
0564 <&cpg_clocks R8A7778_CLK_P>,
0565 <&cpg_clocks R8A7778_CLK_P>,
0566 <&cpg_clocks R8A7778_CLK_P>,
0567 <&cpg_clocks R8A7778_CLK_P>,
0568 <&cpg_clocks R8A7778_CLK_P>,
0569 <&cpg_clocks R8A7778_CLK_S>,
0570 <&cpg_clocks R8A7778_CLK_S>,
0571 <&cpg_clocks R8A7778_CLK_P>,
0572 <&cpg_clocks R8A7778_CLK_P>,
0573 <&cpg_clocks R8A7778_CLK_P>,
0574 <&cpg_clocks R8A7778_CLK_P>,
0575 <&cpg_clocks R8A7778_CLK_P>,
0576 <&cpg_clocks R8A7778_CLK_P>,
0577 <&cpg_clocks R8A7778_CLK_P>,
0578 <&cpg_clocks R8A7778_CLK_P>,
0579 <&cpg_clocks R8A7778_CLK_S>;
0580 #clock-cells = <1>;
0581 clock-indices = <
0582 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
0583 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
0584 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
0585 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
0586 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
0587 R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1
0588 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
0589 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
0590 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
0591 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
0592 R8A7778_CLK_HSPI
0593 >;
0594 clock-output-names =
0595 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
0596 "scif1", "scif2", "scif3", "scif4", "scif5",
0597 "hscif0", "hscif1",
0598 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
0599 "ssi2", "ssi3", "sru", "hspi";
0600 };
0601 mstp1_clks: mstp1_clks@ffc80034 {
0602 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
0603 reg = <0xffc80034 4>, <0xffc80044 4>;
0604 clocks = <&cpg_clocks R8A7778_CLK_P>,
0605 <&cpg_clocks R8A7778_CLK_S>,
0606 <&cpg_clocks R8A7778_CLK_S>,
0607 <&cpg_clocks R8A7778_CLK_P>;
0608 #clock-cells = <1>;
0609 clock-indices = <
0610 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
0611 R8A7778_CLK_VIN1 R8A7778_CLK_USB
0612 >;
0613 clock-output-names =
0614 "ether", "vin0", "vin1", "usb";
0615 };
0616 mstp3_clks: mstp3_clks@ffc8003c {
0617 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
0618 reg = <0xffc8003c 4>;
0619 clocks = <&s4_clk>,
0620 <&cpg_clocks R8A7778_CLK_P>,
0621 <&cpg_clocks R8A7778_CLK_P>,
0622 <&cpg_clocks R8A7778_CLK_P>,
0623 <&cpg_clocks R8A7778_CLK_P>,
0624 <&cpg_clocks R8A7778_CLK_P>,
0625 <&cpg_clocks R8A7778_CLK_P>,
0626 <&cpg_clocks R8A7778_CLK_P>,
0627 <&cpg_clocks R8A7778_CLK_P>;
0628 #clock-cells = <1>;
0629 clock-indices = <
0630 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
0631 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
0632 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
0633 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
0634 R8A7778_CLK_SSI8
0635 >;
0636 clock-output-names =
0637 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
0638 "ssi5", "ssi6", "ssi7", "ssi8";
0639 };
0640 mstp5_clks: mstp5_clks@ffc80054 {
0641 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
0642 reg = <0xffc80054 4>;
0643 clocks = <&cpg_clocks R8A7778_CLK_P>,
0644 <&cpg_clocks R8A7778_CLK_P>,
0645 <&cpg_clocks R8A7778_CLK_P>,
0646 <&cpg_clocks R8A7778_CLK_P>,
0647 <&cpg_clocks R8A7778_CLK_P>,
0648 <&cpg_clocks R8A7778_CLK_P>,
0649 <&cpg_clocks R8A7778_CLK_P>,
0650 <&cpg_clocks R8A7778_CLK_P>,
0651 <&cpg_clocks R8A7778_CLK_P>;
0652 #clock-cells = <1>;
0653 clock-indices = <
0654 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
0655 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
0656 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
0657 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
0658 R8A7778_CLK_SRU_SRC8
0659 >;
0660 clock-output-names =
0661 "sru-src0", "sru-src1", "sru-src2",
0662 "sru-src3", "sru-src4", "sru-src5",
0663 "sru-src6", "sru-src7", "sru-src8";
0664 };
0665 };
0666
0667 rst: reset-controller@ffcc0000 {
0668 compatible = "renesas,r8a7778-reset-wdt";
0669 reg = <0xffcc0000 0x40>;
0670 };
0671 };
