0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for the SK-RZG1E board
0004 *
0005 * Copyright (C) 2016-2017 Cogent Embedded, Inc.
0006 */
0007
0008 /dts-v1/;
0009 #include "r8a7745.dtsi"
0010 #include <dt-bindings/gpio/gpio.h>
0011
0012 / {
0013 model = "SK-RZG1E";
0014 compatible = "renesas,sk-rzg1e", "renesas,r8a7745";
0015
0016 aliases {
0017 serial0 = &scif2;
0018 };
0019
0020 chosen {
0021 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
0022 stdout-path = "serial0:115200n8";
0023 };
0024
0025 memory@40000000 {
0026 device_type = "memory";
0027 reg = <0 0x40000000 0 0x40000000>;
0028 };
0029 };
0030
0031 &extal_clk {
0032 clock-frequency = <20000000>;
0033 };
0034
0035 &pfc {
0036 scif2_pins: scif2 {
0037 groups = "scif2_data";
0038 function = "scif2";
0039 };
0040
0041 ether_pins: ether {
0042 groups = "eth_link", "eth_mdio", "eth_rmii";
0043 function = "eth";
0044 };
0045
0046 phy1_pins: phy1 {
0047 groups = "intc_irq8";
0048 function = "intc";
0049 };
0050 };
0051
0052 &scif2 {
0053 pinctrl-0 = <&scif2_pins>;
0054 pinctrl-names = "default";
0055
0056 status = "okay";
0057 };
0058
0059 ðer {
0060 pinctrl-0 = <ðer_pins>, <&phy1_pins>;
0061 pinctrl-names = "default";
0062
0063 phy-handle = <&phy1>;
0064 renesas,ether-link-active-low;
0065 status = "okay";
0066
0067 phy1: ethernet-phy@1 {
0068 compatible = "ethernet-phy-id0022.1537",
0069 "ethernet-phy-ieee802.3-c22";
0070 reg = <1>;
0071 interrupt-parent = <&irqc>;
0072 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
0073 micrel,led-mode = <1>;
0074 reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
0075 };
0076 };