0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for the SK-RZG1M board
0004 *
0005 * Copyright (C) 2016-2017 Cogent Embedded, Inc.
0006 */
0007
0008 /dts-v1/;
0009 #include "r8a7743.dtsi"
0010 #include <dt-bindings/gpio/gpio.h>
0011
0012 / {
0013 model = "SK-RZG1M";
0014 compatible = "renesas,sk-rzg1m", "renesas,r8a7743";
0015
0016 aliases {
0017 serial0 = &scif0;
0018 };
0019
0020 chosen {
0021 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
0022 stdout-path = "serial0:115200n8";
0023 };
0024
0025 memory@40000000 {
0026 device_type = "memory";
0027 reg = <0 0x40000000 0 0x40000000>;
0028 };
0029
0030 memory@200000000 {
0031 device_type = "memory";
0032 reg = <2 0x00000000 0 0x40000000>;
0033 };
0034 };
0035
0036 &extal_clk {
0037 clock-frequency = <20000000>;
0038 };
0039
0040 &pfc {
0041 scif0_pins: scif0 {
0042 groups = "scif0_data_d";
0043 function = "scif0";
0044 };
0045
0046 ether_pins: ether {
0047 groups = "eth_link", "eth_mdio", "eth_rmii";
0048 function = "eth";
0049 };
0050
0051 phy1_pins: phy1 {
0052 groups = "intc_irq0";
0053 function = "intc";
0054 };
0055 };
0056
0057 &scif0 {
0058 pinctrl-0 = <&scif0_pins>;
0059 pinctrl-names = "default";
0060
0061 status = "okay";
0062 };
0063
0064 ðer {
0065 pinctrl-0 = <ðer_pins>, <&phy1_pins>;
0066 pinctrl-names = "default";
0067
0068 phy-handle = <&phy1>;
0069 renesas,ether-link-active-low;
0070 status = "okay";
0071
0072 phy1: ethernet-phy@1 {
0073 compatible = "ethernet-phy-id0022.1537",
0074 "ethernet-phy-ieee802.3-c22";
0075 reg = <1>;
0076 interrupt-parent = <&irqc>;
0077 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
0078 micrel,led-mode = <1>;
0079 reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
0080 };
0081 };