0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for the iWave-RZ/G1H Qseven board development
0004 * platform with camera daughter board
0005 *
0006 * Copyright (C) 2020 Renesas Electronics Corp.
0007 */
0008
0009 /dts-v1/;
0010 #include "r8a7742-iwg21d-q7.dts"
0011
0012 / {
0013 model = "iWave Systems RZ/G1H Qseven development platform with camera add-on";
0014 compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742";
0015
0016 aliases {
0017 serial0 = &scif0;
0018 serial1 = &scif1;
0019 serial3 = &scifb1;
0020 serial5 = &hscif0;
0021 ethernet1 = ðer;
0022 };
0023
0024 mclk_cam1: mclk-cam1 {
0025 compatible = "fixed-clock";
0026 #clock-cells = <0>;
0027 clock-frequency = <26000000>;
0028 };
0029
0030 mclk_cam2: mclk-cam2 {
0031 compatible = "fixed-clock";
0032 #clock-cells = <0>;
0033 clock-frequency = <26000000>;
0034 };
0035
0036 mclk_cam3: mclk-cam3 {
0037 compatible = "fixed-clock";
0038 #clock-cells = <0>;
0039 clock-frequency = <26000000>;
0040 };
0041
0042 mclk_cam4: mclk-cam4 {
0043 compatible = "fixed-clock";
0044 #clock-cells = <0>;
0045 clock-frequency = <26000000>;
0046 };
0047
0048 reg_1p8v: 1p8v {
0049 compatible = "regulator-fixed";
0050 regulator-name = "1P8V";
0051 regulator-min-microvolt = <1800000>;
0052 regulator-max-microvolt = <1800000>;
0053 regulator-always-on;
0054 };
0055
0056 reg_2p8v: 2p8v {
0057 compatible = "regulator-fixed";
0058 regulator-name = "2P8V";
0059 regulator-min-microvolt = <2800000>;
0060 regulator-max-microvolt = <2800000>;
0061 regulator-always-on;
0062 };
0063 };
0064
0065 &avb {
0066 /* Pins shared with VIN0, keep status disabled */
0067 status = "disabled";
0068 };
0069
0070 &can0 {
0071 pinctrl-0 = <&can0_pins>;
0072 pinctrl-names = "default";
0073 status = "okay";
0074 };
0075
0076 ðer {
0077 pinctrl-0 = <ðer_pins>;
0078 pinctrl-names = "default";
0079
0080 phy-handle = <&phy1>;
0081 renesas,ether-link-active-low;
0082 status = "okay";
0083
0084 phy1: ethernet-phy@1 {
0085 compatible = "ethernet-phy-id0022.1560",
0086 "ethernet-phy-ieee802.3-c22";
0087 reg = <1>;
0088 micrel,led-mode = <1>;
0089 };
0090 };
0091
0092 &gpio0 {
0093 /* Disable hogging GP0_18 to output LOW */
0094 /delete-node/ qspi-en-hog;
0095
0096 /* Hog GP0_18 to output HIGH to enable VIN2 */
0097 vin2-en-hog {
0098 gpio-hog;
0099 gpios = <18 GPIO_ACTIVE_HIGH>;
0100 output-high;
0101 line-name = "VIN2_EN";
0102 };
0103 };
0104
0105 &hscif0 {
0106 pinctrl-0 = <&hscif0_pins>;
0107 pinctrl-names = "default";
0108 uart-has-rtscts;
0109 status = "okay";
0110 };
0111
0112 &i2c1 {
0113 pinctrl-0 = <&i2c1_pins>;
0114 pinctrl-names = "default";
0115
0116 /* status set to "okay" when needed by camera configuration below */
0117 clock-frequency = <400000>;
0118 };
0119
0120 &i2c3 {
0121 pinctrl-0 = <&i2c3_pins>;
0122 pinctrl-names = "default";
0123
0124 /* status set to "okay" when needed by camera configuration below */
0125 clock-frequency = <400000>;
0126 };
0127
0128 &pfc {
0129 can0_pins: can0 {
0130 groups = "can0_data_d";
0131 function = "can0";
0132 };
0133
0134 ether_pins: ether {
0135 groups = "eth_mdio", "eth_rmii";
0136 function = "eth";
0137 };
0138
0139 hscif0_pins: hscif0 {
0140 groups = "hscif0_data", "hscif0_ctrl";
0141 function = "hscif0";
0142 };
0143
0144 i2c1_pins: i2c1 {
0145 groups = "i2c1_c";
0146 function = "i2c1";
0147 };
0148
0149 i2c3_pins: i2c3 {
0150 groups = "i2c3";
0151 function = "i2c3";
0152 };
0153
0154 scif0_pins: scif0 {
0155 groups = "scif0_data";
0156 function = "scif0";
0157 };
0158
0159 scif1_pins: scif1 {
0160 groups = "scif1_data";
0161 function = "scif1";
0162 };
0163
0164 scifb1_pins: scifb1 {
0165 groups = "scifb1_data";
0166 function = "scifb1";
0167 };
0168
0169 vin0_8bit_pins: vin0 {
0170 groups = "vin0_data8", "vin0_clk", "vin0_sync";
0171 function = "vin0";
0172 };
0173
0174 vin1_8bit_pins: vin1 {
0175 groups = "vin1_data8_b", "vin1_clk_b", "vin1_sync_b";
0176 function = "vin1";
0177 };
0178
0179 vin2_pins: vin2 {
0180 groups = "vin2_g8", "vin2_clk";
0181 function = "vin2";
0182 };
0183
0184 vin3_pins: vin3 {
0185 groups = "vin3_data8", "vin3_clk", "vin3_sync";
0186 function = "vin3";
0187 };
0188 };
0189
0190 &qspi {
0191 /* Pins shared with VIN2, keep status disabled */
0192 status = "disabled";
0193 };
0194
0195 &scif0 {
0196 pinctrl-0 = <&scif0_pins>;
0197 pinctrl-names = "default";
0198 status = "okay";
0199 };
0200
0201 &scif1 {
0202 pinctrl-0 = <&scif1_pins>;
0203 pinctrl-names = "default";
0204 status = "okay";
0205 };
0206
0207 &scifb1 {
0208 pinctrl-0 = <&scifb1_pins>;
0209 pinctrl-names = "default";
0210 status = "okay";
0211
0212 rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
0213 cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
0214 };
0215
0216 /*
0217 * Below configuration ties VINx endpoints to ov5640/ov7725 camera endpoints
0218 *
0219 * (un)comment the #include statements to change configuration
0220 */
0221
0222 /* 8bit CMOS Camera 1 (J13) */
0223 #define CAM_PARENT_I2C i2c0
0224 #define MCLK_CAM mclk_cam1
0225 #define CAM_EP cam0ep
0226 #define VIN_EP vin0ep
0227 #undef CAM_ENABLED
0228 #include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
0229 //#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"
0230
0231 #ifdef CAM_ENABLED
0232 &vin0 {
0233 /*
0234 * Set SW2 switch on the SOM to 'ON'
0235 * Set SW1 switch on camera board to 'OFF' as we are using 8bit mode
0236 */
0237 status = "okay";
0238 pinctrl-0 = <&vin0_8bit_pins>;
0239 pinctrl-names = "default";
0240
0241 port {
0242 vin0ep: endpoint {
0243 remote-endpoint = <&cam0ep>;
0244 bus-width = <8>;
0245 bus-type = <6>;
0246 };
0247 };
0248 };
0249 #endif /* CAM_ENABLED */
0250
0251 #undef CAM_PARENT_I2C
0252 #undef MCLK_CAM
0253 #undef CAM_EP
0254 #undef VIN_EP
0255
0256 /* 8bit CMOS Camera 2 (J14) */
0257 #define CAM_PARENT_I2C i2c1
0258 #define MCLK_CAM mclk_cam2
0259 #define CAM_EP cam1ep
0260 #define VIN_EP vin1ep
0261 #undef CAM_ENABLED
0262 #include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
0263 //#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"
0264
0265 #ifdef CAM_ENABLED
0266 &vin1 {
0267 /* Set SW1 switch on the SOM to 'ON' */
0268 status = "okay";
0269 pinctrl-0 = <&vin1_8bit_pins>;
0270 pinctrl-names = "default";
0271
0272 port {
0273 vin1ep: endpoint {
0274 remote-endpoint = <&cam1ep>;
0275 bus-width = <8>;
0276 bus-type = <6>;
0277 };
0278 };
0279 };
0280
0281 #endif /* CAM_ENABLED */
0282
0283 #undef CAM_PARENT_I2C
0284 #undef MCLK_CAM
0285 #undef CAM_EP
0286 #undef VIN_EP
0287
0288 /* 8bit CMOS Camera 3 (J12) */
0289 #define CAM_PARENT_I2C i2c2
0290 #define MCLK_CAM mclk_cam3
0291 #define CAM_EP cam2ep
0292 #define VIN_EP vin2ep
0293 #undef CAM_ENABLED
0294 #include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
0295 //#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"
0296
0297 #ifdef CAM_ENABLED
0298 &vin2 {
0299 status = "okay";
0300 pinctrl-0 = <&vin2_pins>;
0301 pinctrl-names = "default";
0302
0303 port {
0304 vin2ep: endpoint {
0305 remote-endpoint = <&cam2ep>;
0306 bus-width = <8>;
0307 data-shift = <8>;
0308 bus-type = <6>;
0309 };
0310 };
0311 };
0312 #endif /* CAM_ENABLED */
0313
0314 #undef CAM_PARENT_I2C
0315 #undef MCLK_CAM
0316 #undef CAM_EP
0317 #undef VIN_EP
0318
0319 /* 8bit CMOS Camera 4 (J11) */
0320 #define CAM_PARENT_I2C i2c3
0321 #define MCLK_CAM mclk_cam4
0322 #define CAM_EP cam3ep
0323 #define VIN_EP vin3ep
0324 #undef CAM_ENABLED
0325 #include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
0326 //#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"
0327
0328 #ifdef CAM_ENABLED
0329 &vin3 {
0330 status = "okay";
0331 pinctrl-0 = <&vin3_pins>;
0332 pinctrl-names = "default";
0333
0334 port {
0335 vin3ep: endpoint {
0336 remote-endpoint = <&cam3ep>;
0337 bus-width = <8>;
0338 bus-type = <6>;
0339 };
0340 };
0341 };
0342 #endif /* CAM_ENABLED */
0343
0344 #undef CAM_PARENT_I2C
0345 #undef MCLK_CAM
0346 #undef CAM_EP
0347 #undef VIN_EP
