0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
0004 *
0005 * Copyright (C) 2012 Renesas Solutions Corp.
0006 */
0007
0008 #include <dt-bindings/clock/r8a7740-clock.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/interrupt-controller/irq.h>
0011
0012 / {
0013 compatible = "renesas,r8a7740";
0014 interrupt-parent = <&gic>;
0015 #address-cells = <1>;
0016 #size-cells = <1>;
0017
0018 cpus {
0019 #address-cells = <1>;
0020 #size-cells = <0>;
0021 cpu@0 {
0022 compatible = "arm,cortex-a9";
0023 device_type = "cpu";
0024 reg = <0x0>;
0025 clock-frequency = <800000000>;
0026 power-domains = <&pd_a3sm>;
0027 next-level-cache = <&L2>;
0028 };
0029 };
0030
0031 gic: interrupt-controller@c2800000 {
0032 compatible = "arm,pl390";
0033 #interrupt-cells = <3>;
0034 interrupt-controller;
0035 reg = <0xc2800000 0x1000>,
0036 <0xc2000000 0x1000>;
0037 };
0038
0039 L2: cache-controller@f0100000 {
0040 compatible = "arm,pl310-cache";
0041 reg = <0xf0100000 0x1000>;
0042 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0043 power-domains = <&pd_a3sm>;
0044 arm,data-latency = <3 3 3>;
0045 arm,tag-latency = <2 2 2>;
0046 arm,shared-override;
0047 cache-unified;
0048 cache-level = <2>;
0049 };
0050
0051 dbsc3: memory-controller@fe400000 {
0052 compatible = "renesas,dbsc3-r8a7740";
0053 reg = <0xfe400000 0x400>;
0054 power-domains = <&pd_a4s>;
0055 };
0056
0057 pmu {
0058 compatible = "arm,cortex-a9-pmu";
0059 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0060 };
0061
0062 ptm {
0063 compatible = "arm,coresight-etm3x";
0064 power-domains = <&pd_d4>;
0065 };
0066
0067 ceu0: ceu@fe910000 {
0068 reg = <0xfe910000 0x3000>;
0069 compatible = "renesas,r8a7740-ceu";
0070 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
0071 clocks = <&mstp1_clks R8A7740_CLK_CEU20>;
0072 power-domains = <&pd_a4r>;
0073 status = "disabled";
0074 };
0075
0076 ceu1: ceu@fe914000 {
0077 reg = <0xfe914000 0x3000>;
0078 compatible = "renesas,r8a7740-ceu";
0079 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
0080 clocks = <&mstp1_clks R8A7740_CLK_CEU21>;
0081 power-domains = <&pd_a4r>;
0082 status = "disabled";
0083 };
0084
0085 cmt1: timer@e6138000 {
0086 compatible = "renesas,r8a7740-cmt1";
0087 reg = <0xe6138000 0x170>;
0088 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0089 clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
0090 clock-names = "fck";
0091 power-domains = <&pd_c5>;
0092 status = "disabled";
0093 };
0094
0095 /* irqpin0: IRQ0 - IRQ7 */
0096 irqpin0: interrupt-controller@e6900000 {
0097 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
0098 #interrupt-cells = <2>;
0099 interrupt-controller;
0100 reg = <0xe6900000 4>,
0101 <0xe6900010 4>,
0102 <0xe6900020 1>,
0103 <0xe6900040 1>,
0104 <0xe6900060 1>;
0105 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0106 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0107 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0108 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0109 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0110 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0111 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0112 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
0113 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
0114 power-domains = <&pd_a4s>;
0115 };
0116
0117 /* irqpin1: IRQ8 - IRQ15 */
0118 irqpin1: interrupt-controller@e6900004 {
0119 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
0120 #interrupt-cells = <2>;
0121 interrupt-controller;
0122 reg = <0xe6900004 4>,
0123 <0xe6900014 4>,
0124 <0xe6900024 1>,
0125 <0xe6900044 1>,
0126 <0xe6900064 1>;
0127 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0128 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0129 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0130 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0131 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0132 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0133 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0134 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
0135 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
0136 power-domains = <&pd_a4s>;
0137 };
0138
0139 /* irqpin2: IRQ16 - IRQ23 */
0140 irqpin2: interrupt-controller@e6900008 {
0141 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
0142 #interrupt-cells = <2>;
0143 interrupt-controller;
0144 reg = <0xe6900008 4>,
0145 <0xe6900018 4>,
0146 <0xe6900028 1>,
0147 <0xe6900048 1>,
0148 <0xe6900068 1>;
0149 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0150 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0151 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0152 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0153 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0154 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0155 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0156 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
0157 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
0158 power-domains = <&pd_a4s>;
0159 };
0160
0161 /* irqpin3: IRQ24 - IRQ31 */
0162 irqpin3: interrupt-controller@e690000c {
0163 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
0164 #interrupt-cells = <2>;
0165 interrupt-controller;
0166 reg = <0xe690000c 4>,
0167 <0xe690001c 4>,
0168 <0xe690002c 1>,
0169 <0xe690004c 1>,
0170 <0xe690006c 1>;
0171 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0172 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0173 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0174 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0175 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0176 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0177 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
0178 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
0179 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
0180 power-domains = <&pd_a4s>;
0181 };
0182
0183 ether: ethernet@e9a00000 {
0184 compatible = "renesas,gether-r8a7740";
0185 reg = <0xe9a00000 0x800>,
0186 <0xe9a01800 0x800>;
0187 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0188 clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
0189 power-domains = <&pd_a4s>;
0190 phy-mode = "mii";
0191 #address-cells = <1>;
0192 #size-cells = <0>;
0193 status = "disabled";
0194 };
0195
0196 i2c0: i2c@fff20000 {
0197 #address-cells = <1>;
0198 #size-cells = <0>;
0199 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
0200 reg = <0xfff20000 0x425>;
0201 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
0202 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
0203 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
0204 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
0205 clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
0206 power-domains = <&pd_a4r>;
0207 status = "disabled";
0208 };
0209
0210 i2c1: i2c@e6c20000 {
0211 #address-cells = <1>;
0212 #size-cells = <0>;
0213 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
0214 reg = <0xe6c20000 0x425>;
0215 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0216 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
0217 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
0218 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0219 clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
0220 power-domains = <&pd_a3sp>;
0221 status = "disabled";
0222 };
0223
0224 scifa0: serial@e6c40000 {
0225 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
0226 reg = <0xe6c40000 0x100>;
0227 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0228 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
0229 clock-names = "fck";
0230 power-domains = <&pd_a3sp>;
0231 status = "disabled";
0232 };
0233
0234 scifa1: serial@e6c50000 {
0235 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
0236 reg = <0xe6c50000 0x100>;
0237 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
0238 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
0239 clock-names = "fck";
0240 power-domains = <&pd_a3sp>;
0241 status = "disabled";
0242 };
0243
0244 scifa2: serial@e6c60000 {
0245 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
0246 reg = <0xe6c60000 0x100>;
0247 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
0248 clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
0249 clock-names = "fck";
0250 power-domains = <&pd_a3sp>;
0251 status = "disabled";
0252 };
0253
0254 scifa3: serial@e6c70000 {
0255 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
0256 reg = <0xe6c70000 0x100>;
0257 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0258 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
0259 clock-names = "fck";
0260 power-domains = <&pd_a3sp>;
0261 status = "disabled";
0262 };
0263
0264 scifa4: serial@e6c80000 {
0265 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
0266 reg = <0xe6c80000 0x100>;
0267 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
0268 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
0269 clock-names = "fck";
0270 power-domains = <&pd_a3sp>;
0271 status = "disabled";
0272 };
0273
0274 scifa5: serial@e6cb0000 {
0275 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
0276 reg = <0xe6cb0000 0x100>;
0277 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0278 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
0279 clock-names = "fck";
0280 power-domains = <&pd_a3sp>;
0281 status = "disabled";
0282 };
0283
0284 scifa6: serial@e6cc0000 {
0285 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
0286 reg = <0xe6cc0000 0x100>;
0287 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0288 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
0289 clock-names = "fck";
0290 power-domains = <&pd_a3sp>;
0291 status = "disabled";
0292 };
0293
0294 scifa7: serial@e6cd0000 {
0295 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
0296 reg = <0xe6cd0000 0x100>;
0297 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0298 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
0299 clock-names = "fck";
0300 power-domains = <&pd_a3sp>;
0301 status = "disabled";
0302 };
0303
0304 scifb: serial@e6c30000 {
0305 compatible = "renesas,scifb-r8a7740", "renesas,scifb";
0306 reg = <0xe6c30000 0x100>;
0307 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
0308 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
0309 clock-names = "fck";
0310 power-domains = <&pd_a3sp>;
0311 status = "disabled";
0312 };
0313
0314 pfc: pinctrl@e6050000 {
0315 compatible = "renesas,pfc-r8a7740";
0316 reg = <0xe6050000 0x8000>,
0317 <0xe605800c 0x20>;
0318 gpio-controller;
0319 #gpio-cells = <2>;
0320 gpio-ranges = <&pfc 0 0 212>;
0321 interrupts-extended =
0322 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
0323 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
0324 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
0325 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
0326 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
0327 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
0328 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
0329 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
0330 power-domains = <&pd_c5>;
0331 };
0332
0333 tpu: pwm@e6600000 {
0334 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
0335 reg = <0xe6600000 0x148>;
0336 clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
0337 power-domains = <&pd_a3sp>;
0338 status = "disabled";
0339 #pwm-cells = <3>;
0340 };
0341
0342 mmcif0: mmc@e6bd0000 {
0343 compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
0344 reg = <0xe6bd0000 0x100>;
0345 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
0346 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0347 clocks = <&mstp3_clks R8A7740_CLK_MMC>;
0348 power-domains = <&pd_a3sp>;
0349 status = "disabled";
0350 };
0351
0352 sdhi0: mmc@e6850000 {
0353 compatible = "renesas,sdhi-r8a7740";
0354 reg = <0xe6850000 0x100>;
0355 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
0356 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
0357 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
0358 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
0359 power-domains = <&pd_a3sp>;
0360 cap-sd-highspeed;
0361 cap-sdio-irq;
0362 status = "disabled";
0363 };
0364
0365 sdhi1: mmc@e6860000 {
0366 compatible = "renesas,sdhi-r8a7740";
0367 reg = <0xe6860000 0x100>;
0368 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
0369 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
0370 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
0371 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
0372 power-domains = <&pd_a3sp>;
0373 cap-sd-highspeed;
0374 cap-sdio-irq;
0375 status = "disabled";
0376 };
0377
0378 sdhi2: mmc@e6870000 {
0379 compatible = "renesas,sdhi-r8a7740";
0380 reg = <0xe6870000 0x100>;
0381 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
0382 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
0383 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
0384 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
0385 power-domains = <&pd_a3sp>;
0386 cap-sd-highspeed;
0387 cap-sdio-irq;
0388 status = "disabled";
0389 };
0390
0391 sh_fsi2: sound@fe1f0000 {
0392 #sound-dai-cells = <1>;
0393 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
0394 reg = <0xfe1f0000 0x400>;
0395 interrupts = <GIC_SPI 9 0x4>;
0396 clocks = <&mstp3_clks R8A7740_CLK_FSI>;
0397 power-domains = <&pd_a4mp>;
0398 status = "disabled";
0399 };
0400
0401 tmu0: timer@fff80000 {
0402 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
0403 reg = <0xfff80000 0x2c>;
0404 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
0405 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
0406 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
0407 clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
0408 clock-names = "fck";
0409 power-domains = <&pd_a4r>;
0410
0411 #renesas,channels = <3>;
0412
0413 status = "disabled";
0414 };
0415
0416 tmu1: timer@fff90000 {
0417 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
0418 reg = <0xfff90000 0x2c>;
0419 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
0420 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
0421 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
0422 clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
0423 clock-names = "fck";
0424 power-domains = <&pd_a4r>;
0425
0426 #renesas,channels = <3>;
0427
0428 status = "disabled";
0429 };
0430
0431 clocks {
0432 #address-cells = <1>;
0433 #size-cells = <1>;
0434 ranges;
0435
0436 /* External root clock */
0437 extalr_clk: extalr {
0438 compatible = "fixed-clock";
0439 #clock-cells = <0>;
0440 clock-frequency = <32768>;
0441 };
0442 extal1_clk: extal1 {
0443 compatible = "fixed-clock";
0444 #clock-cells = <0>;
0445 clock-frequency = <0>;
0446 };
0447 extal2_clk: extal2 {
0448 compatible = "fixed-clock";
0449 #clock-cells = <0>;
0450 clock-frequency = <0>;
0451 };
0452 dv_clk: dv {
0453 compatible = "fixed-clock";
0454 #clock-cells = <0>;
0455 clock-frequency = <27000000>;
0456 };
0457 fmsick_clk: fmsick {
0458 compatible = "fixed-clock";
0459 #clock-cells = <0>;
0460 clock-frequency = <0>;
0461 };
0462 fmsock_clk: fmsock {
0463 compatible = "fixed-clock";
0464 #clock-cells = <0>;
0465 clock-frequency = <0>;
0466 };
0467 fsiack_clk: fsiack {
0468 compatible = "fixed-clock";
0469 #clock-cells = <0>;
0470 clock-frequency = <0>;
0471 };
0472 fsibck_clk: fsibck {
0473 compatible = "fixed-clock";
0474 #clock-cells = <0>;
0475 clock-frequency = <0>;
0476 };
0477
0478 /* Special CPG clocks */
0479 cpg_clocks: cpg_clocks@e6150000 {
0480 compatible = "renesas,r8a7740-cpg-clocks";
0481 reg = <0xe6150000 0x10000>;
0482 clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
0483 #clock-cells = <1>;
0484 clock-output-names = "system", "pllc0", "pllc1",
0485 "pllc2", "r",
0486 "usb24s",
0487 "i", "zg", "b", "m1", "hp",
0488 "hpp", "usbp", "s", "zb", "m3",
0489 "cp";
0490 };
0491
0492 /* Variable factor clocks (DIV6) */
0493 vclk1_clk: vclk1@e6150008 {
0494 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
0495 reg = <0xe6150008 4>;
0496 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
0497 <&cpg_clocks R8A7740_CLK_USB24S>,
0498 <&extal1_div2_clk>, <&extalr_clk>, <0>,
0499 <0>;
0500 #clock-cells = <0>;
0501 };
0502 vclk2_clk: vclk2@e615000c {
0503 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
0504 reg = <0xe615000c 4>;
0505 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
0506 <&cpg_clocks R8A7740_CLK_USB24S>,
0507 <&extal1_div2_clk>, <&extalr_clk>, <0>,
0508 <0>;
0509 #clock-cells = <0>;
0510 };
0511 fmsi_clk: fmsi@e6150010 {
0512 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
0513 reg = <0xe6150010 4>;
0514 clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
0515 #clock-cells = <0>;
0516 };
0517 fmso_clk: fmso@e6150014 {
0518 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
0519 reg = <0xe6150014 4>;
0520 clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
0521 #clock-cells = <0>;
0522 };
0523 fsia_clk: fsia@e6150018 {
0524 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
0525 reg = <0xe6150018 4>;
0526 clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
0527 #clock-cells = <0>;
0528 };
0529 sub_clk: sub@e6150080 {
0530 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
0531 reg = <0xe6150080 4>;
0532 clocks = <&pllc1_div2_clk>,
0533 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
0534 #clock-cells = <0>;
0535 };
0536 spu_clk: spu@e6150084 {
0537 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
0538 reg = <0xe6150084 4>;
0539 clocks = <&pllc1_div2_clk>,
0540 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
0541 #clock-cells = <0>;
0542 };
0543 vou_clk: vou@e6150088 {
0544 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
0545 reg = <0xe6150088 4>;
0546 clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
0547 <0>;
0548 #clock-cells = <0>;
0549 };
0550 stpro_clk: stpro@e615009c {
0551 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
0552 reg = <0xe615009c 4>;
0553 clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
0554 #clock-cells = <0>;
0555 };
0556
0557 /* Fixed factor clocks */
0558 pllc1_div2_clk: pllc1_div2 {
0559 compatible = "fixed-factor-clock";
0560 clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
0561 #clock-cells = <0>;
0562 clock-div = <2>;
0563 clock-mult = <1>;
0564 };
0565 extal1_div2_clk: extal1_div2 {
0566 compatible = "fixed-factor-clock";
0567 clocks = <&extal1_clk>;
0568 #clock-cells = <0>;
0569 clock-div = <2>;
0570 clock-mult = <1>;
0571 };
0572
0573 /* Gate clocks */
0574 subck_clks: subck_clks@e6150080 {
0575 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
0576 reg = <0xe6150080 4>;
0577 clocks = <&sub_clk>, <&sub_clk>;
0578 #clock-cells = <1>;
0579 clock-indices = <
0580 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
0581 >;
0582 clock-output-names =
0583 "subck", "subck2";
0584 };
0585 mstp1_clks: mstp1_clks@e6150134 {
0586 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
0587 reg = <0xe6150134 4>, <0xe6150038 4>;
0588 clocks = <&cpg_clocks R8A7740_CLK_S>,
0589 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
0590 <&cpg_clocks R8A7740_CLK_B>,
0591 <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
0592 <&cpg_clocks R8A7740_CLK_B>;
0593 #clock-cells = <1>;
0594 clock-indices = <
0595 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
0596 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
0597 R8A7740_CLK_LCDC0
0598 >;
0599 clock-output-names =
0600 "ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
0601 "tmu1", "lcdc0";
0602 };
0603 mstp2_clks: mstp2_clks@e6150138 {
0604 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
0605 reg = <0xe6150138 4>, <0xe6150040 4>;
0606 clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
0607 <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
0608 <&cpg_clocks R8A7740_CLK_HP>,
0609 <&cpg_clocks R8A7740_CLK_HP>,
0610 <&cpg_clocks R8A7740_CLK_HP>,
0611 <&sub_clk>, <&sub_clk>, <&sub_clk>,
0612 <&sub_clk>, <&sub_clk>, <&sub_clk>,
0613 <&sub_clk>;
0614 #clock-cells = <1>;
0615 clock-indices = <
0616 R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
0617 R8A7740_CLK_SCIFA7
0618 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
0619 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
0620 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
0621 R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
0622 R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
0623 R8A7740_CLK_SCIFA4
0624 >;
0625 clock-output-names =
0626 "scifa6", "intca",
0627 "scifa7", "dmac1", "dmac2", "dmac3",
0628 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
0629 "scifa2", "scifa3", "scifa4";
0630 };
0631 mstp3_clks: mstp3_clks@e615013c {
0632 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
0633 reg = <0xe615013c 4>, <0xe6150048 4>;
0634 clocks = <&cpg_clocks R8A7740_CLK_R>,
0635 <&cpg_clocks R8A7740_CLK_HP>,
0636 <&sub_clk>,
0637 <&cpg_clocks R8A7740_CLK_HP>,
0638 <&cpg_clocks R8A7740_CLK_HP>,
0639 <&cpg_clocks R8A7740_CLK_HP>,
0640 <&cpg_clocks R8A7740_CLK_HP>,
0641 <&cpg_clocks R8A7740_CLK_HP>,
0642 <&cpg_clocks R8A7740_CLK_HP>;
0643 #clock-cells = <1>;
0644 clock-indices = <
0645 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
0646 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
0647 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
0648 >;
0649 clock-output-names =
0650 "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
0651 "mmc", "gether", "tpu0";
0652 };
0653 mstp4_clks: mstp4_clks@e6150140 {
0654 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
0655 reg = <0xe6150140 4>, <0xe615004c 4>;
0656 clocks = <&cpg_clocks R8A7740_CLK_HP>,
0657 <&cpg_clocks R8A7740_CLK_HP>,
0658 <&cpg_clocks R8A7740_CLK_HP>,
0659 <&cpg_clocks R8A7740_CLK_HP>;
0660 #clock-cells = <1>;
0661 clock-indices = <
0662 R8A7740_CLK_USBH R8A7740_CLK_SDHI2
0663 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
0664 >;
0665 clock-output-names =
0666 "usbhost", "sdhi2", "usbfunc", "usphy";
0667 };
0668 };
0669
0670 sysc: system-controller@e6180000 {
0671 compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
0672 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
0673
0674 pm-domains {
0675 pd_c5: c5 {
0676 #address-cells = <1>;
0677 #size-cells = <0>;
0678 #power-domain-cells = <0>;
0679
0680 pd_a4lc: a4lc@1 {
0681 reg = <1>;
0682 #power-domain-cells = <0>;
0683 };
0684
0685 pd_a4mp: a4mp@2 {
0686 reg = <2>;
0687 #power-domain-cells = <0>;
0688 };
0689
0690 pd_d4: d4@3 {
0691 reg = <3>;
0692 #power-domain-cells = <0>;
0693 };
0694
0695 pd_a4r: a4r@5 {
0696 reg = <5>;
0697 #address-cells = <1>;
0698 #size-cells = <0>;
0699 #power-domain-cells = <0>;
0700
0701 pd_a3rv: a3rv@6 {
0702 reg = <6>;
0703 #power-domain-cells = <0>;
0704 };
0705 };
0706
0707 pd_a4s: a4s@10 {
0708 reg = <10>;
0709 #address-cells = <1>;
0710 #size-cells = <0>;
0711 #power-domain-cells = <0>;
0712
0713 pd_a3sp: a3sp@11 {
0714 reg = <11>;
0715 #power-domain-cells = <0>;
0716 };
0717
0718 pd_a3sm: a3sm@12 {
0719 reg = <12>;
0720 #power-domain-cells = <0>;
0721 };
0722
0723 pd_a3sg: a3sg@13 {
0724 reg = <13>;
0725 #power-domain-cells = <0>;
0726 };
0727 };
0728
0729 pd_a4su: a4su@20 {
0730 reg = <20>;
0731 #power-domain-cells = <0>;
0732 };
0733 };
0734 };
0735 };
0736 };
