0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for the r8a73a4 SoC
0004 *
0005 * Copyright (C) 2013 Renesas Solutions Corp.
0006 * Copyright (C) 2013 Magnus Damm
0007 */
0008
0009 #include <dt-bindings/clock/r8a73a4-clock.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/interrupt-controller/irq.h>
0012
0013 / {
0014 compatible = "renesas,r8a73a4";
0015 interrupt-parent = <&gic>;
0016 #address-cells = <2>;
0017 #size-cells = <2>;
0018
0019 cpus {
0020 #address-cells = <1>;
0021 #size-cells = <0>;
0022
0023 cpu0: cpu@0 {
0024 device_type = "cpu";
0025 compatible = "arm,cortex-a15";
0026 reg = <0>;
0027 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
0028 clock-frequency = <1500000000>;
0029 power-domains = <&pd_a2sl>;
0030 next-level-cache = <&L2_CA15>;
0031 };
0032
0033 L2_CA15: cache-controller-0 {
0034 compatible = "cache";
0035 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
0036 power-domains = <&pd_a3sm>;
0037 cache-unified;
0038 cache-level = <2>;
0039 };
0040
0041 L2_CA7: cache-controller-1 {
0042 compatible = "cache";
0043 clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
0044 power-domains = <&pd_a3km>;
0045 cache-unified;
0046 cache-level = <2>;
0047 };
0048 };
0049
0050 ptm {
0051 compatible = "arm,coresight-etm3x";
0052 power-domains = <&pd_d4>;
0053 };
0054
0055 timer {
0056 compatible = "arm,armv7-timer";
0057 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0058 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0059 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0060 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
0061 };
0062
0063 dbsc1: memory-controller@e6790000 {
0064 compatible = "renesas,dbsc-r8a73a4";
0065 reg = <0 0xe6790000 0 0x10000>;
0066 power-domains = <&pd_a3bc>;
0067 };
0068
0069 dbsc2: memory-controller@e67a0000 {
0070 compatible = "renesas,dbsc-r8a73a4";
0071 reg = <0 0xe67a0000 0 0x10000>;
0072 power-domains = <&pd_a3bc>;
0073 };
0074
0075 i2c5: i2c@e60b0000 {
0076 #address-cells = <1>;
0077 #size-cells = <0>;
0078 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
0079 reg = <0 0xe60b0000 0 0x428>;
0080 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
0081 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
0082 power-domains = <&pd_a3sp>;
0083
0084 status = "disabled";
0085 };
0086
0087 cmt1: timer@e6130000 {
0088 compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
0089 reg = <0 0xe6130000 0 0x1004>;
0090 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0091 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
0092 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
0093 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
0094 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
0095 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
0096 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
0097 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
0098 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
0099 clock-names = "fck";
0100 power-domains = <&pd_c5>;
0101 status = "disabled";
0102 };
0103
0104 irqc0: interrupt-controller@e61c0000 {
0105 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
0106 #interrupt-cells = <2>;
0107 interrupt-controller;
0108 reg = <0 0xe61c0000 0 0x200>;
0109 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0110 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0111 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0112 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0113 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0114 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0115 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0116 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0117 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0118 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0119 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0120 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0121 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0122 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0123 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0124 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0125 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
0126 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
0127 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0128 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0129 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
0130 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
0131 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
0132 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
0133 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
0134 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
0135 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
0136 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
0137 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
0138 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
0139 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
0140 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0141 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
0142 power-domains = <&pd_c4>;
0143 };
0144
0145 irqc1: interrupt-controller@e61c0200 {
0146 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
0147 #interrupt-cells = <2>;
0148 interrupt-controller;
0149 reg = <0 0xe61c0200 0 0x200>;
0150 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
0151 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0152 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
0153 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
0154 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
0155 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
0156 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
0157 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
0158 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
0159 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
0160 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
0161 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
0162 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
0163 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
0164 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
0165 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
0166 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
0167 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
0168 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
0169 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
0170 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
0171 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
0172 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
0173 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
0174 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
0175 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0176 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
0177 power-domains = <&pd_c4>;
0178 };
0179
0180 pfc: pinctrl@e6050000 {
0181 compatible = "renesas,pfc-r8a73a4";
0182 reg = <0 0xe6050000 0 0x9000>;
0183 gpio-controller;
0184 #gpio-cells = <2>;
0185 gpio-ranges =
0186 <&pfc 0 0 31>, <&pfc 32 32 9>,
0187 <&pfc 64 64 22>, <&pfc 96 96 31>,
0188 <&pfc 128 128 7>, <&pfc 160 160 19>,
0189 <&pfc 192 192 31>, <&pfc 224 224 27>,
0190 <&pfc 256 256 28>, <&pfc 288 288 21>,
0191 <&pfc 320 320 10>;
0192 interrupts-extended =
0193 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
0194 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
0195 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
0196 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
0197 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
0198 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
0199 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
0200 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
0201 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
0202 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
0203 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
0204 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
0205 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
0206 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
0207 <&irqc1 24 0>, <&irqc1 25 0>;
0208 power-domains = <&pd_c5>;
0209 };
0210
0211 thermal@e61f0000 {
0212 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
0213 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
0214 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
0215 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0216 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
0217 power-domains = <&pd_c5>;
0218 };
0219
0220 i2c0: i2c@e6500000 {
0221 #address-cells = <1>;
0222 #size-cells = <0>;
0223 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
0224 reg = <0 0xe6500000 0 0x428>;
0225 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
0226 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
0227 power-domains = <&pd_a3sp>;
0228 status = "disabled";
0229 };
0230
0231 i2c1: i2c@e6510000 {
0232 #address-cells = <1>;
0233 #size-cells = <0>;
0234 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
0235 reg = <0 0xe6510000 0 0x428>;
0236 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
0237 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
0238 power-domains = <&pd_a3sp>;
0239 status = "disabled";
0240 };
0241
0242 i2c2: i2c@e6520000 {
0243 #address-cells = <1>;
0244 #size-cells = <0>;
0245 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
0246 reg = <0 0xe6520000 0 0x428>;
0247 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
0248 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
0249 power-domains = <&pd_a3sp>;
0250 status = "disabled";
0251 };
0252
0253 i2c3: i2c@e6530000 {
0254 #address-cells = <1>;
0255 #size-cells = <0>;
0256 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
0257 reg = <0 0xe6530000 0 0x428>;
0258 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
0259 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
0260 power-domains = <&pd_a3sp>;
0261 status = "disabled";
0262 };
0263
0264 i2c4: i2c@e6540000 {
0265 #address-cells = <1>;
0266 #size-cells = <0>;
0267 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
0268 reg = <0 0xe6540000 0 0x428>;
0269 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
0270 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
0271 power-domains = <&pd_a3sp>;
0272 status = "disabled";
0273 };
0274
0275 i2c6: i2c@e6550000 {
0276 #address-cells = <1>;
0277 #size-cells = <0>;
0278 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
0279 reg = <0 0xe6550000 0 0x428>;
0280 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
0281 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
0282 power-domains = <&pd_a3sp>;
0283 status = "disabled";
0284 };
0285
0286 i2c7: i2c@e6560000 {
0287 #address-cells = <1>;
0288 #size-cells = <0>;
0289 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
0290 reg = <0 0xe6560000 0 0x428>;
0291 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
0292 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
0293 power-domains = <&pd_a3sp>;
0294 status = "disabled";
0295 };
0296
0297 i2c8: i2c@e6570000 {
0298 #address-cells = <1>;
0299 #size-cells = <0>;
0300 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
0301 reg = <0 0xe6570000 0 0x428>;
0302 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
0303 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
0304 power-domains = <&pd_a3sp>;
0305 status = "disabled";
0306 };
0307
0308 scifb0: serial@e6c20000 {
0309 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
0310 reg = <0 0xe6c20000 0 0x100>;
0311 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
0312 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
0313 clock-names = "fck";
0314 power-domains = <&pd_a3sp>;
0315 status = "disabled";
0316 };
0317
0318 scifb1: serial@e6c30000 {
0319 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
0320 reg = <0 0xe6c30000 0 0x100>;
0321 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
0322 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
0323 clock-names = "fck";
0324 power-domains = <&pd_a3sp>;
0325 status = "disabled";
0326 };
0327
0328 scifa0: serial@e6c40000 {
0329 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
0330 reg = <0 0xe6c40000 0 0x100>;
0331 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
0332 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
0333 clock-names = "fck";
0334 power-domains = <&pd_a3sp>;
0335 status = "disabled";
0336 };
0337
0338 scifa1: serial@e6c50000 {
0339 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
0340 reg = <0 0xe6c50000 0 0x100>;
0341 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
0342 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
0343 clock-names = "fck";
0344 power-domains = <&pd_a3sp>;
0345 status = "disabled";
0346 };
0347
0348 scifb2: serial@e6ce0000 {
0349 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
0350 reg = <0 0xe6ce0000 0 0x100>;
0351 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
0352 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
0353 clock-names = "fck";
0354 power-domains = <&pd_a3sp>;
0355 status = "disabled";
0356 };
0357
0358 scifb3: serial@e6cf0000 {
0359 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
0360 reg = <0 0xe6cf0000 0 0x100>;
0361 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
0362 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
0363 clock-names = "fck";
0364 power-domains = <&pd_c4>;
0365 status = "disabled";
0366 };
0367
0368 sdhi0: mmc@ee100000 {
0369 compatible = "renesas,sdhi-r8a73a4";
0370 reg = <0 0xee100000 0 0x100>;
0371 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
0372 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
0373 power-domains = <&pd_a3sp>;
0374 cap-sd-highspeed;
0375 status = "disabled";
0376 };
0377
0378 sdhi1: mmc@ee120000 {
0379 compatible = "renesas,sdhi-r8a73a4";
0380 reg = <0 0xee120000 0 0x100>;
0381 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
0382 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
0383 power-domains = <&pd_a3sp>;
0384 cap-sd-highspeed;
0385 status = "disabled";
0386 };
0387
0388 sdhi2: mmc@ee140000 {
0389 compatible = "renesas,sdhi-r8a73a4";
0390 reg = <0 0xee140000 0 0x100>;
0391 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
0392 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
0393 power-domains = <&pd_a3sp>;
0394 cap-sd-highspeed;
0395 status = "disabled";
0396 };
0397
0398 mmcif0: mmc@ee200000 {
0399 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
0400 reg = <0 0xee200000 0 0x80>;
0401 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
0402 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
0403 power-domains = <&pd_a3sp>;
0404 reg-io-width = <4>;
0405 status = "disabled";
0406 };
0407
0408 mmcif1: mmc@ee220000 {
0409 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
0410 reg = <0 0xee220000 0 0x80>;
0411 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
0412 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
0413 power-domains = <&pd_a3sp>;
0414 reg-io-width = <4>;
0415 status = "disabled";
0416 };
0417
0418 gic: interrupt-controller@f1001000 {
0419 compatible = "arm,gic-400";
0420 #interrupt-cells = <3>;
0421 #address-cells = <0>;
0422 interrupt-controller;
0423 reg = <0 0xf1001000 0 0x1000>,
0424 <0 0xf1002000 0 0x2000>,
0425 <0 0xf1004000 0 0x2000>,
0426 <0 0xf1006000 0 0x2000>;
0427 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
0428 clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
0429 clock-names = "clk";
0430 power-domains = <&pd_c4>;
0431 };
0432
0433 bsc: bus@fec10000 {
0434 compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
0435 "simple-pm-bus";
0436 #address-cells = <1>;
0437 #size-cells = <1>;
0438 ranges = <0 0 0 0x20000000>;
0439 reg = <0 0xfec10000 0 0x400>;
0440 clocks = <&zb_clk>;
0441 power-domains = <&pd_c4>;
0442 };
0443
0444 clocks {
0445 #address-cells = <2>;
0446 #size-cells = <2>;
0447 ranges;
0448
0449 /* External root clocks */
0450 extalr_clk: extalr {
0451 compatible = "fixed-clock";
0452 #clock-cells = <0>;
0453 clock-frequency = <32768>;
0454 };
0455 extal1_clk: extal1 {
0456 compatible = "fixed-clock";
0457 #clock-cells = <0>;
0458 clock-frequency = <25000000>;
0459 };
0460 extal2_clk: extal2 {
0461 compatible = "fixed-clock";
0462 #clock-cells = <0>;
0463 clock-frequency = <48000000>;
0464 };
0465 fsiack_clk: fsiack {
0466 compatible = "fixed-clock";
0467 #clock-cells = <0>;
0468 /* This value must be overridden by the board. */
0469 clock-frequency = <0>;
0470 };
0471 fsibck_clk: fsibck {
0472 compatible = "fixed-clock";
0473 #clock-cells = <0>;
0474 /* This value must be overridden by the board. */
0475 clock-frequency = <0>;
0476 };
0477
0478 /* Special CPG clocks */
0479 cpg_clocks: cpg_clocks@e6150000 {
0480 compatible = "renesas,r8a73a4-cpg-clocks";
0481 reg = <0 0xe6150000 0 0x10000>;
0482 clocks = <&extal1_clk>, <&extal2_clk>;
0483 #clock-cells = <1>;
0484 clock-output-names = "main", "pll0", "pll1", "pll2",
0485 "pll2s", "pll2h", "z", "z2",
0486 "i", "m3", "b", "m1", "m2",
0487 "zx", "zs", "hp";
0488 };
0489
0490 /* Variable factor clocks (DIV6) */
0491 zb_clk: zb_clk@e6150010 {
0492 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
0493 reg = <0 0xe6150010 0 4>;
0494 clocks = <&pll1_div2_clk>, <0>,
0495 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
0496 #clock-cells = <0>;
0497 clock-output-names = "zb";
0498 };
0499 sdhi0_clk: sdhi0ck@e6150074 {
0500 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
0501 reg = <0 0xe6150074 0 4>;
0502 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
0503 <0>, <&extal2_clk>;
0504 #clock-cells = <0>;
0505 };
0506 sdhi1_clk: sdhi1ck@e6150078 {
0507 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
0508 reg = <0 0xe6150078 0 4>;
0509 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
0510 <0>, <&extal2_clk>;
0511 #clock-cells = <0>;
0512 };
0513 sdhi2_clk: sdhi2ck@e615007c {
0514 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
0515 reg = <0 0xe615007c 0 4>;
0516 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
0517 <0>, <&extal2_clk>;
0518 #clock-cells = <0>;
0519 };
0520 mmc0_clk: mmc0@e6150240 {
0521 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
0522 reg = <0 0xe6150240 0 4>;
0523 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
0524 <0>, <&extal2_clk>;
0525 #clock-cells = <0>;
0526 };
0527 mmc1_clk: mmc1@e6150244 {
0528 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
0529 reg = <0 0xe6150244 0 4>;
0530 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
0531 <0>, <&extal2_clk>;
0532 #clock-cells = <0>;
0533 };
0534 vclk1_clk: vclk1@e6150008 {
0535 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
0536 reg = <0 0xe6150008 0 4>;
0537 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
0538 <0>, <&extal2_clk>, <&main_div2_clk>,
0539 <&extalr_clk>, <0>, <0>;
0540 #clock-cells = <0>;
0541 };
0542 vclk2_clk: vclk2@e615000c {
0543 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
0544 reg = <0 0xe615000c 0 4>;
0545 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
0546 <0>, <&extal2_clk>, <&main_div2_clk>,
0547 <&extalr_clk>, <0>, <0>;
0548 #clock-cells = <0>;
0549 };
0550 vclk3_clk: vclk3@e615001c {
0551 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
0552 reg = <0 0xe615001c 0 4>;
0553 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
0554 <0>, <&extal2_clk>, <&main_div2_clk>,
0555 <&extalr_clk>, <0>, <0>;
0556 #clock-cells = <0>;
0557 };
0558 vclk4_clk: vclk4@e6150014 {
0559 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
0560 reg = <0 0xe6150014 0 4>;
0561 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
0562 <0>, <&extal2_clk>, <&main_div2_clk>,
0563 <&extalr_clk>, <0>, <0>;
0564 #clock-cells = <0>;
0565 };
0566 vclk5_clk: vclk5@e6150034 {
0567 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
0568 reg = <0 0xe6150034 0 4>;
0569 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
0570 <0>, <&extal2_clk>, <&main_div2_clk>,
0571 <&extalr_clk>, <0>, <0>;
0572 #clock-cells = <0>;
0573 };
0574 fsia_clk: fsia@e6150018 {
0575 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
0576 reg = <0 0xe6150018 0 4>;
0577 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
0578 <&fsiack_clk>, <0>;
0579 #clock-cells = <0>;
0580 };
0581 fsib_clk: fsib@e6150090 {
0582 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
0583 reg = <0 0xe6150090 0 4>;
0584 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
0585 <&fsibck_clk>, <0>;
0586 #clock-cells = <0>;
0587 };
0588 mp_clk: mp@e6150080 {
0589 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
0590 reg = <0 0xe6150080 0 4>;
0591 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
0592 <&extal2_clk>, <&extal2_clk>;
0593 #clock-cells = <0>;
0594 };
0595 m4_clk: m4@e6150098 {
0596 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
0597 reg = <0 0xe6150098 0 4>;
0598 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
0599 #clock-cells = <0>;
0600 };
0601 hsi_clk: hsi@e615026c {
0602 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
0603 reg = <0 0xe615026c 0 4>;
0604 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
0605 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
0606 #clock-cells = <0>;
0607 };
0608 spuv_clk: spuv@e6150094 {
0609 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
0610 reg = <0 0xe6150094 0 4>;
0611 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
0612 <&extal2_clk>, <&extal2_clk>;
0613 #clock-cells = <0>;
0614 };
0615
0616 /* Fixed factor clocks */
0617 main_div2_clk: main_div2 {
0618 compatible = "fixed-factor-clock";
0619 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
0620 #clock-cells = <0>;
0621 clock-div = <2>;
0622 clock-mult = <1>;
0623 };
0624 pll0_div2_clk: pll0_div2 {
0625 compatible = "fixed-factor-clock";
0626 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
0627 #clock-cells = <0>;
0628 clock-div = <2>;
0629 clock-mult = <1>;
0630 };
0631 pll1_div2_clk: pll1_div2 {
0632 compatible = "fixed-factor-clock";
0633 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
0634 #clock-cells = <0>;
0635 clock-div = <2>;
0636 clock-mult = <1>;
0637 };
0638 extal1_div2_clk: extal1_div2 {
0639 compatible = "fixed-factor-clock";
0640 clocks = <&extal1_clk>;
0641 #clock-cells = <0>;
0642 clock-div = <2>;
0643 clock-mult = <1>;
0644 };
0645
0646 /* Gate clocks */
0647 mstp2_clks: mstp2_clks@e6150138 {
0648 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
0649 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
0650 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
0651 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
0652 #clock-cells = <1>;
0653 clock-indices = <
0654 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
0655 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
0656 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
0657 R8A73A4_CLK_DMAC
0658 >;
0659 clock-output-names =
0660 "scifa0", "scifa1", "scifb0", "scifb1",
0661 "scifb2", "scifb3", "dmac";
0662 };
0663 mstp3_clks: mstp3_clks@e615013c {
0664 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
0665 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
0666 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
0667 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
0668 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
0669 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
0670 R8A73A4_CLK_HP>, <&cpg_clocks
0671 R8A73A4_CLK_HP>, <&extalr_clk>;
0672 #clock-cells = <1>;
0673 clock-indices = <
0674 R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
0675 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
0676 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
0677 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
0678 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
0679 R8A73A4_CLK_CMT1
0680 >;
0681 clock-output-names =
0682 "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
0683 "mmcif0", "iic6", "iic7", "iic0", "iic1",
0684 "cmt1";
0685 };
0686 mstp4_clks: mstp4_clks@e6150140 {
0687 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
0688 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
0689 clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
0690 <&main_div2_clk>,
0691 <&cpg_clocks R8A73A4_CLK_HP>,
0692 <&cpg_clocks R8A73A4_CLK_HP>;
0693 #clock-cells = <1>;
0694 clock-indices = <
0695 R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS
0696 R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
0697 R8A73A4_CLK_IIC3
0698 >;
0699 clock-output-names =
0700 "irqc", "intc-sys", "iic5", "iic4", "iic3";
0701 };
0702 mstp5_clks: mstp5_clks@e6150144 {
0703 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
0704 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
0705 clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
0706 #clock-cells = <1>;
0707 clock-indices = <
0708 R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
0709 >;
0710 clock-output-names =
0711 "thermal", "iic8";
0712 };
0713 };
0714
0715 prr: chipid@ff000044 {
0716 compatible = "renesas,prr";
0717 reg = <0 0xff000044 0 4>;
0718 };
0719
0720 sysc: system-controller@e6180000 {
0721 compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
0722 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
0723
0724 pm-domains {
0725 pd_c5: c5 {
0726 #address-cells = <1>;
0727 #size-cells = <0>;
0728 #power-domain-cells = <0>;
0729
0730 pd_c4: c4@0 {
0731 reg = <0>;
0732 #address-cells = <1>;
0733 #size-cells = <0>;
0734 #power-domain-cells = <0>;
0735
0736 pd_a3sg: a3sg@16 {
0737 reg = <16>;
0738 #power-domain-cells = <0>;
0739 };
0740
0741 pd_a3ex: a3ex@17 {
0742 reg = <17>;
0743 #power-domain-cells = <0>;
0744 };
0745
0746 pd_a3sp: a3sp@18 {
0747 reg = <18>;
0748 #address-cells = <1>;
0749 #size-cells = <0>;
0750 #power-domain-cells = <0>;
0751
0752 pd_a2us: a2us@19 {
0753 reg = <19>;
0754 #power-domain-cells = <0>;
0755 };
0756 };
0757
0758 pd_a3sm: a3sm@20 {
0759 reg = <20>;
0760 #address-cells = <1>;
0761 #size-cells = <0>;
0762 #power-domain-cells = <0>;
0763
0764 pd_a2sl: a2sl@21 {
0765 reg = <21>;
0766 #power-domain-cells = <0>;
0767 };
0768 };
0769
0770 pd_a3km: a3km@22 {
0771 reg = <22>;
0772 #address-cells = <1>;
0773 #size-cells = <0>;
0774 #power-domain-cells = <0>;
0775
0776 pd_a2kl: a2kl@23 {
0777 reg = <23>;
0778 #power-domain-cells = <0>;
0779 };
0780 };
0781 };
0782
0783 pd_c4ma: c4ma@1 {
0784 reg = <1>;
0785 #power-domain-cells = <0>;
0786 };
0787
0788 pd_c4cl: c4cl@2 {
0789 reg = <2>;
0790 #power-domain-cells = <0>;
0791 };
0792
0793 pd_d4: d4@3 {
0794 reg = <3>;
0795 #power-domain-cells = <0>;
0796 };
0797
0798 pd_a4bc: a4bc@4 {
0799 reg = <4>;
0800 #address-cells = <1>;
0801 #size-cells = <0>;
0802 #power-domain-cells = <0>;
0803
0804 pd_a3bc: a3bc@5 {
0805 reg = <5>;
0806 #power-domain-cells = <0>;
0807 };
0808 };
0809
0810 pd_a4l: a4l@6 {
0811 reg = <6>;
0812 #power-domain-cells = <0>;
0813 };
0814
0815 pd_a4lc: a4lc@7 {
0816 reg = <7>;
0817 #power-domain-cells = <0>;
0818 };
0819
0820 pd_a4mp: a4mp@8 {
0821 reg = <8>;
0822 #address-cells = <1>;
0823 #size-cells = <0>;
0824 #power-domain-cells = <0>;
0825
0826 pd_a3mp: a3mp@9 {
0827 reg = <9>;
0828 #power-domain-cells = <0>;
0829 };
0830
0831 pd_a3vc: a3vc@10 {
0832 reg = <10>;
0833 #power-domain-cells = <0>;
0834 };
0835 };
0836
0837 pd_a4sf: a4sf@11 {
0838 reg = <11>;
0839 #power-domain-cells = <0>;
0840 };
0841
0842 pd_a3r: a3r@12 {
0843 reg = <12>;
0844 #address-cells = <1>;
0845 #size-cells = <0>;
0846 #power-domain-cells = <0>;
0847
0848 pd_a2rv: a2rv@13 {
0849 reg = <13>;
0850 #power-domain-cells = <0>;
0851 };
0852
0853 pd_a2is: a2is@14 {
0854 reg = <14>;
0855 #power-domain-cells = <0>;
0856 };
0857 };
0858 };
0859 };
0860 };
0861 };
