0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for the r7s72100 SoC
0004 *
0005 * Copyright (C) 2013-14 Renesas Solutions Corp.
0006 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
0007 */
0008
0009 #include <dt-bindings/clock/r7s72100-clock.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/interrupt-controller/irq.h>
0012
0013 / {
0014 compatible = "renesas,r7s72100";
0015 #address-cells = <1>;
0016 #size-cells = <1>;
0017
0018 aliases {
0019 i2c0 = &i2c0;
0020 i2c1 = &i2c1;
0021 i2c2 = &i2c2;
0022 i2c3 = &i2c3;
0023 spi0 = &spi0;
0024 spi1 = &spi1;
0025 spi2 = &spi2;
0026 spi3 = &spi3;
0027 spi4 = &spi4;
0028 };
0029
0030 /* Fixed factor clocks */
0031 b_clk: b {
0032 #clock-cells = <0>;
0033 compatible = "fixed-factor-clock";
0034 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
0035 clock-mult = <1>;
0036 clock-div = <3>;
0037 };
0038
0039 cpus {
0040 #address-cells = <1>;
0041 #size-cells = <0>;
0042
0043 cpu@0 {
0044 device_type = "cpu";
0045 compatible = "arm,cortex-a9";
0046 reg = <0>;
0047 clock-frequency = <400000000>;
0048 clocks = <&cpg_clocks R7S72100_CLK_I>;
0049 next-level-cache = <&L2>;
0050 };
0051 };
0052
0053 /* External clocks */
0054 extal_clk: extal {
0055 #clock-cells = <0>;
0056 compatible = "fixed-clock";
0057 /* If clk present, value must be set by board */
0058 clock-frequency = <0>;
0059 };
0060
0061 p0_clk: p0 {
0062 #clock-cells = <0>;
0063 compatible = "fixed-factor-clock";
0064 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
0065 clock-mult = <1>;
0066 clock-div = <12>;
0067 };
0068
0069 p1_clk: p1 {
0070 #clock-cells = <0>;
0071 compatible = "fixed-factor-clock";
0072 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
0073 clock-mult = <1>;
0074 clock-div = <6>;
0075 };
0076
0077 pmu {
0078 compatible = "arm,cortex-a9-pmu";
0079 interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
0080 };
0081
0082 rtc_x1_clk: rtc_x1 {
0083 #clock-cells = <0>;
0084 compatible = "fixed-clock";
0085 /* If clk present, value must be set by board to 32678 */
0086 clock-frequency = <0>;
0087 };
0088
0089 rtc_x3_clk: rtc_x3 {
0090 #clock-cells = <0>;
0091 compatible = "fixed-clock";
0092 /* If clk present, value must be set by board to 4000000 */
0093 clock-frequency = <0>;
0094 };
0095
0096 soc {
0097 compatible = "simple-bus";
0098 interrupt-parent = <&gic>;
0099
0100 #address-cells = <1>;
0101 #size-cells = <1>;
0102 ranges;
0103
0104 L2: cache-controller@3ffff000 {
0105 compatible = "arm,pl310-cache";
0106 reg = <0x3ffff000 0x1000>;
0107 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0108 arm,early-bresp-disable;
0109 arm,full-line-zero-disable;
0110 cache-unified;
0111 cache-level = <2>;
0112 };
0113
0114 scif0: serial@e8007000 {
0115 compatible = "renesas,scif-r7s72100", "renesas,scif";
0116 reg = <0xe8007000 64>;
0117 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
0118 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
0119 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
0120 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
0121 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
0122 clock-names = "fck";
0123 power-domains = <&cpg_clocks>;
0124 status = "disabled";
0125 };
0126
0127 scif1: serial@e8007800 {
0128 compatible = "renesas,scif-r7s72100", "renesas,scif";
0129 reg = <0xe8007800 64>;
0130 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
0131 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
0132 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
0133 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
0134 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
0135 clock-names = "fck";
0136 power-domains = <&cpg_clocks>;
0137 status = "disabled";
0138 };
0139
0140 scif2: serial@e8008000 {
0141 compatible = "renesas,scif-r7s72100", "renesas,scif";
0142 reg = <0xe8008000 64>;
0143 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
0144 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
0145 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
0146 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
0147 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
0148 clock-names = "fck";
0149 power-domains = <&cpg_clocks>;
0150 status = "disabled";
0151 };
0152
0153 scif3: serial@e8008800 {
0154 compatible = "renesas,scif-r7s72100", "renesas,scif";
0155 reg = <0xe8008800 64>;
0156 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
0157 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
0158 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
0159 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
0160 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
0161 clock-names = "fck";
0162 power-domains = <&cpg_clocks>;
0163 status = "disabled";
0164 };
0165
0166 scif4: serial@e8009000 {
0167 compatible = "renesas,scif-r7s72100", "renesas,scif";
0168 reg = <0xe8009000 64>;
0169 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
0170 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
0171 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
0172 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
0173 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
0174 clock-names = "fck";
0175 power-domains = <&cpg_clocks>;
0176 status = "disabled";
0177 };
0178
0179 scif5: serial@e8009800 {
0180 compatible = "renesas,scif-r7s72100", "renesas,scif";
0181 reg = <0xe8009800 64>;
0182 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
0183 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
0184 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
0185 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
0186 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
0187 clock-names = "fck";
0188 power-domains = <&cpg_clocks>;
0189 status = "disabled";
0190 };
0191
0192 scif6: serial@e800a000 {
0193 compatible = "renesas,scif-r7s72100", "renesas,scif";
0194 reg = <0xe800a000 64>;
0195 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
0196 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
0197 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
0198 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
0199 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
0200 clock-names = "fck";
0201 power-domains = <&cpg_clocks>;
0202 status = "disabled";
0203 };
0204
0205 scif7: serial@e800a800 {
0206 compatible = "renesas,scif-r7s72100", "renesas,scif";
0207 reg = <0xe800a800 64>;
0208 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
0209 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
0210 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
0211 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
0212 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
0213 clock-names = "fck";
0214 power-domains = <&cpg_clocks>;
0215 status = "disabled";
0216 };
0217
0218 spi0: spi@e800c800 {
0219 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
0220 reg = <0xe800c800 0x24>;
0221 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
0222 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
0223 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
0224 interrupt-names = "error", "rx", "tx";
0225 clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
0226 power-domains = <&cpg_clocks>;
0227 num-cs = <1>;
0228 #address-cells = <1>;
0229 #size-cells = <0>;
0230 status = "disabled";
0231 };
0232
0233 spi1: spi@e800d000 {
0234 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
0235 reg = <0xe800d000 0x24>;
0236 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
0237 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
0238 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
0239 interrupt-names = "error", "rx", "tx";
0240 clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
0241 power-domains = <&cpg_clocks>;
0242 num-cs = <1>;
0243 #address-cells = <1>;
0244 #size-cells = <0>;
0245 status = "disabled";
0246 };
0247
0248 spi2: spi@e800d800 {
0249 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
0250 reg = <0xe800d800 0x24>;
0251 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
0252 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
0253 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
0254 interrupt-names = "error", "rx", "tx";
0255 clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
0256 power-domains = <&cpg_clocks>;
0257 num-cs = <1>;
0258 #address-cells = <1>;
0259 #size-cells = <0>;
0260 status = "disabled";
0261 };
0262
0263 spi3: spi@e800e000 {
0264 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
0265 reg = <0xe800e000 0x24>;
0266 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
0267 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
0268 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
0269 interrupt-names = "error", "rx", "tx";
0270 clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
0271 power-domains = <&cpg_clocks>;
0272 num-cs = <1>;
0273 #address-cells = <1>;
0274 #size-cells = <0>;
0275 status = "disabled";
0276 };
0277
0278 spi4: spi@e800e800 {
0279 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
0280 reg = <0xe800e800 0x24>;
0281 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
0282 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
0283 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
0284 interrupt-names = "error", "rx", "tx";
0285 clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
0286 power-domains = <&cpg_clocks>;
0287 num-cs = <1>;
0288 #address-cells = <1>;
0289 #size-cells = <0>;
0290 status = "disabled";
0291 };
0292
0293 usbhs0: usb@e8010000 {
0294 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
0295 reg = <0xe8010000 0x1a0>;
0296 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
0297 clocks = <&mstp7_clks R7S72100_CLK_USB0>;
0298 renesas,buswait = <4>;
0299 power-domains = <&cpg_clocks>;
0300 status = "disabled";
0301 };
0302
0303 usbhs1: usb@e8207000 {
0304 compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
0305 reg = <0xe8207000 0x1a0>;
0306 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0307 clocks = <&mstp7_clks R7S72100_CLK_USB1>;
0308 renesas,buswait = <4>;
0309 power-domains = <&cpg_clocks>;
0310 status = "disabled";
0311 };
0312
0313 mmcif: mmc@e804c800 {
0314 compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
0315 reg = <0xe804c800 0x80>;
0316 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
0317 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
0318 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
0319 clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
0320 power-domains = <&cpg_clocks>;
0321 reg-io-width = <4>;
0322 bus-width = <8>;
0323 status = "disabled";
0324 };
0325
0326 sdhi0: mmc@e804e000 {
0327 compatible = "renesas,sdhi-r7s72100";
0328 reg = <0xe804e000 0x100>;
0329 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
0330 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
0331 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
0332
0333 clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
0334 <&mstp12_clks R7S72100_CLK_SDHI01>;
0335 clock-names = "core", "cd";
0336 power-domains = <&cpg_clocks>;
0337 cap-sd-highspeed;
0338 cap-sdio-irq;
0339 status = "disabled";
0340 };
0341
0342 sdhi1: mmc@e804e800 {
0343 compatible = "renesas,sdhi-r7s72100";
0344 reg = <0xe804e800 0x100>;
0345 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
0346 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
0347 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
0348
0349 clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
0350 <&mstp12_clks R7S72100_CLK_SDHI11>;
0351 clock-names = "core", "cd";
0352 power-domains = <&cpg_clocks>;
0353 cap-sd-highspeed;
0354 cap-sdio-irq;
0355 status = "disabled";
0356 };
0357
0358 gic: interrupt-controller@e8201000 {
0359 compatible = "arm,pl390";
0360 #interrupt-cells = <3>;
0361 #address-cells = <0>;
0362 interrupt-controller;
0363 reg = <0xe8201000 0x1000>,
0364 <0xe8202000 0x1000>;
0365 };
0366
0367 ether: ethernet@e8203000 {
0368 compatible = "renesas,ether-r7s72100";
0369 reg = <0xe8203000 0x800>,
0370 <0xe8204800 0x200>;
0371 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
0372 clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
0373 power-domains = <&cpg_clocks>;
0374 phy-mode = "mii";
0375 #address-cells = <1>;
0376 #size-cells = <0>;
0377 status = "disabled";
0378 };
0379
0380 ceu: camera@e8210000 {
0381 reg = <0xe8210000 0x3000>;
0382 compatible = "renesas,r7s72100-ceu";
0383 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
0384 clocks = <&mstp6_clks R7S72100_CLK_CEU>;
0385 power-domains = <&cpg_clocks>;
0386 status = "disabled";
0387 };
0388
0389 wdt: watchdog@fcfe0000 {
0390 compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
0391 reg = <0xfcfe0000 0x6>;
0392 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0393 clocks = <&p0_clk>;
0394 };
0395
0396 /* Special CPG clocks */
0397 cpg_clocks: cpg_clocks@fcfe0000 {
0398 #clock-cells = <1>;
0399 compatible = "renesas,r7s72100-cpg-clocks",
0400 "renesas,rz-cpg-clocks";
0401 reg = <0xfcfe0000 0x18>;
0402 clocks = <&extal_clk>, <&usb_x1_clk>;
0403 clock-output-names = "pll", "i", "g";
0404 #power-domain-cells = <0>;
0405 };
0406
0407 /* MSTP clocks */
0408 mstp3_clks: mstp3_clks@fcfe0420 {
0409 #clock-cells = <1>;
0410 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
0411 reg = <0xfcfe0420 4>;
0412 clocks = <&p0_clk>;
0413 clock-indices = <R7S72100_CLK_MTU2>;
0414 clock-output-names = "mtu2";
0415 };
0416
0417 mstp4_clks: mstp4_clks@fcfe0424 {
0418 #clock-cells = <1>;
0419 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
0420 reg = <0xfcfe0424 4>;
0421 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
0422 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
0423 clock-indices = <
0424 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
0425 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
0426 >;
0427 clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
0428 };
0429
0430 mstp5_clks: mstp5_clks@fcfe0428 {
0431 #clock-cells = <1>;
0432 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
0433 reg = <0xfcfe0428 4>;
0434 clocks = <&p0_clk>, <&p0_clk>;
0435 clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
0436 clock-output-names = "ostm0", "ostm1";
0437 };
0438
0439 mstp6_clks: mstp6_clks@fcfe042c {
0440 #clock-cells = <1>;
0441 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
0442 reg = <0xfcfe042c 4>;
0443 clocks = <&b_clk>, <&p0_clk>;
0444 clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>;
0445 clock-output-names = "ceu", "rtc";
0446 };
0447
0448 mstp7_clks: mstp7_clks@fcfe0430 {
0449 #clock-cells = <1>;
0450 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
0451 reg = <0xfcfe0430 4>;
0452 clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
0453 clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
0454 clock-output-names = "ether", "usb0", "usb1";
0455 };
0456
0457 mstp8_clks: mstp8_clks@fcfe0434 {
0458 #clock-cells = <1>;
0459 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
0460 reg = <0xfcfe0434 4>;
0461 clocks = <&p1_clk>;
0462 clock-indices = <R7S72100_CLK_MMCIF>;
0463 clock-output-names = "mmcif";
0464 };
0465
0466 mstp9_clks: mstp9_clks@fcfe0438 {
0467 #clock-cells = <1>;
0468 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
0469 reg = <0xfcfe0438 4>;
0470 clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>;
0471 clock-indices = <
0472 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
0473 R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1
0474 >;
0475 clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1";
0476 };
0477
0478 mstp10_clks: mstp10_clks@fcfe043c {
0479 #clock-cells = <1>;
0480 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
0481 reg = <0xfcfe043c 4>;
0482 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
0483 <&p1_clk>;
0484 clock-indices = <
0485 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
0486 R7S72100_CLK_SPI4
0487 >;
0488 clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
0489 };
0490 mstp12_clks: mstp12_clks@fcfe0444 {
0491 #clock-cells = <1>;
0492 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
0493 reg = <0xfcfe0444 4>;
0494 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
0495 clock-indices = <
0496 R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
0497 R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
0498 >;
0499 clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
0500 };
0501
0502 pinctrl: pinctrl@fcfe3000 {
0503 compatible = "renesas,r7s72100-ports";
0504
0505 reg = <0xfcfe3000 0x4230>;
0506
0507 port0: gpio-0 {
0508 gpio-controller;
0509 #gpio-cells = <2>;
0510 gpio-ranges = <&pinctrl 0 0 6>;
0511 };
0512
0513 port1: gpio-1 {
0514 gpio-controller;
0515 #gpio-cells = <2>;
0516 gpio-ranges = <&pinctrl 0 16 16>;
0517 };
0518
0519 port2: gpio-2 {
0520 gpio-controller;
0521 #gpio-cells = <2>;
0522 gpio-ranges = <&pinctrl 0 32 16>;
0523 };
0524
0525 port3: gpio-3 {
0526 gpio-controller;
0527 #gpio-cells = <2>;
0528 gpio-ranges = <&pinctrl 0 48 16>;
0529 };
0530
0531 port4: gpio-4 {
0532 gpio-controller;
0533 #gpio-cells = <2>;
0534 gpio-ranges = <&pinctrl 0 64 16>;
0535 };
0536
0537 port5: gpio-5 {
0538 gpio-controller;
0539 #gpio-cells = <2>;
0540 gpio-ranges = <&pinctrl 0 80 11>;
0541 };
0542
0543 port6: gpio-6 {
0544 gpio-controller;
0545 #gpio-cells = <2>;
0546 gpio-ranges = <&pinctrl 0 96 16>;
0547 };
0548
0549 port7: gpio-7 {
0550 gpio-controller;
0551 #gpio-cells = <2>;
0552 gpio-ranges = <&pinctrl 0 112 16>;
0553 };
0554
0555 port8: gpio-8 {
0556 gpio-controller;
0557 #gpio-cells = <2>;
0558 gpio-ranges = <&pinctrl 0 128 16>;
0559 };
0560
0561 port9: gpio-9 {
0562 gpio-controller;
0563 #gpio-cells = <2>;
0564 gpio-ranges = <&pinctrl 0 144 8>;
0565 };
0566
0567 port10: gpio-10 {
0568 gpio-controller;
0569 #gpio-cells = <2>;
0570 gpio-ranges = <&pinctrl 0 160 16>;
0571 };
0572
0573 port11: gpio-11 {
0574 gpio-controller;
0575 #gpio-cells = <2>;
0576 gpio-ranges = <&pinctrl 0 176 16>;
0577 };
0578 };
0579
0580 ostm0: timer@fcfec000 {
0581 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
0582 reg = <0xfcfec000 0x30>;
0583 interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
0584 clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
0585 power-domains = <&cpg_clocks>;
0586 status = "disabled";
0587 };
0588
0589 ostm1: timer@fcfec400 {
0590 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
0591 reg = <0xfcfec400 0x30>;
0592 interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
0593 clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
0594 power-domains = <&cpg_clocks>;
0595 status = "disabled";
0596 };
0597
0598 i2c0: i2c@fcfee000 {
0599 #address-cells = <1>;
0600 #size-cells = <0>;
0601 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
0602 reg = <0xfcfee000 0x44>;
0603 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
0604 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
0605 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
0606 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
0607 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
0608 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
0609 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
0610 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
0611 interrupt-names = "tei", "ri", "ti", "spi", "sti",
0612 "naki", "ali", "tmoi";
0613 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
0614 clock-frequency = <100000>;
0615 power-domains = <&cpg_clocks>;
0616 status = "disabled";
0617 };
0618
0619 i2c1: i2c@fcfee400 {
0620 #address-cells = <1>;
0621 #size-cells = <0>;
0622 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
0623 reg = <0xfcfee400 0x44>;
0624 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
0625 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
0626 <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
0627 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
0628 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
0629 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
0630 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
0631 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
0632 interrupt-names = "tei", "ri", "ti", "spi", "sti",
0633 "naki", "ali", "tmoi";
0634 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
0635 clock-frequency = <100000>;
0636 power-domains = <&cpg_clocks>;
0637 status = "disabled";
0638 };
0639
0640 i2c2: i2c@fcfee800 {
0641 #address-cells = <1>;
0642 #size-cells = <0>;
0643 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
0644 reg = <0xfcfee800 0x44>;
0645 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
0646 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
0647 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
0648 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
0649 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
0650 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
0651 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
0652 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
0653 interrupt-names = "tei", "ri", "ti", "spi", "sti",
0654 "naki", "ali", "tmoi";
0655 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
0656 clock-frequency = <100000>;
0657 power-domains = <&cpg_clocks>;
0658 status = "disabled";
0659 };
0660
0661 i2c3: i2c@fcfeec00 {
0662 #address-cells = <1>;
0663 #size-cells = <0>;
0664 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
0665 reg = <0xfcfeec00 0x44>;
0666 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
0667 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
0668 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
0669 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
0670 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
0671 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
0672 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
0673 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
0674 interrupt-names = "tei", "ri", "ti", "spi", "sti",
0675 "naki", "ali", "tmoi";
0676 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
0677 clock-frequency = <100000>;
0678 power-domains = <&cpg_clocks>;
0679 status = "disabled";
0680 };
0681
0682 irqc: interrupt-controller@fcfef800 {
0683 compatible = "renesas,r7s72100-irqc",
0684 "renesas,rza1-irqc";
0685 #interrupt-cells = <2>;
0686 #address-cells = <0>;
0687 interrupt-controller;
0688 reg = <0xfcfef800 0x6>;
0689 interrupt-map =
0690 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0691 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0692 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0693 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0694 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0695 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0696 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0697 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0698 interrupt-map-mask = <7 0>;
0699 };
0700
0701 mtu2: timer@fcff0000 {
0702 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
0703 reg = <0xfcff0000 0x400>;
0704 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0705 interrupt-names = "tgi0a";
0706 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
0707 clock-names = "fck";
0708 power-domains = <&cpg_clocks>;
0709 status = "disabled";
0710 };
0711
0712 rtc: rtc@fcff1000 {
0713 compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
0714 reg = <0xfcff1000 0x2e>;
0715 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
0716 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
0717 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
0718 interrupt-names = "alarm", "period", "carry";
0719 clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
0720 <&rtc_x3_clk>, <&extal_clk>;
0721 clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
0722 power-domains = <&cpg_clocks>;
0723 status = "disabled";
0724 };
0725 };
0726
0727 usb_x1_clk: usb_x1 {
0728 #clock-cells = <0>;
0729 compatible = "fixed-clock";
0730 /* If clk present, value must be set by board */
0731 clock-frequency = <0>;
0732 };
0733 };
