boot/dts/r7s72100-gr-peach.dts

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Device Tree Source for the GR-Peach board
0004  *
0005  * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
0006  * Copyright (C) 2016 Renesas Electronics
0007  */
0008
0009 /dts-v1/;
0010 #include "r7s72100.dtsi"
0011 #include <dt-bindings/gpio/gpio.h>
0012 #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
0013
0014 / {
0015         model = "GR-Peach";
0016         compatible = "renesas,gr-peach", "renesas,r7s72100";
0017
0018         aliases {
0019                 serial0 = &scif2;
0020         };
0021
0022         chosen {
0023                 bootargs = "ignore_loglevel rw root=/dev/mtdblock0";
0024                 stdout-path = "serial0:115200n8";
0025         };
0026
0027         memory@20000000 {
0028                 device_type = "memory";
0029                 reg = <0x20000000 0x00a00000>;
0030         };
0031
0032         lbsc {
0033                 #address-cells = <1>;
0034                 #size-cells = <1>;
0035         };
0036
0037         flash@18000000 {
0038                 compatible = "mtd-rom";
0039                 probe-type = "map_rom";
0040                 reg = <0x18000000 0x00800000>;
0041                 bank-width = <4>;
0042                 device-width = <1>;
0043
0044                 clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>;
0045                 power-domains = <&cpg_clocks>;
0046
0047                 #address-cells = <1>;
0048                 #size-cells = <1>;
0049
0050                 rootfs@600000 {
0051                         label = "rootfs";
0052                         reg = <0x00600000 0x00200000>;
0053                 };
0054         };
0055
0056         leds {
0057                 status = "okay";
0058                 compatible = "gpio-leds";
0059
0060                 led1 {
0061                         gpios = <&port6 12 GPIO_ACTIVE_HIGH>;
0062                 };
0063         };
0064 };
0065
0066 &pinctrl {
0067         scif2_pins: serial2 {
0068                 /* P6_2 as RxD2; P6_3 as TxD2 */
0069                 pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
0070         };
0071
0072         ether_pins: ether {
0073                 /* Ethernet on Ports 1,3,5,10 */
0074                 pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL   */
0075                          <RZA1_PINMUX(3, 0, 2)>,  /* P3_0 = ET_TXCLK  */
0076                          <RZA1_PINMUX(3, 3, 2)>,  /* P3_3 = ET_MDIO   */
0077                          <RZA1_PINMUX(3, 4, 2)>,  /* P3_4 = ET_RXCLK  */
0078                          <RZA1_PINMUX(3, 5, 2)>,  /* P3_5 = ET_RXER   */
0079                          <RZA1_PINMUX(3, 6, 2)>,  /* P3_6 = ET_RXDV   */
0080                          <RZA1_PINMUX(5, 9, 2)>,  /* P5_9 = ET_MDC    */
0081                          <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER  */
0082                          <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN  */
0083                          <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS   */
0084                          <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0  */
0085                          <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1  */
0086                          <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2  */
0087                          <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3  */
0088                          <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0  */
0089                          <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1  */
0090                          <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
0091                          <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
0092         };
0093 };
0094
0095 &extal_clk {
0096         clock-frequency = <13333000>;
0097 };
0098
0099 &usb_x1_clk {
0100         clock-frequency = <48000000>;
0101 };
0102
0103 &mtu2 {
0104         status = "okay";
0105 };
0106
0107 &ostm0 {
0108         status = "okay";
0109 };
0110
0111 &ostm1 {
0112         status = "okay";
0113 };
0114
0115 &scif2 {
0116         pinctrl-names = "default";
0117         pinctrl-0 = <&scif2_pins>;
0118
0119         status = "okay";
0120 };
0121
0122 &ether {
0123         pinctrl-names = "default";
0124         pinctrl-0 = <&ether_pins>;
0125
0126         status = "okay";
0127
0128         renesas,no-ether-link;
0129         phy-handle = <&phy0>;
0130
0131         phy0: ethernet-phy@0 {
0132                 compatible = "ethernet-phy-id0007.c0f0",
0133                              "ethernet-phy-ieee802.3-c22";
0134                 reg = <0>;
0135
0136                 reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
0137                 reset-delay-us = <5>;
0138         };
0139 };