0001 // SPDX-License-Identifier: BSD-3-Clause
0002 /*
0003 * SDX65 SoC device tree source
0004 *
0005 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
0006 *
0007 */
0008
0009 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
0010 #include <dt-bindings/clock/qcom,rpmh.h>
0011 #include <dt-bindings/interrupt-controller/arm-gic.h>
0012 #include <dt-bindings/power/qcom-rpmpd.h>
0013 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
0014
0015 / {
0016 #address-cells = <1>;
0017 #size-cells = <1>;
0018 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
0019 interrupt-parent = <&intc>;
0020
0021 memory {
0022 device_type = "memory";
0023 reg = <0 0>;
0024 };
0025
0026 clocks {
0027 xo_board: xo-board {
0028 compatible = "fixed-clock";
0029 clock-frequency = <76800000>;
0030 clock-output-names = "xo_board";
0031 #clock-cells = <0>;
0032 };
0033
0034 sleep_clk: sleep-clk {
0035 compatible = "fixed-clock";
0036 clock-frequency = <32764>;
0037 clock-output-names = "sleep_clk";
0038 #clock-cells = <0>;
0039 };
0040
0041 nand_clk_dummy: nand-clk-dummy {
0042 compatible = "fixed-clock";
0043 clock-frequency = <32764>;
0044 #clock-cells = <0>;
0045 };
0046 };
0047
0048 cpus {
0049 #address-cells = <1>;
0050 #size-cells = <0>;
0051
0052 cpu0: cpu@0 {
0053 device_type = "cpu";
0054 compatible = "arm,cortex-a7";
0055 reg = <0x0>;
0056 enable-method = "psci";
0057 clocks = <&apcs>;
0058 power-domains = <&rpmhpd SDX65_CX_AO>;
0059 power-domain-names = "rpmhpd";
0060 operating-points-v2 = <&cpu_opp_table>;
0061 };
0062 };
0063
0064 cpu_opp_table: cpu-opp-table {
0065 compatible = "operating-points-v2";
0066 opp-shared;
0067
0068 opp-345600000 {
0069 opp-hz = /bits/ 64 <345600000>;
0070 required-opps = <&rpmhpd_opp_low_svs>;
0071 };
0072
0073 opp-576000000 {
0074 opp-hz = /bits/ 64 <576000000>;
0075 required-opps = <&rpmhpd_opp_svs>;
0076 };
0077
0078 opp-1094400000 {
0079 opp-hz = /bits/ 64 <1094400000>;
0080 required-opps = <&rpmhpd_opp_nom>;
0081 };
0082
0083 opp-1497600000 {
0084 opp-hz = /bits/ 64 <1497600000>;
0085 required-opps = <&rpmhpd_opp_turbo>;
0086 };
0087 };
0088
0089 firmware {
0090 scm {
0091 compatible = "qcom,scm-sdx65", "qcom,scm";
0092 };
0093 };
0094
0095 mc_virt: interconnect-mc-virt {
0096 compatible = "qcom,sdx65-mc-virt";
0097 #interconnect-cells = <1>;
0098 qcom,bcm-voters = <&apps_bcm_voter>;
0099 };
0100
0101 psci {
0102 compatible = "arm,psci-1.0";
0103 method = "smc";
0104 };
0105
0106 reserved_memory: reserved-memory {
0107 #address-cells = <1>;
0108 #size-cells = <1>;
0109 ranges;
0110
0111 tz_heap_mem: memory@8fcad000 {
0112 no-map;
0113 reg = <0x8fcad000 0x40000>;
0114 };
0115
0116 secdata_mem: memory@8fcfd000 {
0117 no-map;
0118 reg = <0x8fcfd000 0x1000>;
0119 };
0120
0121 hyp_mem: memory@8fd00000 {
0122 no-map;
0123 reg = <0x8fd00000 0x80000>;
0124 };
0125
0126 access_control_mem: memory@8fd80000 {
0127 no-map;
0128 reg = <0x8fd80000 0x80000>;
0129 };
0130
0131 aop_mem: memory@8fe00000 {
0132 no-map;
0133 reg = <0x8fe00000 0x20000>;
0134 };
0135
0136 smem_mem: memory@8fe20000 {
0137 compatible = "qcom,smem";
0138 reg = <0x8fe20000 0xc0000>;
0139 hwlocks = <&tcsr_mutex 3>;
0140 no-map;
0141 };
0142
0143 cmd_db: reserved-memory@8fee0000 {
0144 compatible = "qcom,cmd-db";
0145 reg = <0x8fee0000 0x20000>;
0146 no-map;
0147 };
0148
0149 tz_mem: memory@8ff00000 {
0150 no-map;
0151 reg = <0x8ff00000 0x100000>;
0152 };
0153
0154 tz_apps_mem: memory@90000000 {
0155 no-map;
0156 reg = <0x90000000 0x500000>;
0157 };
0158
0159 llcc_tcm_mem: memory@15800000 {
0160 no-map;
0161 reg = <0x15800000 0x800000>;
0162 };
0163 };
0164
0165 smp2p-mpss {
0166 compatible = "qcom,smp2p";
0167 qcom,smem = <435>, <428>;
0168 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
0169 mboxes = <&apcs 14>;
0170 qcom,local-pid = <0>;
0171 qcom,remote-pid = <1>;
0172
0173 modem_smp2p_out: master-kernel {
0174 qcom,entry-name = "master-kernel";
0175 #qcom,smem-state-cells = <1>;
0176 };
0177
0178 modem_smp2p_in: slave-kernel {
0179 qcom,entry-name = "slave-kernel";
0180 interrupt-controller;
0181 #interrupt-cells = <2>;
0182 };
0183
0184 ipa_smp2p_out: ipa-ap-to-modem {
0185 qcom,entry-name = "ipa";
0186 #qcom,smem-state-cells = <1>;
0187 };
0188
0189 ipa_smp2p_in: ipa-modem-to-ap {
0190 qcom,entry-name = "ipa";
0191 interrupt-controller;
0192 #interrupt-cells = <2>;
0193 };
0194 };
0195
0196 soc: soc {
0197 #address-cells = <1>;
0198 #size-cells = <1>;
0199 ranges;
0200 compatible = "simple-bus";
0201
0202 gcc: clock-controller@100000 {
0203 compatible = "qcom,gcc-sdx65";
0204 reg = <0x00100000 0x001f7400>;
0205 clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>;
0206 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
0207 #power-domain-cells = <1>;
0208 #clock-cells = <1>;
0209 #reset-cells = <1>;
0210 };
0211
0212 blsp1_uart3: serial@831000 {
0213 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0214 reg = <0x00831000 0x200>;
0215 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0216 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
0217 clock-names = "core", "iface";
0218 status = "disabled";
0219 };
0220
0221 usb_hsphy: phy@ff4000 {
0222 compatible = "qcom,usb-snps-hs-7nm-phy";
0223 reg = <0xff4000 0x120>;
0224 #phy-cells = <0>;
0225 status = "disabled";
0226 clocks = <&rpmhcc RPMH_CXO_CLK>;
0227 clock-names = "ref";
0228 resets = <&gcc GCC_QUSB2PHY_BCR>;
0229 };
0230
0231 usb_qmpphy: phy@ff6000 {
0232 compatible = "qcom,sdx65-qmp-usb3-uni-phy";
0233 reg = <0x00ff6000 0x1c8>;
0234 status = "disabled";
0235 #address-cells = <1>;
0236 #size-cells = <1>;
0237 ranges;
0238
0239 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
0240 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
0241 <&gcc GCC_USB3_PRIM_CLKREF_EN>;
0242 clock-names = "aux", "cfg_ahb", "ref";
0243
0244 resets = <&gcc GCC_USB3PHY_PHY_BCR>,
0245 <&gcc GCC_USB3_PHY_BCR>;
0246 reset-names = "phy", "common";
0247
0248 usb_ssphy: phy@ff6200 {
0249 reg = <0x00ff6e00 0x160>,
0250 <0x00ff7000 0x1ec>,
0251 <0x00ff6200 0x1e00>;
0252 #phy-cells = <0>;
0253 #clock-cells = <0>;
0254 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
0255 clock-names = "pipe0";
0256 clock-output-names = "usb3_uni_phy_pipe_clk_src";
0257 };
0258 };
0259
0260 system_noc: interconnect@1620000 {
0261 compatible = "qcom,sdx65-system-noc";
0262 reg = <0x01620000 0x31200>;
0263 #interconnect-cells = <1>;
0264 qcom,bcm-voters = <&apps_bcm_voter>;
0265 };
0266
0267 qpic_bam: dma-controller@1b04000 {
0268 compatible = "qcom,bam-v1.7.0";
0269 reg = <0x01b04000 0x1c000>;
0270 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
0271 clocks = <&rpmhcc RPMH_QPIC_CLK>;
0272 clock-names = "bam_clk";
0273 #dma-cells = <1>;
0274 qcom,ee = <0>;
0275 qcom,controlled-remotely;
0276 status = "disabled";
0277 };
0278
0279 qpic_nand: nand-controller@1b30000 {
0280 compatible = "qcom,sdx55-nand";
0281 reg = <0x01b30000 0x10000>;
0282 #address-cells = <1>;
0283 #size-cells = <0>;
0284 clocks = <&rpmhcc RPMH_QPIC_CLK>,
0285 <&nand_clk_dummy>;
0286 clock-names = "core", "aon";
0287
0288 dmas = <&qpic_bam 0>,
0289 <&qpic_bam 1>,
0290 <&qpic_bam 2>;
0291 dma-names = "tx", "rx", "cmd";
0292 status = "disabled";
0293 };
0294
0295 tcsr_mutex: hwlock@1f40000 {
0296 compatible = "qcom,tcsr-mutex";
0297 reg = <0x01f40000 0x40000>;
0298 #hwlock-cells = <1>;
0299 };
0300
0301 remoteproc_mpss: remoteproc@4080000 {
0302 compatible = "qcom,sdx55-mpss-pas";
0303 reg = <0x04080000 0x4040>;
0304
0305 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
0306 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
0307 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
0308 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
0309 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
0310 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
0311 interrupt-names = "wdog", "fatal", "ready", "handover",
0312 "stop-ack", "shutdown-ack";
0313
0314 clocks = <&rpmhcc RPMH_CXO_CLK>;
0315 clock-names = "xo";
0316
0317 power-domains = <&rpmhpd SDX65_CX>,
0318 <&rpmhpd SDX65_MSS>;
0319 power-domain-names = "cx", "mss";
0320
0321 qcom,smem-states = <&modem_smp2p_out 0>;
0322 qcom,smem-state-names = "stop";
0323
0324 status = "disabled";
0325
0326 glink-edge {
0327 interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
0328 label = "mpss";
0329 qcom,remote-pid = <1>;
0330 mboxes = <&apcs 15>;
0331 };
0332 };
0333
0334 sdhc_1: mmc@8804000 {
0335 compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
0336 reg = <0x08804000 0x1000>;
0337 reg-names = "hc_mem";
0338 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
0339 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
0340 interrupt-names = "hc_irq", "pwr_irq";
0341 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
0342 <&gcc GCC_SDCC1_AHB_CLK>;
0343 clock-names = "core", "iface";
0344 status = "disabled";
0345 };
0346
0347 mem_noc: interconnect@9680000 {
0348 compatible = "qcom,sdx65-mem-noc";
0349 reg = <0x09680000 0x27200>;
0350 #interconnect-cells = <1>;
0351 qcom,bcm-voters = <&apps_bcm_voter>;
0352 };
0353
0354 usb: usb@a6f8800 {
0355 compatible = "qcom,sdx65-dwc3", "qcom,dwc3";
0356 reg = <0x0a6f8800 0x400>;
0357 status = "disabled";
0358 #address-cells = <1>;
0359 #size-cells = <1>;
0360 ranges;
0361
0362 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
0363 <&gcc GCC_USB30_MASTER_CLK>,
0364 <&gcc GCC_USB30_MSTR_AXI_CLK>,
0365 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
0366 <&gcc GCC_USB30_SLEEP_CLK>;
0367 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
0368 "sleep";
0369
0370 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
0371 <&gcc GCC_USB30_MASTER_CLK>;
0372 assigned-clock-rates = <19200000>, <200000000>;
0373
0374 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
0375 <&pdc 76 IRQ_TYPE_LEVEL_HIGH>,
0376 <&pdc 18 IRQ_TYPE_EDGE_BOTH>,
0377 <&pdc 19 IRQ_TYPE_EDGE_BOTH>;
0378 interrupt-names = "hs_phy_irq",
0379 "ss_phy_irq",
0380 "dm_hs_phy_irq",
0381 "dp_hs_phy_irq";
0382
0383 power-domains = <&gcc USB30_GDSC>;
0384
0385 resets = <&gcc GCC_USB30_BCR>;
0386
0387 usb_dwc3: usb@a600000 {
0388 compatible = "snps,dwc3";
0389 reg = <0x0a600000 0xcd00>;
0390 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
0391 iommus = <&apps_smmu 0x1a0 0x0>;
0392 snps,dis_u2_susphy_quirk;
0393 snps,dis_enblslpm_quirk;
0394 phys = <&usb_hsphy>, <&usb_ssphy>;
0395 phy-names = "usb2-phy", "usb3-phy";
0396 };
0397 };
0398
0399 restart@c264000 {
0400 compatible = "qcom,pshold";
0401 reg = <0x0c264000 0x1000>;
0402 };
0403
0404 spmi_bus: qcom,spmi@c440000 {
0405 compatible = "qcom,spmi-pmic-arb";
0406 reg = <0xc440000 0xd00>,
0407 <0xc600000 0x2000000>,
0408 <0xe600000 0x100000>,
0409 <0xe700000 0xa0000>,
0410 <0xc40a000 0x26000>;
0411 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
0412 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
0413 interrupt-names = "periph_irq";
0414 interrupt-controller;
0415 #interrupt-cells = <4>;
0416 #address-cells = <2>;
0417 #size-cells = <0>;
0418 cell-index = <0>;
0419 qcom,channel = <0>;
0420 qcom,ee = <0>;
0421 };
0422
0423 tlmm: pinctrl@f100000 {
0424 compatible = "qcom,sdx65-tlmm";
0425 reg = <0xf100000 0x300000>;
0426 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
0427 gpio-controller;
0428 #gpio-cells = <2>;
0429 gpio-ranges = <&tlmm 0 0 109>;
0430 interrupt-controller;
0431 interrupt-parent = <&intc>;
0432 #interrupt-cells = <2>;
0433 };
0434
0435 pdc: interrupt-controller@b210000 {
0436 compatible = "qcom,sdx65-pdc", "qcom,pdc";
0437 reg = <0xb210000 0x10000>;
0438 qcom,pdc-ranges = <0 147 52>, <52 266 32>;
0439 #interrupt-cells = <2>;
0440 interrupt-parent = <&intc>;
0441 interrupt-controller;
0442 };
0443
0444 imem@1468f000 {
0445 compatible = "simple-mfd";
0446 reg = <0x1468f000 0x1000>;
0447 ranges = <0x0 0x1468f000 0x1000>;
0448 #address-cells = <1>;
0449 #size-cells = <1>;
0450
0451 pil-reloc@94c {
0452 compatible = "qcom,pil-reloc-info";
0453 reg = <0x94c 0xc8>;
0454 };
0455 };
0456
0457 apps_smmu: iommu@15000000 {
0458 compatible = "qcom,sdx65-smmu-500", "arm,mmu-500";
0459 reg = <0x15000000 0x40000>;
0460 #iommu-cells = <2>;
0461 #global-interrupts = <1>;
0462 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
0463 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0464 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
0465 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
0466 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
0467 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
0468 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
0469 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
0470 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
0471 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
0472 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
0473 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
0474 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
0475 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
0476 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
0477 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0478 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0479 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0480 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
0481 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
0482 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0483 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0484 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
0485 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
0486 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
0487 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
0488 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
0489 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
0490 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
0491 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
0492 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
0493 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
0494 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
0495 };
0496
0497 intc: interrupt-controller@17800000 {
0498 compatible = "qcom,msm-qgic2";
0499 interrupt-controller;
0500 interrupt-parent = <&intc>;
0501 #interrupt-cells = <3>;
0502 reg = <0x17800000 0x1000>,
0503 <0x17802000 0x1000>;
0504 };
0505
0506 a7pll: clock@17808000 {
0507 compatible = "qcom,sdx55-a7pll";
0508 reg = <0x17808000 0x1000>;
0509 clocks = <&rpmhcc RPMH_CXO_CLK>;
0510 clock-names = "bi_tcxo";
0511 #clock-cells = <0>;
0512 };
0513
0514 apcs: mailbox@17810000 {
0515 compatible = "qcom,sdx55-apcs-gcc", "syscon";
0516 reg = <0x17810000 0x2000>;
0517 #mbox-cells = <1>;
0518 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;
0519 clock-names = "ref", "pll", "aux";
0520 #clock-cells = <0>;
0521 };
0522
0523 watchdog@17817000 {
0524 compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt";
0525 reg = <0x17817000 0x1000>;
0526 clocks = <&sleep_clk>;
0527 };
0528
0529 timer@17820000 {
0530 #address-cells = <1>;
0531 #size-cells = <1>;
0532 ranges;
0533 compatible = "arm,armv7-timer-mem";
0534 reg = <0x17820000 0x1000>;
0535 clock-frequency = <19200000>;
0536
0537 frame@17821000 {
0538 frame-number = <0>;
0539 interrupts = <GIC_SPI 7 0x4>,
0540 <GIC_SPI 6 0x4>;
0541 reg = <0x17821000 0x1000>,
0542 <0x17822000 0x1000>;
0543 };
0544
0545 frame@17823000 {
0546 frame-number = <1>;
0547 interrupts = <GIC_SPI 8 0x4>;
0548 reg = <0x17823000 0x1000>;
0549 status = "disabled";
0550 };
0551
0552 frame@17824000 {
0553 frame-number = <2>;
0554 interrupts = <GIC_SPI 9 0x4>;
0555 reg = <0x17824000 0x1000>;
0556 status = "disabled";
0557 };
0558
0559 frame@17825000 {
0560 frame-number = <3>;
0561 interrupts = <GIC_SPI 10 0x4>;
0562 reg = <0x17825000 0x1000>;
0563 status = "disabled";
0564 };
0565
0566 frame@17826000 {
0567 frame-number = <4>;
0568 interrupts = <GIC_SPI 11 0x4>;
0569 reg = <0x17826000 0x1000>;
0570 status = "disabled";
0571 };
0572
0573 frame@17827000 {
0574 frame-number = <5>;
0575 interrupts = <GIC_SPI 12 0x4>;
0576 reg = <0x17827000 0x1000>;
0577 status = "disabled";
0578 };
0579
0580 frame@17828000 {
0581 frame-number = <6>;
0582 interrupts = <GIC_SPI 13 0x4>;
0583 reg = <0x17828000 0x1000>;
0584 status = "disabled";
0585 };
0586
0587 frame@17829000 {
0588 frame-number = <7>;
0589 interrupts = <GIC_SPI 14 0x4>;
0590 reg = <0x17829000 0x1000>;
0591 status = "disabled";
0592 };
0593 };
0594
0595 apps_rsc: rsc@17830000 {
0596 label = "apps_rsc";
0597 compatible = "qcom,rpmh-rsc";
0598 reg = <0x17830000 0x10000>,
0599 <0x17840000 0x10000>;
0600 reg-names = "drv-0", "drv-1";
0601 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
0602 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0603 qcom,tcs-offset = <0xd00>;
0604 qcom,drv-id = <1>;
0605 qcom,tcs-config = <ACTIVE_TCS 2>,
0606 <SLEEP_TCS 2>,
0607 <WAKE_TCS 2>,
0608 <CONTROL_TCS 1>;
0609
0610 rpmhcc: clock-controller {
0611 compatible = "qcom,sdx65-rpmh-clk";
0612 #clock-cells = <1>;
0613 clock-names = "xo";
0614 clocks = <&xo_board>;
0615 };
0616
0617 rpmhpd: power-controller {
0618 compatible = "qcom,sdx65-rpmhpd";
0619 #power-domain-cells = <1>;
0620 operating-points-v2 = <&rpmhpd_opp_table>;
0621
0622 rpmhpd_opp_table: opp-table {
0623 compatible = "operating-points-v2";
0624
0625 rpmhpd_opp_ret: opp1 {
0626 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
0627 };
0628
0629 rpmhpd_opp_min_svs: opp2 {
0630 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
0631 };
0632
0633 rpmhpd_opp_low_svs: opp3 {
0634 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
0635 };
0636
0637 rpmhpd_opp_svs: opp4 {
0638 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
0639 };
0640
0641 rpmhpd_opp_svs_l1: opp5 {
0642 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
0643 };
0644
0645 rpmhpd_opp_nom: opp6 {
0646 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
0647 };
0648
0649 rpmhpd_opp_nom_l1: opp7 {
0650 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
0651 };
0652
0653 rpmhpd_opp_nom_l2: opp8 {
0654 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
0655 };
0656
0657 rpmhpd_opp_turbo: opp9 {
0658 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
0659 };
0660
0661 rpmhpd_opp_turbo_l1: opp10 {
0662 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
0663 };
0664 };
0665 };
0666
0667 apps_bcm_voter: bcm-voter {
0668 compatible = "qcom,bcm-voter";
0669 };
0670
0671 };
0672 };
0673
0674 timer {
0675 compatible = "arm,armv7-timer";
0676 interrupts = <1 13 0xf08>,
0677 <1 12 0xf08>,
0678 <1 10 0xf08>,
0679 <1 11 0xf08>;
0680 clock-frequency = <19200000>;
0681 };
0682 };
