0001 // SPDX-License-Identifier: BSD-3-Clause
0002 /*
0003 * SDX55 SoC device tree source
0004 *
0005 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
0006 * Copyright (c) 2020, Linaro Ltd.
0007 */
0008
0009 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
0010 #include <dt-bindings/clock/qcom,rpmh.h>
0011 #include <dt-bindings/gpio/gpio.h>
0012 #include <dt-bindings/interconnect/qcom,sdx55.h>
0013 #include <dt-bindings/interrupt-controller/arm-gic.h>
0014 #include <dt-bindings/power/qcom-rpmpd.h>
0015 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
0016
0017 / {
0018 #address-cells = <1>;
0019 #size-cells = <1>;
0020 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
0021 interrupt-parent = <&intc>;
0022
0023 memory {
0024 device_type = "memory";
0025 reg = <0 0>;
0026 };
0027
0028 clocks {
0029 xo_board: xo-board {
0030 compatible = "fixed-clock";
0031 #clock-cells = <0>;
0032 clock-frequency = <38400000>;
0033 clock-output-names = "xo_board";
0034 };
0035
0036 sleep_clk: sleep-clk {
0037 compatible = "fixed-clock";
0038 #clock-cells = <0>;
0039 clock-frequency = <32000>;
0040 };
0041
0042 nand_clk_dummy: nand-clk-dummy {
0043 compatible = "fixed-clock";
0044 #clock-cells = <0>;
0045 clock-frequency = <32000>;
0046 };
0047 };
0048
0049 cpus {
0050 #address-cells = <1>;
0051 #size-cells = <0>;
0052
0053 cpu0: cpu@0 {
0054 device_type = "cpu";
0055 compatible = "arm,cortex-a7";
0056 reg = <0x0>;
0057 enable-method = "psci";
0058 clocks = <&apcs>;
0059 power-domains = <&rpmhpd SDX55_CX>;
0060 power-domain-names = "rpmhpd";
0061 operating-points-v2 = <&cpu_opp_table>;
0062 };
0063 };
0064
0065 cpu_opp_table: cpu-opp-table {
0066 compatible = "operating-points-v2";
0067 opp-shared;
0068
0069 opp-345600000 {
0070 opp-hz = /bits/ 64 <345600000>;
0071 required-opps = <&rpmhpd_opp_low_svs>;
0072 };
0073
0074 opp-576000000 {
0075 opp-hz = /bits/ 64 <576000000>;
0076 required-opps = <&rpmhpd_opp_svs>;
0077 };
0078
0079 opp-1094400000 {
0080 opp-hz = /bits/ 64 <1094400000>;
0081 required-opps = <&rpmhpd_opp_nom>;
0082 };
0083
0084 opp-1555200000 {
0085 opp-hz = /bits/ 64 <1555200000>;
0086 required-opps = <&rpmhpd_opp_turbo>;
0087 };
0088 };
0089
0090 firmware {
0091 scm {
0092 compatible = "qcom,scm-sdx55", "qcom,scm";
0093 };
0094 };
0095
0096 psci {
0097 compatible = "arm,psci-1.0";
0098 method = "smc";
0099 };
0100
0101 reserved-memory {
0102 #address-cells = <1>;
0103 #size-cells = <1>;
0104 ranges;
0105
0106 hyp_mem: memory@8fc00000 {
0107 no-map;
0108 reg = <0x8fc00000 0x80000>;
0109 };
0110
0111 ac_db_mem: memory@8fc80000 {
0112 no-map;
0113 reg = <0x8fc80000 0x40000>;
0114 };
0115
0116 secdata_mem: memory@8fcfd000 {
0117 no-map;
0118 reg = <0x8fcfd000 0x1000>;
0119 };
0120
0121 sbl_mem: memory@8fd00000 {
0122 no-map;
0123 reg = <0x8fd00000 0x100000>;
0124 };
0125
0126 aop_image: memory@8fe00000 {
0127 no-map;
0128 reg = <0x8fe00000 0x20000>;
0129 };
0130
0131 aop_cmd_db: memory@8fe20000 {
0132 compatible = "qcom,cmd-db";
0133 reg = <0x8fe20000 0x20000>;
0134 no-map;
0135 };
0136
0137 smem_mem: memory@8fe40000 {
0138 no-map;
0139 reg = <0x8fe40000 0xc0000>;
0140 };
0141
0142 tz_mem: memory@8ff00000 {
0143 no-map;
0144 reg = <0x8ff00000 0x100000>;
0145 };
0146
0147 tz_apps_mem: memory@90000000 {
0148 no-map;
0149 reg = <0x90000000 0x500000>;
0150 };
0151 };
0152
0153 smem {
0154 compatible = "qcom,smem";
0155 memory-region = <&smem_mem>;
0156 hwlocks = <&tcsr_mutex 3>;
0157 };
0158
0159 smp2p-mpss {
0160 compatible = "qcom,smp2p";
0161 qcom,smem = <435>, <428>;
0162 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
0163 mboxes = <&apcs 14>;
0164 qcom,local-pid = <0>;
0165 qcom,remote-pid = <1>;
0166
0167 modem_smp2p_out: master-kernel {
0168 qcom,entry-name = "master-kernel";
0169 #qcom,smem-state-cells = <1>;
0170 };
0171
0172 modem_smp2p_in: slave-kernel {
0173 qcom,entry-name = "slave-kernel";
0174 interrupt-controller;
0175 #interrupt-cells = <2>;
0176 };
0177
0178 ipa_smp2p_out: ipa-ap-to-modem {
0179 qcom,entry-name = "ipa";
0180 #qcom,smem-state-cells = <1>;
0181 };
0182
0183 ipa_smp2p_in: ipa-modem-to-ap {
0184 qcom,entry-name = "ipa";
0185 interrupt-controller;
0186 #interrupt-cells = <2>;
0187 };
0188 };
0189
0190 soc: soc {
0191 #address-cells = <1>;
0192 #size-cells = <1>;
0193 ranges;
0194 compatible = "simple-bus";
0195
0196 gcc: clock-controller@100000 {
0197 compatible = "qcom,gcc-sdx55";
0198 reg = <0x100000 0x1f0000>;
0199 #clock-cells = <1>;
0200 #reset-cells = <1>;
0201 #power-domain-cells = <1>;
0202 clock-names = "bi_tcxo", "sleep_clk";
0203 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
0204 };
0205
0206 blsp1_uart3: serial@831000 {
0207 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0208 reg = <0x00831000 0x200>;
0209 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0210 clocks = <&gcc 30>,
0211 <&gcc 9>;
0212 clock-names = "core", "iface";
0213 status = "disabled";
0214 };
0215
0216 usb_hsphy: phy@ff4000 {
0217 compatible = "qcom,usb-snps-hs-7nm-phy";
0218 reg = <0x00ff4000 0x114>;
0219 status = "disabled";
0220 #phy-cells = <0>;
0221
0222 clocks = <&rpmhcc RPMH_CXO_CLK>;
0223 clock-names = "ref";
0224
0225 resets = <&gcc GCC_QUSB2PHY_BCR>;
0226 };
0227
0228 usb_qmpphy: phy@ff6000 {
0229 compatible = "qcom,sdx55-qmp-usb3-uni-phy";
0230 reg = <0x00ff6000 0x1c0>;
0231 status = "disabled";
0232 #address-cells = <1>;
0233 #size-cells = <1>;
0234 ranges;
0235
0236 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
0237 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
0238 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
0239 clock-names = "aux", "cfg_ahb", "ref";
0240
0241 resets = <&gcc GCC_USB3PHY_PHY_BCR>,
0242 <&gcc GCC_USB3_PHY_BCR>;
0243 reset-names = "phy", "common";
0244
0245 usb_ssphy: phy@ff6200 {
0246 reg = <0x00ff6200 0x170>,
0247 <0x00ff6400 0x200>,
0248 <0x00ff6800 0x800>;
0249 #phy-cells = <0>;
0250 #clock-cells = <0>;
0251 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
0252 clock-names = "pipe0";
0253 clock-output-names = "usb3_uni_phy_pipe_clk_src";
0254 };
0255 };
0256
0257 mc_virt: interconnect@1100000 {
0258 compatible = "qcom,sdx55-mc-virt";
0259 reg = <0x01100000 0x400000>;
0260 #interconnect-cells = <1>;
0261 qcom,bcm-voters = <&apps_bcm_voter>;
0262 };
0263
0264 mem_noc: interconnect@9680000 {
0265 compatible = "qcom,sdx55-mem-noc";
0266 reg = <0x09680000 0x40000>;
0267 #interconnect-cells = <1>;
0268 qcom,bcm-voters = <&apps_bcm_voter>;
0269 };
0270
0271 system_noc: interconnect@162c000 {
0272 compatible = "qcom,sdx55-system-noc";
0273 reg = <0x0162c000 0x31200>;
0274 #interconnect-cells = <1>;
0275 qcom,bcm-voters = <&apps_bcm_voter>;
0276 };
0277
0278 qpic_bam: dma-controller@1b04000 {
0279 compatible = "qcom,bam-v1.7.0";
0280 reg = <0x01b04000 0x1c000>;
0281 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
0282 clocks = <&rpmhcc RPMH_QPIC_CLK>;
0283 clock-names = "bam_clk";
0284 #dma-cells = <1>;
0285 qcom,ee = <0>;
0286 qcom,controlled-remotely;
0287 status = "disabled";
0288 };
0289
0290 qpic_nand: nand-controller@1b30000 {
0291 compatible = "qcom,sdx55-nand";
0292 reg = <0x01b30000 0x10000>;
0293 #address-cells = <1>;
0294 #size-cells = <0>;
0295 clocks = <&rpmhcc RPMH_QPIC_CLK>,
0296 <&nand_clk_dummy>;
0297 clock-names = "core", "aon";
0298
0299 dmas = <&qpic_bam 0>,
0300 <&qpic_bam 1>,
0301 <&qpic_bam 2>;
0302 dma-names = "tx", "rx", "cmd";
0303 status = "disabled";
0304 };
0305
0306 pcie0_phy: phy@1c07000 {
0307 compatible = "qcom,sdx55-qmp-pcie-phy";
0308 reg = <0x01c07000 0x1c4>;
0309 #address-cells = <1>;
0310 #size-cells = <1>;
0311 ranges;
0312 clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
0313 <&gcc GCC_PCIE_CFG_AHB_CLK>,
0314 <&gcc GCC_PCIE_0_CLKREF_CLK>,
0315 <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
0316 clock-names = "aux", "cfg_ahb", "ref", "refgen";
0317
0318 resets = <&gcc GCC_PCIE_PHY_BCR>;
0319 reset-names = "phy";
0320
0321 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
0322 assigned-clock-rates = <100000000>;
0323
0324 status = "disabled";
0325
0326 pcie0_lane: lanes@1c06000 {
0327 reg = <0x01c06000 0x104>, /* tx0 */
0328 <0x01c06200 0x328>, /* rx0 */
0329 <0x01c07200 0x1e8>, /* pcs */
0330 <0x01c06800 0x104>, /* tx1 */
0331 <0x01c06a00 0x328>, /* rx1 */
0332 <0x01c07600 0x800>; /* pcs_misc */
0333 clocks = <&gcc GCC_PCIE_PIPE_CLK>;
0334 clock-names = "pipe0";
0335
0336 #phy-cells = <0>;
0337 clock-output-names = "pcie_pipe_clk";
0338 };
0339 };
0340
0341 ipa: ipa@1e40000 {
0342 compatible = "qcom,sdx55-ipa";
0343
0344 iommus = <&apps_smmu 0x5e0 0x0>,
0345 <&apps_smmu 0x5e2 0x0>;
0346 reg = <0x1e40000 0x7000>,
0347 <0x1e50000 0x4b20>,
0348 <0x1e04000 0x2c000>;
0349 reg-names = "ipa-reg",
0350 "ipa-shared",
0351 "gsi";
0352
0353 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
0354 <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
0355 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
0356 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
0357 interrupt-names = "ipa",
0358 "gsi",
0359 "ipa-clock-query",
0360 "ipa-setup-ready";
0361
0362 clocks = <&rpmhcc RPMH_IPA_CLK>;
0363 clock-names = "core";
0364
0365 interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI_CH0>,
0366 <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>,
0367 <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_IPA_CFG>;
0368 interconnect-names = "memory",
0369 "imem",
0370 "config";
0371
0372 qcom,smem-states = <&ipa_smp2p_out 0>,
0373 <&ipa_smp2p_out 1>;
0374 qcom,smem-state-names = "ipa-clock-enabled-valid",
0375 "ipa-clock-enabled";
0376
0377 status = "disabled";
0378 };
0379
0380 tcsr_mutex: hwlock@1f40000 {
0381 compatible = "qcom,tcsr-mutex";
0382 reg = <0x01f40000 0x40000>;
0383 #hwlock-cells = <1>;
0384 };
0385
0386 tcsr: syscon@1fcb000 {
0387 compatible = "syscon";
0388 reg = <0x01fc0000 0x1000>;
0389 };
0390
0391 sdhc_1: mmc@8804000 {
0392 compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
0393 reg = <0x08804000 0x1000>;
0394 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
0395 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
0396 interrupt-names = "hc_irq", "pwr_irq";
0397 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
0398 <&gcc GCC_SDCC1_APPS_CLK>;
0399 clock-names = "iface", "core";
0400 status = "disabled";
0401 };
0402
0403 pcie_ep: pcie-ep@40000000 {
0404 compatible = "qcom,sdx55-pcie-ep";
0405 reg = <0x01c00000 0x3000>,
0406 <0x40000000 0xf1d>,
0407 <0x40000f20 0xc8>,
0408 <0x40001000 0x1000>,
0409 <0x40200000 0x100000>,
0410 <0x01c03000 0x3000>;
0411 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
0412 "mmio";
0413
0414 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
0415
0416 clocks = <&gcc GCC_PCIE_AUX_CLK>,
0417 <&gcc GCC_PCIE_CFG_AHB_CLK>,
0418 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
0419 <&gcc GCC_PCIE_SLV_AXI_CLK>,
0420 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
0421 <&gcc GCC_PCIE_SLEEP_CLK>,
0422 <&gcc GCC_PCIE_0_CLKREF_CLK>;
0423 clock-names = "aux", "cfg", "bus_master", "bus_slave",
0424 "slave_q2a", "sleep", "ref";
0425
0426 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
0427 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
0428 interrupt-names = "global", "doorbell";
0429 reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
0430 wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
0431 resets = <&gcc GCC_PCIE_BCR>;
0432 reset-names = "core";
0433 power-domains = <&gcc PCIE_GDSC>;
0434 phys = <&pcie0_lane>;
0435 phy-names = "pciephy";
0436 max-link-speed = <3>;
0437 num-lanes = <2>;
0438
0439 status = "disabled";
0440 };
0441
0442 remoteproc_mpss: remoteproc@4080000 {
0443 compatible = "qcom,sdx55-mpss-pas";
0444 reg = <0x04080000 0x4040>;
0445
0446 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
0447 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
0448 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
0449 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
0450 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
0451 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
0452 interrupt-names = "wdog", "fatal", "ready", "handover",
0453 "stop-ack", "shutdown-ack";
0454
0455 clocks = <&rpmhcc RPMH_CXO_CLK>;
0456 clock-names = "xo";
0457
0458 power-domains = <&rpmhpd SDX55_CX>,
0459 <&rpmhpd SDX55_MSS>;
0460 power-domain-names = "cx", "mss";
0461
0462 qcom,smem-states = <&modem_smp2p_out 0>;
0463 qcom,smem-state-names = "stop";
0464
0465 status = "disabled";
0466
0467 glink-edge {
0468 interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
0469 label = "mpss";
0470 qcom,remote-pid = <1>;
0471 mboxes = <&apcs 15>;
0472 };
0473 };
0474
0475 usb: usb@a6f8800 {
0476 compatible = "qcom,sdx55-dwc3", "qcom,dwc3";
0477 reg = <0x0a6f8800 0x400>;
0478 status = "disabled";
0479 #address-cells = <1>;
0480 #size-cells = <1>;
0481 ranges;
0482
0483 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
0484 <&gcc GCC_USB30_MASTER_CLK>,
0485 <&gcc GCC_USB30_MSTR_AXI_CLK>,
0486 <&gcc GCC_USB30_SLEEP_CLK>,
0487 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
0488 clock-names = "cfg_noc",
0489 "core",
0490 "iface",
0491 "sleep",
0492 "mock_utmi";
0493
0494 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
0495 <&gcc GCC_USB30_MASTER_CLK>;
0496 assigned-clock-rates = <19200000>, <200000000>;
0497
0498 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
0499 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
0500 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
0501 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
0502 interrupt-names = "hs_phy_irq", "ss_phy_irq",
0503 "dm_hs_phy_irq", "dp_hs_phy_irq";
0504
0505 power-domains = <&gcc USB30_GDSC>;
0506
0507 resets = <&gcc GCC_USB30_BCR>;
0508
0509 usb_dwc3: dwc3@a600000 {
0510 compatible = "snps,dwc3";
0511 reg = <0x0a600000 0xcd00>;
0512 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
0513 iommus = <&apps_smmu 0x1a0 0x0>;
0514 snps,dis_u2_susphy_quirk;
0515 snps,dis_enblslpm_quirk;
0516 phys = <&usb_hsphy>, <&usb_ssphy>;
0517 phy-names = "usb2-phy", "usb3-phy";
0518 };
0519 };
0520
0521 pdc: interrupt-controller@b210000 {
0522 compatible = "qcom,sdx55-pdc", "qcom,pdc";
0523 reg = <0x0b210000 0x30000>;
0524 qcom,pdc-ranges = <0 179 52>;
0525 #interrupt-cells = <3>;
0526 interrupt-parent = <&intc>;
0527 interrupt-controller;
0528 };
0529
0530 restart@c264000 {
0531 compatible = "qcom,pshold";
0532 reg = <0x0c264000 0x1000>;
0533 };
0534
0535 spmi_bus: spmi@c440000 {
0536 compatible = "qcom,spmi-pmic-arb";
0537 reg = <0x0c440000 0x0000d00>,
0538 <0x0c600000 0x2000000>,
0539 <0x0e600000 0x0100000>,
0540 <0x0e700000 0x00a0000>,
0541 <0x0c40a000 0x0000700>;
0542 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
0543 interrupt-names = "periph_irq";
0544 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
0545 qcom,ee = <0>;
0546 qcom,channel = <0>;
0547 #address-cells = <2>;
0548 #size-cells = <0>;
0549 interrupt-controller;
0550 #interrupt-cells = <4>;
0551 cell-index = <0>;
0552 };
0553
0554 tlmm: pinctrl@f100000 {
0555 compatible = "qcom,sdx55-pinctrl";
0556 reg = <0xf100000 0x300000>;
0557 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
0558 gpio-controller;
0559 #gpio-cells = <2>;
0560 interrupt-controller;
0561 #interrupt-cells = <2>;
0562 };
0563
0564 sram@1468f000 {
0565 compatible = "qcom,sdx55-imem", "syscon", "simple-mfd";
0566 reg = <0x1468f000 0x1000>;
0567
0568 #address-cells = <1>;
0569 #size-cells = <1>;
0570
0571 ranges = <0x0 0x1468f000 0x1000>;
0572
0573 pil-reloc@94c {
0574 compatible = "qcom,pil-reloc-info";
0575 reg = <0x94c 0x200>;
0576 };
0577 };
0578
0579 apps_smmu: iommu@15000000 {
0580 compatible = "qcom,sdx55-smmu-500", "arm,mmu-500";
0581 reg = <0x15000000 0x20000>;
0582 #iommu-cells = <2>;
0583 #global-interrupts = <1>;
0584 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
0585 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0586 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
0587 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
0588 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
0589 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
0590 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
0591 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
0592 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
0593 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
0594 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
0595 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
0596 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
0597 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
0598 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
0599 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0600 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0601 };
0602
0603 intc: interrupt-controller@17800000 {
0604 compatible = "qcom,msm-qgic2";
0605 interrupt-controller;
0606 interrupt-parent = <&intc>;
0607 #interrupt-cells = <3>;
0608 reg = <0x17800000 0x1000>,
0609 <0x17802000 0x1000>;
0610 };
0611
0612 a7pll: clock@17808000 {
0613 compatible = "qcom,sdx55-a7pll";
0614 reg = <0x17808000 0x1000>;
0615 clocks = <&rpmhcc RPMH_CXO_CLK>;
0616 clock-names = "bi_tcxo";
0617 #clock-cells = <0>;
0618 };
0619
0620 apcs: mailbox@17810000 {
0621 compatible = "qcom,sdx55-apcs-gcc", "syscon";
0622 reg = <0x17810000 0x2000>;
0623 #mbox-cells = <1>;
0624 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;
0625 clock-names = "ref", "pll", "aux";
0626 #clock-cells = <0>;
0627 };
0628
0629 watchdog@17817000 {
0630 compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt";
0631 reg = <0x17817000 0x1000>;
0632 clocks = <&sleep_clk>;
0633 };
0634
0635 timer@17820000 {
0636 #address-cells = <1>;
0637 #size-cells = <1>;
0638 ranges;
0639 compatible = "arm,armv7-timer-mem";
0640 reg = <0x17820000 0x1000>;
0641 clock-frequency = <19200000>;
0642
0643 frame@17821000 {
0644 frame-number = <0>;
0645 interrupts = <GIC_SPI 7 0x4>,
0646 <GIC_SPI 6 0x4>;
0647 reg = <0x17821000 0x1000>,
0648 <0x17822000 0x1000>;
0649 };
0650
0651 frame@17823000 {
0652 frame-number = <1>;
0653 interrupts = <GIC_SPI 8 0x4>;
0654 reg = <0x17823000 0x1000>;
0655 status = "disabled";
0656 };
0657
0658 frame@17824000 {
0659 frame-number = <2>;
0660 interrupts = <GIC_SPI 9 0x4>;
0661 reg = <0x17824000 0x1000>;
0662 status = "disabled";
0663 };
0664
0665 frame@17825000 {
0666 frame-number = <3>;
0667 interrupts = <GIC_SPI 10 0x4>;
0668 reg = <0x17825000 0x1000>;
0669 status = "disabled";
0670 };
0671
0672 frame@17826000 {
0673 frame-number = <4>;
0674 interrupts = <GIC_SPI 11 0x4>;
0675 reg = <0x17826000 0x1000>;
0676 status = "disabled";
0677 };
0678
0679 frame@17827000 {
0680 frame-number = <5>;
0681 interrupts = <GIC_SPI 12 0x4>;
0682 reg = <0x17827000 0x1000>;
0683 status = "disabled";
0684 };
0685
0686 frame@17828000 {
0687 frame-number = <6>;
0688 interrupts = <GIC_SPI 13 0x4>;
0689 reg = <0x17828000 0x1000>;
0690 status = "disabled";
0691 };
0692
0693 frame@17829000 {
0694 frame-number = <7>;
0695 interrupts = <GIC_SPI 14 0x4>;
0696 reg = <0x17829000 0x1000>;
0697 status = "disabled";
0698 };
0699 };
0700
0701 apps_rsc: rsc@17840000 {
0702 compatible = "qcom,rpmh-rsc";
0703 reg = <0x17830000 0x10000>, <0x17840000 0x10000>;
0704 reg-names = "drv-0", "drv-1";
0705 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
0706 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0707 qcom,tcs-offset = <0xd00>;
0708 qcom,drv-id = <1>;
0709 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 2>,
0710 <WAKE_TCS 2>, <CONTROL_TCS 1>;
0711
0712 rpmhcc: clock-controller {
0713 compatible = "qcom,sdx55-rpmh-clk";
0714 #clock-cells = <1>;
0715 clock-names = "xo";
0716 clocks = <&xo_board>;
0717 };
0718
0719 rpmhpd: power-controller {
0720 compatible = "qcom,sdx55-rpmhpd";
0721 #power-domain-cells = <1>;
0722 operating-points-v2 = <&rpmhpd_opp_table>;
0723
0724 rpmhpd_opp_table: opp-table {
0725 compatible = "operating-points-v2";
0726
0727 rpmhpd_opp_ret: opp1 {
0728 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
0729 };
0730
0731 rpmhpd_opp_min_svs: opp2 {
0732 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
0733 };
0734
0735 rpmhpd_opp_low_svs: opp3 {
0736 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
0737 };
0738
0739 rpmhpd_opp_svs: opp4 {
0740 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
0741 };
0742
0743 rpmhpd_opp_svs_l1: opp5 {
0744 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
0745 };
0746
0747 rpmhpd_opp_nom: opp6 {
0748 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
0749 };
0750
0751 rpmhpd_opp_nom_l1: opp7 {
0752 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
0753 };
0754
0755 rpmhpd_opp_nom_l2: opp8 {
0756 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
0757 };
0758
0759 rpmhpd_opp_turbo: opp9 {
0760 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
0761 };
0762
0763 rpmhpd_opp_turbo_l1: opp10 {
0764 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
0765 };
0766 };
0767 };
0768
0769 apps_bcm_voter: bcm-voter {
0770 compatible = "qcom,bcm-voter";
0771 };
0772 };
0773 };
0774
0775 timer {
0776 compatible = "arm,armv7-timer";
0777 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0778 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0779 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0780 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0781 clock-frequency = <19200000>;
0782 };
0783 };
