0001 // SPDX-License-Identifier: GPL-2.0
0002 /dts-v1/;
0003
0004 #include <dt-bindings/interrupt-controller/irq.h>
0005 #include <dt-bindings/interrupt-controller/arm-gic.h>
0006 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
0007 #include <dt-bindings/soc/qcom,gsbi.h>
0008
0009 / {
0010 #address-cells = <1>;
0011 #size-cells = <1>;
0012 model = "Qualcomm MSM8660";
0013 compatible = "qcom,msm8660";
0014 interrupt-parent = <&intc>;
0015
0016 cpus {
0017 #address-cells = <1>;
0018 #size-cells = <0>;
0019
0020 cpu@0 {
0021 compatible = "qcom,scorpion";
0022 enable-method = "qcom,gcc-msm8660";
0023 device_type = "cpu";
0024 reg = <0>;
0025 next-level-cache = <&L2>;
0026 };
0027
0028 cpu@1 {
0029 compatible = "qcom,scorpion";
0030 enable-method = "qcom,gcc-msm8660";
0031 device_type = "cpu";
0032 reg = <1>;
0033 next-level-cache = <&L2>;
0034 };
0035
0036 L2: l2-cache {
0037 compatible = "cache";
0038 cache-level = <2>;
0039 };
0040 };
0041
0042 memory {
0043 device_type = "memory";
0044 reg = <0x0 0x0>;
0045 };
0046
0047 cpu-pmu {
0048 compatible = "qcom,scorpion-mp-pmu";
0049 interrupts = <1 9 0x304>;
0050 };
0051
0052 clocks {
0053 cxo_board {
0054 compatible = "fixed-clock";
0055 #clock-cells = <0>;
0056 clock-frequency = <19200000>;
0057 };
0058
0059 pxo_board: pxo_board {
0060 compatible = "fixed-clock";
0061 #clock-cells = <0>;
0062 clock-frequency = <27000000>;
0063 };
0064
0065 sleep_clk {
0066 compatible = "fixed-clock";
0067 #clock-cells = <0>;
0068 clock-frequency = <32768>;
0069 };
0070 };
0071
0072 /*
0073 * These channels from the ADC are simply hardware monitors.
0074 * That is why the ADC is referred to as "HKADC" - HouseKeeping
0075 * ADC.
0076 */
0077 iio-hwmon {
0078 compatible = "iio-hwmon";
0079 io-channels = <&xoadc 0x00 0x01>, /* Battery */
0080 <&xoadc 0x00 0x02>, /* DC in (charger) */
0081 <&xoadc 0x00 0x04>, /* VPH the main system voltage */
0082 <&xoadc 0x00 0x0b>, /* Die temperature */
0083 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
0084 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
0085 <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
0086 };
0087
0088 soc: soc {
0089 #address-cells = <1>;
0090 #size-cells = <1>;
0091 ranges;
0092 compatible = "simple-bus";
0093
0094 intc: interrupt-controller@2080000 {
0095 compatible = "qcom,msm-8660-qgic";
0096 interrupt-controller;
0097 #interrupt-cells = <3>;
0098 reg = < 0x02080000 0x1000 >,
0099 < 0x02081000 0x1000 >;
0100 };
0101
0102 timer@2000000 {
0103 compatible = "qcom,scss-timer", "qcom,msm-timer";
0104 interrupts = <1 0 0x301>,
0105 <1 1 0x301>,
0106 <1 2 0x301>;
0107 reg = <0x02000000 0x100>;
0108 clock-frequency = <27000000>,
0109 <32768>;
0110 cpu-offset = <0x40000>;
0111 };
0112
0113 tlmm: pinctrl@800000 {
0114 compatible = "qcom,msm8660-pinctrl";
0115 reg = <0x800000 0x4000>;
0116
0117 gpio-controller;
0118 gpio-ranges = <&tlmm 0 0 173>;
0119 #gpio-cells = <2>;
0120 interrupts = <0 16 0x4>;
0121 interrupt-controller;
0122 #interrupt-cells = <2>;
0123
0124 };
0125
0126 gcc: clock-controller@900000 {
0127 compatible = "qcom,gcc-msm8660";
0128 #clock-cells = <1>;
0129 #power-domain-cells = <1>;
0130 #reset-cells = <1>;
0131 reg = <0x900000 0x4000>;
0132 };
0133
0134 gsbi6: gsbi@16500000 {
0135 compatible = "qcom,gsbi-v1.0.0";
0136 cell-index = <12>;
0137 reg = <0x16500000 0x100>;
0138 clocks = <&gcc GSBI6_H_CLK>;
0139 clock-names = "iface";
0140 #address-cells = <1>;
0141 #size-cells = <1>;
0142 ranges;
0143 status = "disabled";
0144
0145 syscon-tcsr = <&tcsr>;
0146
0147 gsbi6_serial: serial@16540000 {
0148 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
0149 reg = <0x16540000 0x1000>,
0150 <0x16500000 0x1000>;
0151 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
0152 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
0153 clock-names = "core", "iface";
0154 status = "disabled";
0155 };
0156
0157 gsbi6_i2c: i2c@16580000 {
0158 compatible = "qcom,i2c-qup-v1.1.1";
0159 reg = <0x16580000 0x1000>;
0160 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
0161 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
0162 clock-names = "core", "iface";
0163 #address-cells = <1>;
0164 #size-cells = <0>;
0165 status = "disabled";
0166 };
0167 };
0168
0169 gsbi7: gsbi@16600000 {
0170 compatible = "qcom,gsbi-v1.0.0";
0171 cell-index = <12>;
0172 reg = <0x16600000 0x100>;
0173 clocks = <&gcc GSBI7_H_CLK>;
0174 clock-names = "iface";
0175 #address-cells = <1>;
0176 #size-cells = <1>;
0177 ranges;
0178 status = "disabled";
0179
0180 syscon-tcsr = <&tcsr>;
0181
0182 gsbi7_serial: serial@16640000 {
0183 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
0184 reg = <0x16640000 0x1000>,
0185 <0x16600000 0x1000>;
0186 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
0187 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
0188 clock-names = "core", "iface";
0189 status = "disabled";
0190 };
0191
0192 gsbi7_i2c: i2c@16680000 {
0193 compatible = "qcom,i2c-qup-v1.1.1";
0194 reg = <0x16680000 0x1000>;
0195 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
0196 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
0197 clock-names = "core", "iface";
0198 #address-cells = <1>;
0199 #size-cells = <0>;
0200 status = "disabled";
0201 };
0202 };
0203
0204 gsbi8: gsbi@19800000 {
0205 compatible = "qcom,gsbi-v1.0.0";
0206 cell-index = <12>;
0207 reg = <0x19800000 0x100>;
0208 clocks = <&gcc GSBI8_H_CLK>;
0209 clock-names = "iface";
0210 #address-cells = <1>;
0211 #size-cells = <1>;
0212 ranges;
0213
0214 syscon-tcsr = <&tcsr>;
0215 status = "disabled";
0216
0217 gsbi8_i2c: i2c@19880000 {
0218 compatible = "qcom,i2c-qup-v1.1.1";
0219 reg = <0x19880000 0x1000>;
0220 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
0221 clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
0222 clock-names = "core", "iface";
0223 #address-cells = <1>;
0224 #size-cells = <0>;
0225 status = "disabled";
0226 };
0227 };
0228
0229 gsbi12: gsbi@19c00000 {
0230 compatible = "qcom,gsbi-v1.0.0";
0231 cell-index = <12>;
0232 reg = <0x19c00000 0x100>;
0233 clocks = <&gcc GSBI12_H_CLK>;
0234 clock-names = "iface";
0235 #address-cells = <1>;
0236 #size-cells = <1>;
0237 ranges;
0238
0239 syscon-tcsr = <&tcsr>;
0240
0241 gsbi12_serial: serial@19c40000 {
0242 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
0243 reg = <0x19c40000 0x1000>,
0244 <0x19c00000 0x1000>;
0245 interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>;
0246 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
0247 clock-names = "core", "iface";
0248 status = "disabled";
0249 };
0250
0251 gsbi12_i2c: i2c@19c80000 {
0252 compatible = "qcom,i2c-qup-v1.1.1";
0253 reg = <0x19c80000 0x1000>;
0254 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
0255 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
0256 clock-names = "core", "iface";
0257 #address-cells = <1>;
0258 #size-cells = <0>;
0259 status = "disabled";
0260 };
0261 };
0262
0263 external-bus@1a100000 {
0264 compatible = "qcom,msm8660-ebi2";
0265 #address-cells = <2>;
0266 #size-cells = <1>;
0267 ranges = <0 0x0 0x1a800000 0x00800000>,
0268 <1 0x0 0x1b000000 0x00800000>,
0269 <2 0x0 0x1b800000 0x00800000>,
0270 <3 0x0 0x1d000000 0x08000000>,
0271 <4 0x0 0x1c800000 0x00800000>,
0272 <5 0x0 0x1c000000 0x00800000>;
0273 reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
0274 reg-names = "ebi2", "xmem";
0275 clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
0276 clock-names = "ebi2x", "ebi2";
0277 status = "disabled";
0278 };
0279
0280 qcom,ssbi@500000 {
0281 compatible = "qcom,ssbi";
0282 reg = <0x500000 0x1000>;
0283 qcom,controller-type = "pmic-arbiter";
0284
0285 pm8058: pmic@0 {
0286 compatible = "qcom,pm8058";
0287 interrupt-parent = <&tlmm>;
0288 interrupts = <88 8>;
0289 #interrupt-cells = <2>;
0290 interrupt-controller;
0291 #address-cells = <1>;
0292 #size-cells = <0>;
0293
0294 pm8058_gpio: gpio@150 {
0295 compatible = "qcom,pm8058-gpio",
0296 "qcom,ssbi-gpio";
0297 reg = <0x150>;
0298 interrupt-controller;
0299 #interrupt-cells = <2>;
0300 gpio-controller;
0301 gpio-ranges = <&pm8058_gpio 0 0 44>;
0302 #gpio-cells = <2>;
0303
0304 };
0305
0306 pm8058_mpps: mpps@50 {
0307 compatible = "qcom,pm8058-mpp",
0308 "qcom,ssbi-mpp";
0309 reg = <0x50>;
0310 gpio-controller;
0311 #gpio-cells = <2>;
0312 gpio-ranges = <&pm8058_mpps 0 0 12>;
0313 interrupt-controller;
0314 #interrupt-cells = <2>;
0315 };
0316
0317 pwrkey@1c {
0318 compatible = "qcom,pm8058-pwrkey";
0319 reg = <0x1c>;
0320 interrupt-parent = <&pm8058>;
0321 interrupts = <50 1>, <51 1>;
0322 debounce = <15625>;
0323 pull-up;
0324 };
0325
0326 keypad@148 {
0327 compatible = "qcom,pm8058-keypad";
0328 reg = <0x148>;
0329 interrupt-parent = <&pm8058>;
0330 interrupts = <74 1>, <75 1>;
0331 debounce = <15>;
0332 scan-delay = <32>;
0333 row-hold = <91500>;
0334 };
0335
0336 xoadc: xoadc@197 {
0337 compatible = "qcom,pm8058-adc";
0338 reg = <0x197>;
0339 interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
0340 #address-cells = <2>;
0341 #size-cells = <0>;
0342 #io-channel-cells = <2>;
0343
0344 vcoin: adc-channel@0 {
0345 reg = <0x00 0x00>;
0346 };
0347 vbat: adc-channel@1 {
0348 reg = <0x00 0x01>;
0349 };
0350 dcin: adc-channel@2 {
0351 reg = <0x00 0x02>;
0352 };
0353 ichg: adc-channel@3 {
0354 reg = <0x00 0x03>;
0355 };
0356 vph_pwr: adc-channel@4 {
0357 reg = <0x00 0x04>;
0358 };
0359 usb_vbus: adc-channel@a {
0360 reg = <0x00 0x0a>;
0361 };
0362 die_temp: adc-channel@b {
0363 reg = <0x00 0x0b>;
0364 };
0365 ref_625mv: adc-channel@c {
0366 reg = <0x00 0x0c>;
0367 };
0368 ref_1250mv: adc-channel@d {
0369 reg = <0x00 0x0d>;
0370 };
0371 ref_325mv: adc-channel@e {
0372 reg = <0x00 0x0e>;
0373 };
0374 ref_muxoff: adc-channel@f {
0375 reg = <0x00 0x0f>;
0376 };
0377 };
0378
0379 rtc@1e8 {
0380 compatible = "qcom,pm8058-rtc";
0381 reg = <0x1e8>;
0382 interrupt-parent = <&pm8058>;
0383 interrupts = <39 1>;
0384 allow-set-time;
0385 };
0386
0387 vibrator@4a {
0388 compatible = "qcom,pm8058-vib";
0389 reg = <0x4a>;
0390 };
0391 };
0392 };
0393
0394 l2cc: clock-controller@2082000 {
0395 compatible = "qcom,kpss-gcc", "syscon";
0396 reg = <0x02082000 0x1000>;
0397 };
0398
0399 rpm: rpm@104000 {
0400 compatible = "qcom,rpm-msm8660";
0401 reg = <0x00104000 0x1000>;
0402 qcom,ipc = <&l2cc 0x8 2>;
0403
0404 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
0405 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
0406 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
0407 interrupt-names = "ack", "err", "wakeup";
0408 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
0409 clock-names = "ram";
0410
0411 rpmcc: clock-controller {
0412 compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
0413 #clock-cells = <1>;
0414 clocks = <&pxo_board>;
0415 clock-names = "pxo";
0416 };
0417
0418 pm8901-regulators {
0419 compatible = "qcom,rpm-pm8901-regulators";
0420
0421 pm8901_l0: l0 {};
0422 pm8901_l1: l1 {};
0423 pm8901_l2: l2 {};
0424 pm8901_l3: l3 {};
0425 pm8901_l4: l4 {};
0426 pm8901_l5: l5 {};
0427 pm8901_l6: l6 {};
0428
0429 /* S0 and S1 Handled as SAW regulators by SPM */
0430 pm8901_s2: s2 {};
0431 pm8901_s3: s3 {};
0432 pm8901_s4: s4 {};
0433
0434 pm8901_lvs0: lvs0 {};
0435 pm8901_lvs1: lvs1 {};
0436 pm8901_lvs2: lvs2 {};
0437 pm8901_lvs3: lvs3 {};
0438
0439 pm8901_mvs: mvs {};
0440 };
0441
0442 pm8058-regulators {
0443 compatible = "qcom,rpm-pm8058-regulators";
0444
0445 pm8058_l0: l0 {};
0446 pm8058_l1: l1 {};
0447 pm8058_l2: l2 {};
0448 pm8058_l3: l3 {};
0449 pm8058_l4: l4 {};
0450 pm8058_l5: l5 {};
0451 pm8058_l6: l6 {};
0452 pm8058_l7: l7 {};
0453 pm8058_l8: l8 {};
0454 pm8058_l9: l9 {};
0455 pm8058_l10: l10 {};
0456 pm8058_l11: l11 {};
0457 pm8058_l12: l12 {};
0458 pm8058_l13: l13 {};
0459 pm8058_l14: l14 {};
0460 pm8058_l15: l15 {};
0461 pm8058_l16: l16 {};
0462 pm8058_l17: l17 {};
0463 pm8058_l18: l18 {};
0464 pm8058_l19: l19 {};
0465 pm8058_l20: l20 {};
0466 pm8058_l21: l21 {};
0467 pm8058_l22: l22 {};
0468 pm8058_l23: l23 {};
0469 pm8058_l24: l24 {};
0470 pm8058_l25: l25 {};
0471
0472 pm8058_s0: s0 {};
0473 pm8058_s1: s1 {};
0474 pm8058_s2: s2 {};
0475 pm8058_s3: s3 {};
0476 pm8058_s4: s4 {};
0477
0478 pm8058_lvs0: lvs0 {};
0479 pm8058_lvs1: lvs1 {};
0480
0481 pm8058_ncp: ncp {};
0482 };
0483 };
0484
0485 amba {
0486 compatible = "simple-bus";
0487 #address-cells = <1>;
0488 #size-cells = <1>;
0489 ranges;
0490 sdcc1: mmc@12400000 {
0491 status = "disabled";
0492 compatible = "arm,pl18x", "arm,primecell";
0493 arm,primecell-periphid = <0x00051180>;
0494 reg = <0x12400000 0x8000>;
0495 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
0496 interrupt-names = "cmd_irq";
0497 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
0498 clock-names = "mclk", "apb_pclk";
0499 bus-width = <8>;
0500 max-frequency = <48000000>;
0501 non-removable;
0502 cap-sd-highspeed;
0503 cap-mmc-highspeed;
0504 };
0505
0506 sdcc2: mmc@12140000 {
0507 status = "disabled";
0508 compatible = "arm,pl18x", "arm,primecell";
0509 arm,primecell-periphid = <0x00051180>;
0510 reg = <0x12140000 0x8000>;
0511 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0512 interrupt-names = "cmd_irq";
0513 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
0514 clock-names = "mclk", "apb_pclk";
0515 bus-width = <8>;
0516 max-frequency = <48000000>;
0517 cap-sd-highspeed;
0518 cap-mmc-highspeed;
0519 };
0520
0521 sdcc3: mmc@12180000 {
0522 compatible = "arm,pl18x", "arm,primecell";
0523 arm,primecell-periphid = <0x00051180>;
0524 status = "disabled";
0525 reg = <0x12180000 0x8000>;
0526 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
0527 interrupt-names = "cmd_irq";
0528 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
0529 clock-names = "mclk", "apb_pclk";
0530 bus-width = <4>;
0531 cap-sd-highspeed;
0532 cap-mmc-highspeed;
0533 max-frequency = <48000000>;
0534 no-1-8-v;
0535 };
0536
0537 sdcc4: mmc@121c0000 {
0538 compatible = "arm,pl18x", "arm,primecell";
0539 arm,primecell-periphid = <0x00051180>;
0540 status = "disabled";
0541 reg = <0x121c0000 0x8000>;
0542 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
0543 interrupt-names = "cmd_irq";
0544 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
0545 clock-names = "mclk", "apb_pclk";
0546 bus-width = <4>;
0547 max-frequency = <48000000>;
0548 cap-sd-highspeed;
0549 cap-mmc-highspeed;
0550 };
0551
0552 sdcc5: mmc@12200000 {
0553 compatible = "arm,pl18x", "arm,primecell";
0554 arm,primecell-periphid = <0x00051180>;
0555 status = "disabled";
0556 reg = <0x12200000 0x8000>;
0557 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
0558 interrupt-names = "cmd_irq";
0559 clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
0560 clock-names = "mclk", "apb_pclk";
0561 bus-width = <4>;
0562 cap-sd-highspeed;
0563 cap-mmc-highspeed;
0564 max-frequency = <48000000>;
0565 };
0566 };
0567
0568 tcsr: syscon@1a400000 {
0569 compatible = "qcom,tcsr-msm8660", "syscon";
0570 reg = <0x1a400000 0x100>;
0571 };
0572 };
0573
0574 };
