0001 /*
0002 * Device Tree Source for Qualcomm MDM9615 SoC
0003 *
0004 * Copyright (C) 2016 BayLibre, SAS.
0005 * Author : Neil Armstrong <narmstrong@baylibre.com>
0006 *
0007 * This file is dual-licensed: you can use it either under the terms
0008 * of the GPL or the X11 license, at your option. Note that this dual
0009 * licensing only applies to this file, and not this project as a
0010 * whole.
0011 *
0012 * a) This file is free software; you can redistribute it and/or
0013 * modify it under the terms of the GNU General Public License as
0014 * published by the Free Software Foundation; either version 2 of the
0015 * License, or (at your option) any later version.
0016 *
0017 * This file is distributed in the hope that it will be useful,
0018 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0019 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0020 * GNU General Public License for more details.
0021 *
0022 * Or, alternatively,
0023 *
0024 * b) Permission is hereby granted, free of charge, to any person
0025 * obtaining a copy of this software and associated documentation
0026 * files (the "Software"), to deal in the Software without
0027 * restriction, including without limitation the rights to use,
0028 * copy, modify, merge, publish, distribute, sublicense, and/or
0029 * sell copies of the Software, and to permit persons to whom the
0030 * Software is furnished to do so, subject to the following
0031 * conditions:
0032 *
0033 * The above copyright notice and this permission notice shall be
0034 * included in all copies or substantial portions of the Software.
0035 *
0036 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0037 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0038 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0039 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0040 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0041 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0042 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0043 * OTHER DEALINGS IN THE SOFTWARE.
0044 */
0045
0046 /dts-v1/;
0047
0048 #include <dt-bindings/interrupt-controller/arm-gic.h>
0049 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
0050 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
0051 #include <dt-bindings/mfd/qcom-rpm.h>
0052 #include <dt-bindings/soc/qcom,gsbi.h>
0053
0054 / {
0055 #address-cells = <1>;
0056 #size-cells = <1>;
0057 model = "Qualcomm MDM9615";
0058 compatible = "qcom,mdm9615";
0059 interrupt-parent = <&intc>;
0060
0061 cpus {
0062 #address-cells = <1>;
0063 #size-cells = <0>;
0064
0065 cpu0: cpu@0 {
0066 compatible = "arm,cortex-a5";
0067 device_type = "cpu";
0068 next-level-cache = <&L2>;
0069 };
0070 };
0071
0072 cpu-pmu {
0073 compatible = "arm,cortex-a5-pmu";
0074 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
0075 };
0076
0077 clocks {
0078 cxo_board {
0079 compatible = "fixed-clock";
0080 #clock-cells = <0>;
0081 clock-frequency = <19200000>;
0082 };
0083 };
0084
0085 regulators {
0086 vsdcc_fixed: vsdcc-regulator {
0087 compatible = "regulator-fixed";
0088 regulator-name = "SDCC Power";
0089 regulator-min-microvolt = <2700000>;
0090 regulator-max-microvolt = <2700000>;
0091 regulator-always-on;
0092 };
0093 };
0094
0095 soc: soc {
0096 #address-cells = <1>;
0097 #size-cells = <1>;
0098 ranges;
0099 compatible = "simple-bus";
0100
0101 L2: cache-controller@2040000 {
0102 compatible = "arm,pl310-cache";
0103 reg = <0x02040000 0x1000>;
0104 arm,data-latency = <2 2 0>;
0105 cache-unified;
0106 cache-level = <2>;
0107 };
0108
0109 intc: interrupt-controller@2000000 {
0110 compatible = "qcom,msm-qgic2";
0111 interrupt-controller;
0112 #interrupt-cells = <3>;
0113 reg = <0x02000000 0x1000>,
0114 <0x02002000 0x1000>;
0115 };
0116
0117 timer@200a000 {
0118 compatible = "qcom,kpss-timer", "qcom,msm-timer";
0119 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
0120 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
0121 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
0122 reg = <0x0200a000 0x100>;
0123 clock-frequency = <27000000>,
0124 <32768>;
0125 cpu-offset = <0x80000>;
0126 };
0127
0128 msmgpio: pinctrl@800000 {
0129 compatible = "qcom,mdm9615-pinctrl";
0130 gpio-controller;
0131 gpio-ranges = <&msmgpio 0 0 88>;
0132 #gpio-cells = <2>;
0133 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0134 interrupt-controller;
0135 #interrupt-cells = <2>;
0136 reg = <0x800000 0x4000>;
0137 };
0138
0139 gcc: clock-controller@900000 {
0140 compatible = "qcom,gcc-mdm9615";
0141 #clock-cells = <1>;
0142 #power-domain-cells = <1>;
0143 #reset-cells = <1>;
0144 reg = <0x900000 0x4000>;
0145 };
0146
0147 lcc: clock-controller@28000000 {
0148 compatible = "qcom,lcc-mdm9615";
0149 reg = <0x28000000 0x1000>;
0150 #clock-cells = <1>;
0151 #reset-cells = <1>;
0152 };
0153
0154 l2cc: clock-controller@2011000 {
0155 compatible = "qcom,kpss-gcc", "syscon";
0156 reg = <0x02011000 0x1000>;
0157 };
0158
0159 rng@1a500000 {
0160 compatible = "qcom,prng";
0161 reg = <0x1a500000 0x200>;
0162 clocks = <&gcc PRNG_CLK>;
0163 clock-names = "core";
0164 assigned-clocks = <&gcc PRNG_CLK>;
0165 assigned-clock-rates = <32000000>;
0166 };
0167
0168 gsbi2: gsbi@16100000 {
0169 compatible = "qcom,gsbi-v1.0.0";
0170 cell-index = <2>;
0171 reg = <0x16100000 0x100>;
0172 clocks = <&gcc GSBI2_H_CLK>;
0173 clock-names = "iface";
0174 status = "disabled";
0175 #address-cells = <1>;
0176 #size-cells = <1>;
0177 ranges;
0178
0179 gsbi2_i2c: i2c@16180000 {
0180 compatible = "qcom,i2c-qup-v1.1.1";
0181 #address-cells = <1>;
0182 #size-cells = <0>;
0183 reg = <0x16180000 0x1000>;
0184 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
0185
0186 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
0187 clock-names = "core", "iface";
0188 status = "disabled";
0189 };
0190 };
0191
0192 gsbi3: gsbi@16200000 {
0193 compatible = "qcom,gsbi-v1.0.0";
0194 cell-index = <3>;
0195 reg = <0x16200000 0x100>;
0196 clocks = <&gcc GSBI3_H_CLK>;
0197 clock-names = "iface";
0198 status = "disabled";
0199 #address-cells = <1>;
0200 #size-cells = <1>;
0201 ranges;
0202
0203 gsbi3_spi: spi@16280000 {
0204 compatible = "qcom,spi-qup-v1.1.1";
0205 #address-cells = <1>;
0206 #size-cells = <0>;
0207 reg = <0x16280000 0x1000>;
0208 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
0209 spi-max-frequency = <24000000>;
0210
0211 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
0212 clock-names = "core", "iface";
0213 status = "disabled";
0214 };
0215 };
0216
0217 gsbi4: gsbi@16300000 {
0218 compatible = "qcom,gsbi-v1.0.0";
0219 cell-index = <4>;
0220 reg = <0x16300000 0x100>;
0221 clocks = <&gcc GSBI4_H_CLK>;
0222 clock-names = "iface";
0223 status = "disabled";
0224 #address-cells = <1>;
0225 #size-cells = <1>;
0226 ranges;
0227
0228 syscon-tcsr = <&tcsr>;
0229
0230 gsbi4_serial: serial@16340000 {
0231 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
0232 reg = <0x16340000 0x1000>,
0233 <0x16300000 0x1000>;
0234 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
0235 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
0236 clock-names = "core", "iface";
0237 status = "disabled";
0238 };
0239 };
0240
0241 gsbi5: gsbi@16400000 {
0242 compatible = "qcom,gsbi-v1.0.0";
0243 cell-index = <5>;
0244 reg = <0x16400000 0x100>;
0245 clocks = <&gcc GSBI5_H_CLK>;
0246 clock-names = "iface";
0247 status = "disabled";
0248 #address-cells = <1>;
0249 #size-cells = <1>;
0250 ranges;
0251
0252 syscon-tcsr = <&tcsr>;
0253
0254 gsbi5_i2c: i2c@16480000 {
0255 compatible = "qcom,i2c-qup-v1.1.1";
0256 #address-cells = <1>;
0257 #size-cells = <0>;
0258 reg = <0x16480000 0x1000>;
0259 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
0260
0261 /* QUP clock is not initialized, set rate */
0262 assigned-clocks = <&gcc GSBI5_QUP_CLK>;
0263 assigned-clock-rates = <24000000>;
0264
0265 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
0266 clock-names = "core", "iface";
0267 status = "disabled";
0268 };
0269
0270 gsbi5_serial: serial@16440000 {
0271 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
0272 reg = <0x16440000 0x1000>,
0273 <0x16400000 0x1000>;
0274 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
0275 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
0276 clock-names = "core", "iface";
0277 status = "disabled";
0278 };
0279 };
0280
0281 qcom,ssbi@500000 {
0282 compatible = "qcom,ssbi";
0283 reg = <0x500000 0x1000>;
0284 qcom,controller-type = "pmic-arbiter";
0285
0286 pmicintc: pmic@0 {
0287 compatible = "qcom,pm8018", "qcom,pm8921";
0288 interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>;
0289 #interrupt-cells = <2>;
0290 interrupt-controller;
0291 #address-cells = <1>;
0292 #size-cells = <0>;
0293
0294 pwrkey@1c {
0295 compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey";
0296 reg = <0x1c>;
0297 interrupt-parent = <&pmicintc>;
0298 interrupts = <50 IRQ_TYPE_EDGE_RISING>,
0299 <51 IRQ_TYPE_EDGE_RISING>;
0300 debounce = <15625>;
0301 pull-up;
0302 };
0303
0304 pmicmpp: mpps@50 {
0305 compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
0306 interrupt-controller;
0307 #interrupt-cells = <2>;
0308 reg = <0x50>;
0309 gpio-controller;
0310 #gpio-cells = <2>;
0311 gpio-ranges = <&pmicmpp 0 0 6>;
0312 };
0313
0314 rtc@11d {
0315 compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc";
0316 interrupt-parent = <&pmicintc>;
0317 interrupts = <39 IRQ_TYPE_EDGE_RISING>;
0318 reg = <0x11d>;
0319 allow-set-time;
0320 };
0321
0322 pmicgpio: gpio@150 {
0323 compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
0324 reg = <0x150>;
0325 interrupt-controller;
0326 #interrupt-cells = <2>;
0327 gpio-controller;
0328 gpio-ranges = <&pmicgpio 0 0 6>;
0329 #gpio-cells = <2>;
0330 };
0331 };
0332 };
0333
0334 sdcc1bam: dma-controller@12182000{
0335 compatible = "qcom,bam-v1.3.0";
0336 reg = <0x12182000 0x8000>;
0337 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0338 clocks = <&gcc SDC1_H_CLK>;
0339 clock-names = "bam_clk";
0340 #dma-cells = <1>;
0341 qcom,ee = <0>;
0342 };
0343
0344 sdcc2bam: dma-controller@12142000{
0345 compatible = "qcom,bam-v1.3.0";
0346 reg = <0x12142000 0x8000>;
0347 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0348 clocks = <&gcc SDC2_H_CLK>;
0349 clock-names = "bam_clk";
0350 #dma-cells = <1>;
0351 qcom,ee = <0>;
0352 };
0353
0354 amba {
0355 compatible = "simple-bus";
0356 #address-cells = <1>;
0357 #size-cells = <1>;
0358 ranges;
0359 sdcc1: mmc@12180000 {
0360 status = "disabled";
0361 compatible = "arm,pl18x", "arm,primecell";
0362 arm,primecell-periphid = <0x00051180>;
0363 reg = <0x12180000 0x2000>;
0364 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
0365 interrupt-names = "cmd_irq";
0366 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
0367 clock-names = "mclk", "apb_pclk";
0368 bus-width = <8>;
0369 max-frequency = <48000000>;
0370 cap-sd-highspeed;
0371 cap-mmc-highspeed;
0372 vmmc-supply = <&vsdcc_fixed>;
0373 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
0374 dma-names = "tx", "rx";
0375 assigned-clocks = <&gcc SDC1_CLK>;
0376 assigned-clock-rates = <400000>;
0377 };
0378
0379 sdcc2: mmc@12140000 {
0380 compatible = "arm,pl18x", "arm,primecell";
0381 arm,primecell-periphid = <0x00051180>;
0382 status = "disabled";
0383 reg = <0x12140000 0x2000>;
0384 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0385 interrupt-names = "cmd_irq";
0386 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
0387 clock-names = "mclk", "apb_pclk";
0388 bus-width = <4>;
0389 cap-sd-highspeed;
0390 cap-mmc-highspeed;
0391 max-frequency = <48000000>;
0392 no-1-8-v;
0393 vmmc-supply = <&vsdcc_fixed>;
0394 dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
0395 dma-names = "tx", "rx";
0396 assigned-clocks = <&gcc SDC2_CLK>;
0397 assigned-clock-rates = <400000>;
0398 };
0399 };
0400
0401 tcsr: syscon@1a400000 {
0402 compatible = "qcom,tcsr-mdm9615", "syscon";
0403 reg = <0x1a400000 0x100>;
0404 };
0405
0406 rpm: rpm@108000 {
0407 compatible = "qcom,rpm-mdm9615";
0408 reg = <0x108000 0x1000>;
0409
0410 qcom,ipc = <&l2cc 0x8 2>;
0411
0412 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
0413 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
0414 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
0415 interrupt-names = "ack", "err", "wakeup";
0416
0417 regulators {
0418 compatible = "qcom,rpm-pm8018-regulators";
0419
0420 vin_lvs1-supply = <&pm8018_s3>;
0421
0422 vdd_l7-supply = <&pm8018_s4>;
0423 vdd_l8-supply = <&pm8018_s3>;
0424 vdd_l9_l10_l11_l12-supply = <&pm8018_s5>;
0425
0426 /* Buck SMPS */
0427 pm8018_s1: s1 {
0428 regulator-min-microvolt = <500000>;
0429 regulator-max-microvolt = <1150000>;
0430 qcom,switch-mode-frequency = <1600000>;
0431 bias-pull-down;
0432 };
0433
0434 pm8018_s2: s2 {
0435 regulator-min-microvolt = <1225000>;
0436 regulator-max-microvolt = <1300000>;
0437 qcom,switch-mode-frequency = <1600000>;
0438 bias-pull-down;
0439 };
0440
0441 pm8018_s3: s3 {
0442 regulator-always-on;
0443 regulator-min-microvolt = <1800000>;
0444 regulator-max-microvolt = <1800000>;
0445 qcom,switch-mode-frequency = <1600000>;
0446 bias-pull-down;
0447 };
0448
0449 pm8018_s4: s4 {
0450 regulator-min-microvolt = <2100000>;
0451 regulator-max-microvolt = <2200000>;
0452 qcom,switch-mode-frequency = <1600000>;
0453 bias-pull-down;
0454 };
0455
0456 pm8018_s5: s5 {
0457 regulator-always-on;
0458 regulator-min-microvolt = <1350000>;
0459 regulator-max-microvolt = <1350000>;
0460 qcom,switch-mode-frequency = <1600000>;
0461 bias-pull-down;
0462 };
0463
0464 /* PMOS LDO */
0465 pm8018_l2: l2 {
0466 regulator-always-on;
0467 regulator-min-microvolt = <1800000>;
0468 regulator-max-microvolt = <1800000>;
0469 bias-pull-down;
0470 };
0471
0472 pm8018_l3: l3 {
0473 regulator-always-on;
0474 regulator-min-microvolt = <1800000>;
0475 regulator-max-microvolt = <1800000>;
0476 bias-pull-down;
0477 };
0478
0479 pm8018_l4: l4 {
0480 regulator-min-microvolt = <3300000>;
0481 regulator-max-microvolt = <3300000>;
0482 bias-pull-down;
0483 };
0484
0485 pm8018_l5: l5 {
0486 regulator-min-microvolt = <2850000>;
0487 regulator-max-microvolt = <2850000>;
0488 bias-pull-down;
0489 };
0490
0491 pm8018_l6: l6 {
0492 regulator-min-microvolt = <1800000>;
0493 regulator-max-microvolt = <2850000>;
0494 bias-pull-down;
0495 };
0496
0497 pm8018_l7: l7 {
0498 regulator-min-microvolt = <1850000>;
0499 regulator-max-microvolt = <1900000>;
0500 bias-pull-down;
0501 };
0502
0503 pm8018_l8: l8 {
0504 regulator-min-microvolt = <1200000>;
0505 regulator-max-microvolt = <1200000>;
0506 bias-pull-down;
0507 };
0508
0509 pm8018_l9: l9 {
0510 regulator-min-microvolt = <750000>;
0511 regulator-max-microvolt = <1150000>;
0512 bias-pull-down;
0513 };
0514
0515 pm8018_l10: l10 {
0516 regulator-min-microvolt = <1050000>;
0517 regulator-max-microvolt = <1050000>;
0518 bias-pull-down;
0519 };
0520
0521 pm8018_l11: l11 {
0522 regulator-min-microvolt = <1050000>;
0523 regulator-max-microvolt = <1050000>;
0524 bias-pull-down;
0525 };
0526
0527 pm8018_l12: l12 {
0528 regulator-min-microvolt = <1050000>;
0529 regulator-max-microvolt = <1050000>;
0530 bias-pull-down;
0531 };
0532
0533 pm8018_l13: l13 {
0534 regulator-min-microvolt = <1850000>;
0535 regulator-max-microvolt = <2950000>;
0536 bias-pull-down;
0537 };
0538
0539 pm8018_l14: l14 {
0540 regulator-min-microvolt = <2850000>;
0541 regulator-max-microvolt = <2850000>;
0542 bias-pull-down;
0543 };
0544
0545 /* Low Voltage Switch */
0546 pm8018_lvs1: lvs1 {
0547 bias-pull-down;
0548 };
0549 };
0550 };
0551 };
0552 };
