0001 // SPDX-License-Identifier: GPL-2.0
0002 /dts-v1/;
0003
0004 #include <dt-bindings/interrupt-controller/arm-gic.h>
0005 #include <dt-bindings/mfd/qcom-rpm.h>
0006 #include <dt-bindings/clock/qcom,rpmcc.h>
0007 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
0008 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
0011 #include <dt-bindings/soc/qcom,gsbi.h>
0012 #include <dt-bindings/interrupt-controller/arm-gic.h>
0013
0014 / {
0015 #address-cells = <1>;
0016 #size-cells = <1>;
0017 model = "Qualcomm IPQ8064";
0018 compatible = "qcom,ipq8064";
0019 interrupt-parent = <&intc>;
0020
0021 cpus {
0022 #address-cells = <1>;
0023 #size-cells = <0>;
0024
0025 cpu0: cpu@0 {
0026 compatible = "qcom,krait";
0027 enable-method = "qcom,kpss-acc-v1";
0028 device_type = "cpu";
0029 reg = <0>;
0030 next-level-cache = <&L2>;
0031 qcom,acc = <&acc0>;
0032 qcom,saw = <&saw0>;
0033 };
0034
0035 cpu1: cpu@1 {
0036 compatible = "qcom,krait";
0037 enable-method = "qcom,kpss-acc-v1";
0038 device_type = "cpu";
0039 reg = <1>;
0040 next-level-cache = <&L2>;
0041 qcom,acc = <&acc1>;
0042 qcom,saw = <&saw1>;
0043 };
0044
0045 L2: l2-cache {
0046 compatible = "cache";
0047 cache-level = <2>;
0048 };
0049 };
0050
0051 thermal-zones {
0052 sensor0-thermal {
0053 polling-delay-passive = <0>;
0054 polling-delay = <0>;
0055 thermal-sensors = <&tsens 0>;
0056
0057 trips {
0058 cpu-critical {
0059 temperature = <105000>;
0060 hysteresis = <2000>;
0061 type = "critical";
0062 };
0063
0064 cpu-hot {
0065 temperature = <95000>;
0066 hysteresis = <2000>;
0067 type = "hot";
0068 };
0069 };
0070 };
0071
0072 sensor1-thermal {
0073 polling-delay-passive = <0>;
0074 polling-delay = <0>;
0075 thermal-sensors = <&tsens 1>;
0076
0077 trips {
0078 cpu-critical {
0079 temperature = <105000>;
0080 hysteresis = <2000>;
0081 type = "critical";
0082 };
0083
0084 cpu-hot {
0085 temperature = <95000>;
0086 hysteresis = <2000>;
0087 type = "hot";
0088 };
0089 };
0090 };
0091
0092 sensor2-thermal {
0093 polling-delay-passive = <0>;
0094 polling-delay = <0>;
0095 thermal-sensors = <&tsens 2>;
0096
0097 trips {
0098 cpu-critical {
0099 temperature = <105000>;
0100 hysteresis = <2000>;
0101 type = "critical";
0102 };
0103
0104 cpu-hot {
0105 temperature = <95000>;
0106 hysteresis = <2000>;
0107 type = "hot";
0108 };
0109 };
0110 };
0111
0112 sensor3-thermal {
0113 polling-delay-passive = <0>;
0114 polling-delay = <0>;
0115 thermal-sensors = <&tsens 3>;
0116
0117 trips {
0118 cpu-critical {
0119 temperature = <105000>;
0120 hysteresis = <2000>;
0121 type = "critical";
0122 };
0123
0124 cpu-hot {
0125 temperature = <95000>;
0126 hysteresis = <2000>;
0127 type = "hot";
0128 };
0129 };
0130 };
0131
0132 sensor4-thermal {
0133 polling-delay-passive = <0>;
0134 polling-delay = <0>;
0135 thermal-sensors = <&tsens 4>;
0136
0137 trips {
0138 cpu-critical {
0139 temperature = <105000>;
0140 hysteresis = <2000>;
0141 type = "critical";
0142 };
0143
0144 cpu-hot {
0145 temperature = <95000>;
0146 hysteresis = <2000>;
0147 type = "hot";
0148 };
0149 };
0150 };
0151
0152 sensor5-thermal {
0153 polling-delay-passive = <0>;
0154 polling-delay = <0>;
0155 thermal-sensors = <&tsens 5>;
0156
0157 trips {
0158 cpu-critical {
0159 temperature = <105000>;
0160 hysteresis = <2000>;
0161 type = "critical";
0162 };
0163
0164 cpu-hot {
0165 temperature = <95000>;
0166 hysteresis = <2000>;
0167 type = "hot";
0168 };
0169 };
0170 };
0171
0172 sensor6-thermal {
0173 polling-delay-passive = <0>;
0174 polling-delay = <0>;
0175 thermal-sensors = <&tsens 6>;
0176
0177 trips {
0178 cpu-critical {
0179 temperature = <105000>;
0180 hysteresis = <2000>;
0181 type = "critical";
0182 };
0183
0184 cpu-hot {
0185 temperature = <95000>;
0186 hysteresis = <2000>;
0187 type = "hot";
0188 };
0189 };
0190 };
0191
0192 sensor7-thermal {
0193 polling-delay-passive = <0>;
0194 polling-delay = <0>;
0195 thermal-sensors = <&tsens 7>;
0196
0197 trips {
0198 cpu-critical {
0199 temperature = <105000>;
0200 hysteresis = <2000>;
0201 type = "critical";
0202 };
0203
0204 cpu-hot {
0205 temperature = <95000>;
0206 hysteresis = <2000>;
0207 type = "hot";
0208 };
0209 };
0210 };
0211
0212 sensor8-thermal {
0213 polling-delay-passive = <0>;
0214 polling-delay = <0>;
0215 thermal-sensors = <&tsens 8>;
0216
0217 trips {
0218 cpu-critical {
0219 temperature = <105000>;
0220 hysteresis = <2000>;
0221 type = "critical";
0222 };
0223
0224 cpu-hot {
0225 temperature = <95000>;
0226 hysteresis = <2000>;
0227 type = "hot";
0228 };
0229 };
0230 };
0231
0232 sensor9-thermal {
0233 polling-delay-passive = <0>;
0234 polling-delay = <0>;
0235 thermal-sensors = <&tsens 9>;
0236
0237 trips {
0238 cpu-critical {
0239 temperature = <105000>;
0240 hysteresis = <2000>;
0241 type = "critical";
0242 };
0243
0244 cpu-hot {
0245 temperature = <95000>;
0246 hysteresis = <2000>;
0247 type = "hot";
0248 };
0249 };
0250 };
0251
0252 sensor10-thermal {
0253 polling-delay-passive = <0>;
0254 polling-delay = <0>;
0255 thermal-sensors = <&tsens 10>;
0256
0257 trips {
0258 cpu-critical {
0259 temperature = <105000>;
0260 hysteresis = <2000>;
0261 type = "critical";
0262 };
0263
0264 cpu-hot {
0265 temperature = <95000>;
0266 hysteresis = <2000>;
0267 type = "hot";
0268 };
0269 };
0270 };
0271 };
0272
0273 memory {
0274 device_type = "memory";
0275 reg = <0x0 0x0>;
0276 };
0277
0278 cpu-pmu {
0279 compatible = "qcom,krait-pmu";
0280 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
0281 IRQ_TYPE_LEVEL_HIGH)>;
0282 };
0283
0284 reserved-memory {
0285 #address-cells = <1>;
0286 #size-cells = <1>;
0287 ranges;
0288
0289 nss@40000000 {
0290 reg = <0x40000000 0x1000000>;
0291 no-map;
0292 };
0293
0294 smem: smem@41000000 {
0295 compatible = "qcom,smem";
0296 reg = <0x41000000 0x200000>;
0297 no-map;
0298
0299 hwlocks = <&sfpb_mutex 3>;
0300 };
0301 };
0302
0303 clocks {
0304 cxo_board: cxo_board {
0305 compatible = "fixed-clock";
0306 #clock-cells = <0>;
0307 clock-frequency = <25000000>;
0308 };
0309
0310 pxo_board: pxo_board {
0311 compatible = "fixed-clock";
0312 #clock-cells = <0>;
0313 clock-frequency = <25000000>;
0314 };
0315
0316 sleep_clk: sleep_clk {
0317 compatible = "fixed-clock";
0318 clock-frequency = <32768>;
0319 #clock-cells = <0>;
0320 };
0321 };
0322
0323 firmware {
0324 scm {
0325 compatible = "qcom,scm-ipq806x", "qcom,scm";
0326 };
0327 };
0328
0329 soc: soc {
0330 #address-cells = <1>;
0331 #size-cells = <1>;
0332 ranges;
0333 compatible = "simple-bus";
0334
0335 lpass@28100000 {
0336 compatible = "qcom,lpass-cpu";
0337 status = "disabled";
0338 clocks = <&lcc AHBIX_CLK>,
0339 <&lcc MI2S_OSR_CLK>,
0340 <&lcc MI2S_BIT_CLK>;
0341 clock-names = "ahbix-clk",
0342 "mi2s-osr-clk",
0343 "mi2s-bit-clk";
0344 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
0345 interrupt-names = "lpass-irq-lpaif";
0346 reg = <0x28100000 0x10000>;
0347 reg-names = "lpass-lpaif";
0348 };
0349
0350 qcom_pinmux: pinmux@800000 {
0351 compatible = "qcom,ipq8064-pinctrl";
0352 reg = <0x800000 0x4000>;
0353
0354 gpio-controller;
0355 gpio-ranges = <&qcom_pinmux 0 0 69>;
0356 #gpio-cells = <2>;
0357 interrupt-controller;
0358 #interrupt-cells = <2>;
0359 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0360
0361 pcie0_pins: pcie0_pinmux {
0362 mux {
0363 pins = "gpio3";
0364 function = "pcie1_rst";
0365 drive-strength = <12>;
0366 bias-disable;
0367 };
0368 };
0369
0370 pcie1_pins: pcie1_pinmux {
0371 mux {
0372 pins = "gpio48";
0373 function = "pcie2_rst";
0374 drive-strength = <12>;
0375 bias-disable;
0376 };
0377 };
0378
0379 pcie2_pins: pcie2_pinmux {
0380 mux {
0381 pins = "gpio63";
0382 function = "pcie3_rst";
0383 drive-strength = <12>;
0384 bias-disable;
0385 };
0386 };
0387
0388 i2c4_pins: i2c4-default {
0389 pins = "gpio12", "gpio13";
0390 function = "gsbi4";
0391 drive-strength = <12>;
0392 bias-disable;
0393 };
0394
0395 spi_pins: spi_pins {
0396 mux {
0397 pins = "gpio18", "gpio19", "gpio21";
0398 function = "gsbi5";
0399 drive-strength = <10>;
0400 bias-none;
0401 };
0402 };
0403
0404 leds_pins: leds_pins {
0405 mux {
0406 pins = "gpio7", "gpio8", "gpio9",
0407 "gpio26", "gpio53";
0408 function = "gpio";
0409 drive-strength = <2>;
0410 bias-pull-down;
0411 output-low;
0412 };
0413 };
0414
0415 buttons_pins: buttons_pins {
0416 mux {
0417 pins = "gpio54";
0418 drive-strength = <2>;
0419 bias-pull-up;
0420 };
0421 };
0422
0423 nand_pins: nand_pins {
0424 mux {
0425 pins = "gpio34", "gpio35", "gpio36",
0426 "gpio37", "gpio38", "gpio39",
0427 "gpio40", "gpio41", "gpio42",
0428 "gpio43", "gpio44", "gpio45",
0429 "gpio46", "gpio47";
0430 function = "nand";
0431 drive-strength = <10>;
0432 bias-disable;
0433 };
0434
0435 pullups {
0436 pins = "gpio39";
0437 function = "nand";
0438 drive-strength = <10>;
0439 bias-pull-up;
0440 };
0441
0442 hold {
0443 pins = "gpio40", "gpio41", "gpio42",
0444 "gpio43", "gpio44", "gpio45",
0445 "gpio46", "gpio47";
0446 function = "nand";
0447 drive-strength = <10>;
0448 bias-bus-hold;
0449 };
0450 };
0451
0452 mdio0_pins: mdio0-pins {
0453 mux {
0454 pins = "gpio0", "gpio1";
0455 function = "mdio";
0456 drive-strength = <8>;
0457 bias-disable;
0458 };
0459 };
0460
0461 rgmii2_pins: rgmii2-pins {
0462 mux {
0463 pins = "gpio27", "gpio28", "gpio29",
0464 "gpio30", "gpio31", "gpio32",
0465 "gpio51", "gpio52", "gpio59",
0466 "gpio60", "gpio61", "gpio62";
0467 function = "rgmii2";
0468 drive-strength = <8>;
0469 bias-disable;
0470 };
0471 };
0472 };
0473
0474 intc: interrupt-controller@2000000 {
0475 compatible = "qcom,msm-qgic2";
0476 interrupt-controller;
0477 #interrupt-cells = <3>;
0478 reg = <0x02000000 0x1000>,
0479 <0x02002000 0x1000>;
0480 };
0481
0482 timer@200a000 {
0483 compatible = "qcom,kpss-timer",
0484 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
0485 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
0486 IRQ_TYPE_EDGE_RISING)>,
0487 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
0488 IRQ_TYPE_EDGE_RISING)>,
0489 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
0490 IRQ_TYPE_EDGE_RISING)>,
0491 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
0492 IRQ_TYPE_EDGE_RISING)>,
0493 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
0494 IRQ_TYPE_EDGE_RISING)>;
0495 reg = <0x0200a000 0x100>;
0496 clock-frequency = <25000000>,
0497 <32768>;
0498 clocks = <&sleep_clk>;
0499 clock-names = "sleep";
0500 cpu-offset = <0x80000>;
0501 };
0502
0503 acc0: clock-controller@2088000 {
0504 compatible = "qcom,kpss-acc-v1";
0505 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
0506 };
0507
0508 acc1: clock-controller@2098000 {
0509 compatible = "qcom,kpss-acc-v1";
0510 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
0511 };
0512
0513 adm_dma: dma-controller@18300000 {
0514 compatible = "qcom,adm";
0515 reg = <0x18300000 0x100000>;
0516 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
0517 #dma-cells = <1>;
0518
0519 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
0520 clock-names = "core", "iface";
0521
0522 resets = <&gcc ADM0_RESET>,
0523 <&gcc ADM0_PBUS_RESET>,
0524 <&gcc ADM0_C0_RESET>,
0525 <&gcc ADM0_C1_RESET>,
0526 <&gcc ADM0_C2_RESET>;
0527 reset-names = "clk", "pbus", "c0", "c1", "c2";
0528 qcom,ee = <0>;
0529
0530 status = "disabled";
0531 };
0532
0533 saw0: regulator@2089000 {
0534 compatible = "qcom,saw2";
0535 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
0536 regulator;
0537 };
0538
0539 saw1: regulator@2099000 {
0540 compatible = "qcom,saw2";
0541 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
0542 regulator;
0543 };
0544
0545 gsbi1: gsbi@12440000 {
0546 compatible = "qcom,gsbi-v1.0.0";
0547 reg = <0x12440000 0x100>;
0548 cell-index = <1>;
0549 clocks = <&gcc GSBI1_H_CLK>;
0550 clock-names = "iface";
0551 #address-cells = <1>;
0552 #size-cells = <1>;
0553 ranges;
0554
0555 syscon-tcsr = <&tcsr>;
0556
0557 status = "disabled";
0558
0559 gsbi1_serial: serial@12450000 {
0560 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
0561 reg = <0x12450000 0x100>,
0562 <0x12400000 0x03>;
0563 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
0564 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
0565 clock-names = "core", "iface";
0566
0567 status = "disabled";
0568 };
0569
0570 gsbi1_i2c: i2c@12460000 {
0571 compatible = "qcom,i2c-qup-v1.1.1";
0572 reg = <0x12460000 0x1000>;
0573 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
0574 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
0575 clock-names = "core", "iface";
0576 #address-cells = <1>;
0577 #size-cells = <0>;
0578
0579 status = "disabled";
0580 };
0581 };
0582
0583 gsbi2: gsbi@12480000 {
0584 compatible = "qcom,gsbi-v1.0.0";
0585 cell-index = <2>;
0586 reg = <0x12480000 0x100>;
0587 clocks = <&gcc GSBI2_H_CLK>;
0588 clock-names = "iface";
0589 #address-cells = <1>;
0590 #size-cells = <1>;
0591 ranges;
0592 status = "disabled";
0593
0594 syscon-tcsr = <&tcsr>;
0595
0596 gsbi2_serial: serial@12490000 {
0597 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
0598 reg = <0x12490000 0x1000>,
0599 <0x12480000 0x1000>;
0600 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
0601 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
0602 clock-names = "core", "iface";
0603 status = "disabled";
0604 };
0605
0606 gsbi2_i2c: i2c@124a0000 {
0607 compatible = "qcom,i2c-qup-v1.1.1";
0608 reg = <0x124a0000 0x1000>;
0609 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
0610
0611 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
0612 clock-names = "core", "iface";
0613 status = "disabled";
0614
0615 #address-cells = <1>;
0616 #size-cells = <0>;
0617 };
0618 };
0619
0620 gsbi4: gsbi@16300000 {
0621 compatible = "qcom,gsbi-v1.0.0";
0622 cell-index = <4>;
0623 reg = <0x16300000 0x100>;
0624 clocks = <&gcc GSBI4_H_CLK>;
0625 clock-names = "iface";
0626 #address-cells = <1>;
0627 #size-cells = <1>;
0628 ranges;
0629 status = "disabled";
0630
0631 syscon-tcsr = <&tcsr>;
0632
0633 gsbi4_serial: serial@16340000 {
0634 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
0635 reg = <0x16340000 0x1000>,
0636 <0x16300000 0x1000>;
0637 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
0638 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
0639 clock-names = "core", "iface";
0640 status = "disabled";
0641 };
0642
0643 i2c@16380000 {
0644 compatible = "qcom,i2c-qup-v1.1.1";
0645 reg = <0x16380000 0x1000>;
0646 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
0647
0648 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
0649 clock-names = "core", "iface";
0650 status = "disabled";
0651
0652 #address-cells = <1>;
0653 #size-cells = <0>;
0654 };
0655 };
0656
0657 gsbi5: gsbi@1a200000 {
0658 compatible = "qcom,gsbi-v1.0.0";
0659 cell-index = <5>;
0660 reg = <0x1a200000 0x100>;
0661 clocks = <&gcc GSBI5_H_CLK>;
0662 clock-names = "iface";
0663 #address-cells = <1>;
0664 #size-cells = <1>;
0665 ranges;
0666 status = "disabled";
0667
0668 syscon-tcsr = <&tcsr>;
0669
0670 gsbi5_serial: serial@1a240000 {
0671 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
0672 reg = <0x1a240000 0x1000>,
0673 <0x1a200000 0x1000>;
0674 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
0675 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
0676 clock-names = "core", "iface";
0677 status = "disabled";
0678 };
0679
0680 i2c@1a280000 {
0681 compatible = "qcom,i2c-qup-v1.1.1";
0682 reg = <0x1a280000 0x1000>;
0683 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
0684
0685 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
0686 clock-names = "core", "iface";
0687 status = "disabled";
0688
0689 #address-cells = <1>;
0690 #size-cells = <0>;
0691 };
0692
0693 spi@1a280000 {
0694 compatible = "qcom,spi-qup-v1.1.1";
0695 reg = <0x1a280000 0x1000>;
0696 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
0697
0698 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
0699 clock-names = "core", "iface";
0700 status = "disabled";
0701
0702 #address-cells = <1>;
0703 #size-cells = <0>;
0704 };
0705 };
0706
0707 gsbi6: gsbi@16500000 {
0708 compatible = "qcom,gsbi-v1.0.0";
0709 reg = <0x16500000 0x100>;
0710 cell-index = <6>;
0711 clocks = <&gcc GSBI6_H_CLK>;
0712 clock-names = "iface";
0713 #address-cells = <1>;
0714 #size-cells = <1>;
0715 ranges;
0716
0717 syscon-tcsr = <&tcsr>;
0718
0719 status = "disabled";
0720
0721 gsbi6_i2c: i2c@16580000 {
0722 compatible = "qcom,i2c-qup-v1.1.1";
0723 reg = <0x16580000 0x1000>;
0724 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
0725
0726 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
0727 clock-names = "core", "iface";
0728
0729 #address-cells = <1>;
0730 #size-cells = <0>;
0731
0732 status = "disabled";
0733 };
0734
0735 gsbi6_spi: spi@16580000 {
0736 compatible = "qcom,spi-qup-v1.1.1";
0737 reg = <0x16580000 0x1000>;
0738 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
0739
0740 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
0741 clock-names = "core", "iface";
0742
0743 #address-cells = <1>;
0744 #size-cells = <0>;
0745
0746 status = "disabled";
0747 };
0748 };
0749
0750 gsbi7: gsbi@16600000 {
0751 status = "disabled";
0752 compatible = "qcom,gsbi-v1.0.0";
0753 cell-index = <7>;
0754 reg = <0x16600000 0x100>;
0755 clocks = <&gcc GSBI7_H_CLK>;
0756 clock-names = "iface";
0757 #address-cells = <1>;
0758 #size-cells = <1>;
0759 ranges;
0760 syscon-tcsr = <&tcsr>;
0761
0762 gsbi7_serial: serial@16640000 {
0763 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
0764 reg = <0x16640000 0x1000>,
0765 <0x16600000 0x1000>;
0766 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
0767 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
0768 clock-names = "core", "iface";
0769 status = "disabled";
0770 };
0771
0772 gsbi7_i2c: i2c@16680000 {
0773 compatible = "qcom,i2c-qup-v1.1.1";
0774 reg = <0x16680000 0x1000>;
0775 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
0776
0777 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
0778 clock-names = "core", "iface";
0779
0780 #address-cells = <1>;
0781 #size-cells = <0>;
0782
0783 status = "disabled";
0784 };
0785 };
0786
0787 rng@1a500000 {
0788 compatible = "qcom,prng";
0789 reg = <0x1a500000 0x200>;
0790 clocks = <&gcc PRNG_CLK>;
0791 clock-names = "core";
0792 };
0793
0794 sata_phy: sata-phy@1b400000 {
0795 compatible = "qcom,ipq806x-sata-phy";
0796 reg = <0x1b400000 0x200>;
0797
0798 clocks = <&gcc SATA_PHY_CFG_CLK>;
0799 clock-names = "cfg";
0800
0801 #phy-cells = <0>;
0802 status = "disabled";
0803 };
0804
0805 nand: nand-controller@1ac00000 {
0806 compatible = "qcom,ipq806x-nand";
0807 reg = <0x1ac00000 0x800>;
0808
0809 pinctrl-0 = <&nand_pins>;
0810 pinctrl-names = "default";
0811
0812 clocks = <&gcc EBI2_CLK>,
0813 <&gcc EBI2_AON_CLK>;
0814 clock-names = "core", "aon";
0815
0816 dmas = <&adm_dma 3>;
0817 dma-names = "rxtx";
0818 qcom,cmd-crci = <15>;
0819 qcom,data-crci = <3>;
0820
0821 #address-cells = <1>;
0822 #size-cells = <0>;
0823
0824 status = "disabled";
0825 };
0826
0827 sata: sata@29000000 {
0828 compatible = "qcom,ipq806x-ahci", "generic-ahci";
0829 reg = <0x29000000 0x180>;
0830
0831 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
0832
0833 clocks = <&gcc SFAB_SATA_S_H_CLK>,
0834 <&gcc SATA_H_CLK>,
0835 <&gcc SATA_A_CLK>,
0836 <&gcc SATA_RXOOB_CLK>,
0837 <&gcc SATA_PMALIVE_CLK>;
0838 clock-names = "slave_face", "iface", "core",
0839 "rxoob", "pmalive";
0840
0841 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
0842 assigned-clock-rates = <100000000>, <100000000>;
0843
0844 phys = <&sata_phy>;
0845 phy-names = "sata-phy";
0846 status = "disabled";
0847 };
0848
0849 qcom,ssbi@500000 {
0850 compatible = "qcom,ssbi";
0851 reg = <0x00500000 0x1000>;
0852 qcom,controller-type = "pmic-arbiter";
0853 };
0854
0855 qfprom: qfprom@700000 {
0856 compatible = "qcom,ipq8064-qfprom", "qcom,qfprom";
0857 reg = <0x00700000 0x1000>;
0858 #address-cells = <1>;
0859 #size-cells = <1>;
0860 speedbin_efuse: speedbin@c0 {
0861 reg = <0xc0 0x4>;
0862 };
0863 tsens_calib: calib@400 {
0864 reg = <0x400 0xb>;
0865 };
0866 tsens_calib_backup: calib_backup@410 {
0867 reg = <0x410 0xb>;
0868 };
0869 };
0870
0871 gcc: clock-controller@900000 {
0872 compatible = "qcom,gcc-ipq8064", "syscon";
0873 clocks = <&pxo_board>, <&cxo_board>;
0874 clock-names = "pxo", "cxo";
0875 reg = <0x00900000 0x4000>;
0876 #clock-cells = <1>;
0877 #reset-cells = <1>;
0878 #power-domain-cells = <1>;
0879
0880 tsens: thermal-sensor@900000 {
0881 compatible = "qcom,ipq8064-tsens";
0882
0883 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
0884 nvmem-cell-names = "calib", "calib_backup";
0885 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
0886 interrupt-names = "uplow";
0887
0888 #qcom,sensors = <11>;
0889 #thermal-sensor-cells = <1>;
0890 };
0891 };
0892
0893 rpm: rpm@108000 {
0894 compatible = "qcom,rpm-ipq8064";
0895 reg = <0x108000 0x1000>;
0896 qcom,ipc = <&l2cc 0x8 2>;
0897
0898 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0899 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
0900 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0901 interrupt-names = "ack", "err", "wakeup";
0902
0903 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
0904 clock-names = "ram";
0905
0906 rpmcc: clock-controller {
0907 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
0908 #clock-cells = <1>;
0909 clocks = <&pxo_board>;
0910 clock-names = "pxo";
0911 };
0912 };
0913
0914 tcsr: syscon@1a400000 {
0915 compatible = "qcom,tcsr-ipq8064", "syscon";
0916 reg = <0x1a400000 0x100>;
0917 };
0918
0919 l2cc: clock-controller@2011000 {
0920 compatible = "qcom,kpss-gcc", "syscon";
0921 reg = <0x2011000 0x1000>;
0922 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
0923 clock-names = "pll8_vote", "pxo";
0924 clock-output-names = "acpu_l2_aux";
0925 };
0926
0927 lcc: clock-controller@28000000 {
0928 compatible = "qcom,lcc-ipq8064";
0929 reg = <0x28000000 0x1000>;
0930 #clock-cells = <1>;
0931 #reset-cells = <1>;
0932 };
0933
0934 pcie0: pci@1b500000 {
0935 compatible = "qcom,pcie-ipq8064";
0936 reg = <0x1b500000 0x1000
0937 0x1b502000 0x80
0938 0x1b600000 0x100
0939 0x0ff00000 0x100000>;
0940 reg-names = "dbi", "elbi", "parf", "config";
0941 device_type = "pci";
0942 linux,pci-domain = <0>;
0943 bus-range = <0x00 0xff>;
0944 num-lanes = <1>;
0945 #address-cells = <3>;
0946 #size-cells = <2>;
0947
0948 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000 /* downstream I/O */
0949 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
0950
0951 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0952 interrupt-names = "msi";
0953 #interrupt-cells = <1>;
0954 interrupt-map-mask = <0 0 0 0x7>;
0955 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
0956 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
0957 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
0958 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
0959
0960 clocks = <&gcc PCIE_A_CLK>,
0961 <&gcc PCIE_H_CLK>,
0962 <&gcc PCIE_PHY_CLK>,
0963 <&gcc PCIE_AUX_CLK>,
0964 <&gcc PCIE_ALT_REF_CLK>;
0965 clock-names = "core", "iface", "phy", "aux", "ref";
0966
0967 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
0968 assigned-clock-rates = <100000000>;
0969
0970 resets = <&gcc PCIE_ACLK_RESET>,
0971 <&gcc PCIE_HCLK_RESET>,
0972 <&gcc PCIE_POR_RESET>,
0973 <&gcc PCIE_PCI_RESET>,
0974 <&gcc PCIE_PHY_RESET>,
0975 <&gcc PCIE_EXT_RESET>;
0976 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
0977
0978 pinctrl-0 = <&pcie0_pins>;
0979 pinctrl-names = "default";
0980
0981 status = "disabled";
0982 perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
0983 };
0984
0985 pcie1: pci@1b700000 {
0986 compatible = "qcom,pcie-ipq8064";
0987 reg = <0x1b700000 0x1000
0988 0x1b702000 0x80
0989 0x1b800000 0x100
0990 0x31f00000 0x100000>;
0991 reg-names = "dbi", "elbi", "parf", "config";
0992 device_type = "pci";
0993 linux,pci-domain = <1>;
0994 bus-range = <0x00 0xff>;
0995 num-lanes = <1>;
0996 #address-cells = <3>;
0997 #size-cells = <2>;
0998
0999 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000 /* downstream I/O */
1000 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1001
1002 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1003 interrupt-names = "msi";
1004 #interrupt-cells = <1>;
1005 interrupt-map-mask = <0 0 0 0x7>;
1006 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1007 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1008 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1009 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1010
1011 clocks = <&gcc PCIE_1_A_CLK>,
1012 <&gcc PCIE_1_H_CLK>,
1013 <&gcc PCIE_1_PHY_CLK>,
1014 <&gcc PCIE_1_AUX_CLK>,
1015 <&gcc PCIE_1_ALT_REF_CLK>;
1016 clock-names = "core", "iface", "phy", "aux", "ref";
1017
1018 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1019 assigned-clock-rates = <100000000>;
1020
1021 resets = <&gcc PCIE_1_ACLK_RESET>,
1022 <&gcc PCIE_1_HCLK_RESET>,
1023 <&gcc PCIE_1_POR_RESET>,
1024 <&gcc PCIE_1_PCI_RESET>,
1025 <&gcc PCIE_1_PHY_RESET>,
1026 <&gcc PCIE_1_EXT_RESET>;
1027 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1028
1029 pinctrl-0 = <&pcie1_pins>;
1030 pinctrl-names = "default";
1031
1032 status = "disabled";
1033 perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1034 };
1035
1036 pcie2: pci@1b900000 {
1037 compatible = "qcom,pcie-ipq8064";
1038 reg = <0x1b900000 0x1000
1039 0x1b902000 0x80
1040 0x1ba00000 0x100
1041 0x35f00000 0x100000>;
1042 reg-names = "dbi", "elbi", "parf", "config";
1043 device_type = "pci";
1044 linux,pci-domain = <2>;
1045 bus-range = <0x00 0xff>;
1046 num-lanes = <1>;
1047 #address-cells = <3>;
1048 #size-cells = <2>;
1049
1050 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000 /* downstream I/O */
1051 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1052
1053 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1054 interrupt-names = "msi";
1055 #interrupt-cells = <1>;
1056 interrupt-map-mask = <0 0 0 0x7>;
1057 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1058 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1059 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1060 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1061
1062 clocks = <&gcc PCIE_2_A_CLK>,
1063 <&gcc PCIE_2_H_CLK>,
1064 <&gcc PCIE_2_PHY_CLK>,
1065 <&gcc PCIE_2_AUX_CLK>,
1066 <&gcc PCIE_2_ALT_REF_CLK>;
1067 clock-names = "core", "iface", "phy", "aux", "ref";
1068
1069 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1070 assigned-clock-rates = <100000000>;
1071
1072 resets = <&gcc PCIE_2_ACLK_RESET>,
1073 <&gcc PCIE_2_HCLK_RESET>,
1074 <&gcc PCIE_2_POR_RESET>,
1075 <&gcc PCIE_2_PCI_RESET>,
1076 <&gcc PCIE_2_PHY_RESET>,
1077 <&gcc PCIE_2_EXT_RESET>;
1078 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1079
1080 pinctrl-0 = <&pcie2_pins>;
1081 pinctrl-names = "default";
1082
1083 status = "disabled";
1084 perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1085 };
1086
1087 nss_common: syscon@03000000 {
1088 compatible = "syscon";
1089 reg = <0x03000000 0x0000FFFF>;
1090 };
1091
1092 qsgmii_csr: syscon@1bb00000 {
1093 compatible = "syscon";
1094 reg = <0x1bb00000 0x000001FF>;
1095 };
1096
1097 stmmac_axi_setup: stmmac-axi-config {
1098 snps,wr_osr_lmt = <7>;
1099 snps,rd_osr_lmt = <7>;
1100 snps,blen = <16 0 0 0 0 0 0>;
1101 };
1102
1103 gmac0: ethernet@37000000 {
1104 device_type = "network";
1105 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1106 reg = <0x37000000 0x200000>;
1107 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1108 interrupt-names = "macirq";
1109
1110 snps,axi-config = <&stmmac_axi_setup>;
1111 snps,pbl = <32>;
1112 snps,aal;
1113
1114 qcom,nss-common = <&nss_common>;
1115 qcom,qsgmii-csr = <&qsgmii_csr>;
1116
1117 clocks = <&gcc GMAC_CORE1_CLK>;
1118 clock-names = "stmmaceth";
1119
1120 resets = <&gcc GMAC_CORE1_RESET>,
1121 <&gcc GMAC_AHB_RESET>;
1122 reset-names = "stmmaceth", "ahb";
1123
1124 status = "disabled";
1125 };
1126
1127 gmac1: ethernet@37200000 {
1128 device_type = "network";
1129 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1130 reg = <0x37200000 0x200000>;
1131 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1132 interrupt-names = "macirq";
1133
1134 snps,axi-config = <&stmmac_axi_setup>;
1135 snps,pbl = <32>;
1136 snps,aal;
1137
1138 qcom,nss-common = <&nss_common>;
1139 qcom,qsgmii-csr = <&qsgmii_csr>;
1140
1141 clocks = <&gcc GMAC_CORE2_CLK>;
1142 clock-names = "stmmaceth";
1143
1144 resets = <&gcc GMAC_CORE2_RESET>,
1145 <&gcc GMAC_AHB_RESET>;
1146 reset-names = "stmmaceth", "ahb";
1147
1148 status = "disabled";
1149 };
1150
1151 gmac2: ethernet@37400000 {
1152 device_type = "network";
1153 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1154 reg = <0x37400000 0x200000>;
1155 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1156 interrupt-names = "macirq";
1157
1158 snps,axi-config = <&stmmac_axi_setup>;
1159 snps,pbl = <32>;
1160 snps,aal;
1161
1162 qcom,nss-common = <&nss_common>;
1163 qcom,qsgmii-csr = <&qsgmii_csr>;
1164
1165 clocks = <&gcc GMAC_CORE3_CLK>;
1166 clock-names = "stmmaceth";
1167
1168 resets = <&gcc GMAC_CORE3_RESET>,
1169 <&gcc GMAC_AHB_RESET>;
1170 reset-names = "stmmaceth", "ahb";
1171
1172 status = "disabled";
1173 };
1174
1175 gmac3: ethernet@37600000 {
1176 device_type = "network";
1177 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1178 reg = <0x37600000 0x200000>;
1179 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1180 interrupt-names = "macirq";
1181
1182 snps,axi-config = <&stmmac_axi_setup>;
1183 snps,pbl = <32>;
1184 snps,aal;
1185
1186 qcom,nss-common = <&nss_common>;
1187 qcom,qsgmii-csr = <&qsgmii_csr>;
1188
1189 clocks = <&gcc GMAC_CORE4_CLK>;
1190 clock-names = "stmmaceth";
1191
1192 resets = <&gcc GMAC_CORE4_RESET>,
1193 <&gcc GMAC_AHB_RESET>;
1194 reset-names = "stmmaceth", "ahb";
1195
1196 status = "disabled";
1197 };
1198
1199 hs_phy_0: phy@100f8800 {
1200 compatible = "qcom,ipq806x-usb-phy-hs";
1201 reg = <0x100f8800 0x30>;
1202 clocks = <&gcc USB30_0_UTMI_CLK>;
1203 clock-names = "ref";
1204 #phy-cells = <0>;
1205
1206 status = "disabled";
1207 };
1208
1209 ss_phy_0: phy@100f8830 {
1210 compatible = "qcom,ipq806x-usb-phy-ss";
1211 reg = <0x100f8830 0x30>;
1212 clocks = <&gcc USB30_0_MASTER_CLK>;
1213 clock-names = "ref";
1214 #phy-cells = <0>;
1215
1216 status = "disabled";
1217 };
1218
1219 usb3_0: usb3@100f8800 {
1220 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
1221 #address-cells = <1>;
1222 #size-cells = <1>;
1223 reg = <0x100f8800 0x8000>;
1224 clocks = <&gcc USB30_0_MASTER_CLK>;
1225 clock-names = "core";
1226
1227 ranges;
1228
1229 resets = <&gcc USB30_0_MASTER_RESET>;
1230 reset-names = "master";
1231
1232 status = "disabled";
1233
1234 dwc3_0: dwc3@10000000 {
1235 compatible = "snps,dwc3";
1236 reg = <0x10000000 0xcd00>;
1237 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1238 phys = <&hs_phy_0>, <&ss_phy_0>;
1239 phy-names = "usb2-phy", "usb3-phy";
1240 dr_mode = "host";
1241 snps,dis_u3_susphy_quirk;
1242 };
1243 };
1244
1245 hs_phy_1: phy@110f8800 {
1246 compatible = "qcom,ipq806x-usb-phy-hs";
1247 reg = <0x110f8800 0x30>;
1248 clocks = <&gcc USB30_1_UTMI_CLK>;
1249 clock-names = "ref";
1250 #phy-cells = <0>;
1251
1252 status = "disabled";
1253 };
1254
1255 ss_phy_1: phy@110f8830 {
1256 compatible = "qcom,ipq806x-usb-phy-ss";
1257 reg = <0x110f8830 0x30>;
1258 clocks = <&gcc USB30_1_MASTER_CLK>;
1259 clock-names = "ref";
1260 #phy-cells = <0>;
1261
1262 status = "disabled";
1263 };
1264
1265 usb3_1: usb3@110f8800 {
1266 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
1267 #address-cells = <1>;
1268 #size-cells = <1>;
1269 reg = <0x110f8800 0x8000>;
1270 clocks = <&gcc USB30_1_MASTER_CLK>;
1271 clock-names = "core";
1272
1273 ranges;
1274
1275 resets = <&gcc USB30_1_MASTER_RESET>;
1276 reset-names = "master";
1277
1278 status = "disabled";
1279
1280 dwc3_1: dwc3@11000000 {
1281 compatible = "snps,dwc3";
1282 reg = <0x11000000 0xcd00>;
1283 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1284 phys = <&hs_phy_1>, <&ss_phy_1>;
1285 phy-names = "usb2-phy", "usb3-phy";
1286 dr_mode = "host";
1287 snps,dis_u3_susphy_quirk;
1288 };
1289 };
1290
1291 vsdcc_fixed: vsdcc-regulator {
1292 compatible = "regulator-fixed";
1293 regulator-name = "SDCC Power";
1294 regulator-min-microvolt = <3300000>;
1295 regulator-max-microvolt = <3300000>;
1296 regulator-always-on;
1297 };
1298
1299 sdcc1bam: dma-controller@12402000 {
1300 compatible = "qcom,bam-v1.3.0";
1301 reg = <0x12402000 0x8000>;
1302 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1303 clocks = <&gcc SDC1_H_CLK>;
1304 clock-names = "bam_clk";
1305 #dma-cells = <1>;
1306 qcom,ee = <0>;
1307 };
1308
1309 sdcc3bam: dma-controller@12182000 {
1310 compatible = "qcom,bam-v1.3.0";
1311 reg = <0x12182000 0x8000>;
1312 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1313 clocks = <&gcc SDC3_H_CLK>;
1314 clock-names = "bam_clk";
1315 #dma-cells = <1>;
1316 qcom,ee = <0>;
1317 };
1318
1319 amba: amba {
1320 compatible = "simple-bus";
1321 #address-cells = <1>;
1322 #size-cells = <1>;
1323 ranges;
1324
1325 sdcc1: mmc@12400000 {
1326 status = "disabled";
1327 compatible = "arm,pl18x", "arm,primecell";
1328 arm,primecell-periphid = <0x00051180>;
1329 reg = <0x12400000 0x2000>;
1330 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1331 interrupt-names = "cmd_irq";
1332 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1333 clock-names = "mclk", "apb_pclk";
1334 bus-width = <8>;
1335 max-frequency = <96000000>;
1336 non-removable;
1337 cap-sd-highspeed;
1338 cap-mmc-highspeed;
1339 mmc-ddr-1_8v;
1340 vmmc-supply = <&vsdcc_fixed>;
1341 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1342 dma-names = "tx", "rx";
1343 };
1344
1345 sdcc3: mmc@12180000 {
1346 compatible = "arm,pl18x", "arm,primecell";
1347 arm,primecell-periphid = <0x00051180>;
1348 status = "disabled";
1349 reg = <0x12180000 0x2000>;
1350 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1351 interrupt-names = "cmd_irq";
1352 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1353 clock-names = "mclk", "apb_pclk";
1354 bus-width = <8>;
1355 cap-sd-highspeed;
1356 cap-mmc-highspeed;
1357 max-frequency = <192000000>;
1358 sd-uhs-sdr104;
1359 sd-uhs-ddr50;
1360 vqmmc-supply = <&vsdcc_fixed>;
1361 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1362 dma-names = "tx", "rx";
1363 };
1364 };
1365
1366 sfpb_mutex: hwlock@1200600 {
1367 compatible = "qcom,sfpb-mutex";
1368 reg = <0x01200600 0x100>;
1369
1370 #hwlock-cells = <1>;
1371 };
1372 };
1373 };
