0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
0004 */
0005
0006 /dts-v1/;
0007
0008 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/interrupt-controller/irq.h>
0011
0012 / {
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015
0016 model = "Qualcomm Technologies, Inc. IPQ4019";
0017 compatible = "qcom,ipq4019";
0018 interrupt-parent = <&intc>;
0019
0020 reserved-memory {
0021 #address-cells = <0x1>;
0022 #size-cells = <0x1>;
0023 ranges;
0024
0025 smem_region: smem@87e00000 {
0026 reg = <0x87e00000 0x080000>;
0027 no-map;
0028 };
0029
0030 tz@87e80000 {
0031 reg = <0x87e80000 0x180000>;
0032 no-map;
0033 };
0034 };
0035
0036 aliases {
0037 spi0 = &blsp1_spi1;
0038 spi1 = &blsp1_spi2;
0039 i2c0 = &blsp1_i2c3;
0040 i2c1 = &blsp1_i2c4;
0041 };
0042
0043 cpus {
0044 #address-cells = <1>;
0045 #size-cells = <0>;
0046 cpu@0 {
0047 device_type = "cpu";
0048 compatible = "arm,cortex-a7";
0049 enable-method = "qcom,kpss-acc-v2";
0050 next-level-cache = <&L2>;
0051 qcom,acc = <&acc0>;
0052 qcom,saw = <&saw0>;
0053 reg = <0x0>;
0054 clocks = <&gcc GCC_APPS_CLK_SRC>;
0055 clock-frequency = <0>;
0056 clock-latency = <256000>;
0057 operating-points-v2 = <&cpu0_opp_table>;
0058 };
0059
0060 cpu@1 {
0061 device_type = "cpu";
0062 compatible = "arm,cortex-a7";
0063 enable-method = "qcom,kpss-acc-v2";
0064 next-level-cache = <&L2>;
0065 qcom,acc = <&acc1>;
0066 qcom,saw = <&saw1>;
0067 reg = <0x1>;
0068 clocks = <&gcc GCC_APPS_CLK_SRC>;
0069 clock-frequency = <0>;
0070 clock-latency = <256000>;
0071 operating-points-v2 = <&cpu0_opp_table>;
0072 };
0073
0074 cpu@2 {
0075 device_type = "cpu";
0076 compatible = "arm,cortex-a7";
0077 enable-method = "qcom,kpss-acc-v2";
0078 next-level-cache = <&L2>;
0079 qcom,acc = <&acc2>;
0080 qcom,saw = <&saw2>;
0081 reg = <0x2>;
0082 clocks = <&gcc GCC_APPS_CLK_SRC>;
0083 clock-frequency = <0>;
0084 clock-latency = <256000>;
0085 operating-points-v2 = <&cpu0_opp_table>;
0086 };
0087
0088 cpu@3 {
0089 device_type = "cpu";
0090 compatible = "arm,cortex-a7";
0091 enable-method = "qcom,kpss-acc-v2";
0092 next-level-cache = <&L2>;
0093 qcom,acc = <&acc3>;
0094 qcom,saw = <&saw3>;
0095 reg = <0x3>;
0096 clocks = <&gcc GCC_APPS_CLK_SRC>;
0097 clock-frequency = <0>;
0098 clock-latency = <256000>;
0099 operating-points-v2 = <&cpu0_opp_table>;
0100 };
0101
0102 L2: l2-cache {
0103 compatible = "cache";
0104 cache-level = <2>;
0105 qcom,saw = <&saw_l2>;
0106 };
0107 };
0108
0109 cpu0_opp_table: opp_table0 {
0110 compatible = "operating-points-v2";
0111 opp-shared;
0112
0113 opp-48000000 {
0114 opp-hz = /bits/ 64 <48000000>;
0115 clock-latency-ns = <256000>;
0116 };
0117 opp-200000000 {
0118 opp-hz = /bits/ 64 <200000000>;
0119 clock-latency-ns = <256000>;
0120 };
0121 opp-500000000 {
0122 opp-hz = /bits/ 64 <500000000>;
0123 clock-latency-ns = <256000>;
0124 };
0125 opp-716000000 {
0126 opp-hz = /bits/ 64 <716000000>;
0127 clock-latency-ns = <256000>;
0128 };
0129 };
0130
0131 memory {
0132 device_type = "memory";
0133 reg = <0x0 0x0>;
0134 };
0135
0136 pmu {
0137 compatible = "arm,cortex-a7-pmu";
0138 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
0139 IRQ_TYPE_LEVEL_HIGH)>;
0140 };
0141
0142 clocks {
0143 sleep_clk: sleep_clk {
0144 compatible = "fixed-clock";
0145 clock-frequency = <32000>;
0146 clock-output-names = "gcc_sleep_clk_src";
0147 #clock-cells = <0>;
0148 };
0149
0150 xo: xo {
0151 compatible = "fixed-clock";
0152 clock-frequency = <48000000>;
0153 #clock-cells = <0>;
0154 };
0155 };
0156
0157 firmware {
0158 scm {
0159 compatible = "qcom,scm-ipq4019", "qcom,scm";
0160 };
0161 };
0162
0163 timer {
0164 compatible = "arm,armv7-timer";
0165 interrupts = <1 2 0xf08>,
0166 <1 3 0xf08>,
0167 <1 4 0xf08>,
0168 <1 1 0xf08>;
0169 clock-frequency = <48000000>;
0170 always-on;
0171 };
0172
0173 soc {
0174 #address-cells = <1>;
0175 #size-cells = <1>;
0176 ranges;
0177 compatible = "simple-bus";
0178
0179 intc: interrupt-controller@b000000 {
0180 compatible = "qcom,msm-qgic2";
0181 interrupt-controller;
0182 #interrupt-cells = <3>;
0183 reg = <0x0b000000 0x1000>,
0184 <0x0b002000 0x1000>;
0185 };
0186
0187 gcc: clock-controller@1800000 {
0188 compatible = "qcom,gcc-ipq4019";
0189 #clock-cells = <1>;
0190 #power-domain-cells = <1>;
0191 #reset-cells = <1>;
0192 reg = <0x1800000 0x60000>;
0193 };
0194
0195 prng: rng@22000 {
0196 compatible = "qcom,prng";
0197 reg = <0x22000 0x140>;
0198 clocks = <&gcc GCC_PRNG_AHB_CLK>;
0199 clock-names = "core";
0200 status = "disabled";
0201 };
0202
0203 tlmm: pinctrl@1000000 {
0204 compatible = "qcom,ipq4019-pinctrl";
0205 reg = <0x01000000 0x300000>;
0206 gpio-controller;
0207 gpio-ranges = <&tlmm 0 0 100>;
0208 #gpio-cells = <2>;
0209 interrupt-controller;
0210 #interrupt-cells = <2>;
0211 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
0212 };
0213
0214 vqmmc: regulator@1948000 {
0215 compatible = "qcom,vqmmc-ipq4019-regulator";
0216 reg = <0x01948000 0x4>;
0217 regulator-name = "vqmmc";
0218 regulator-min-microvolt = <1500000>;
0219 regulator-max-microvolt = <3000000>;
0220 regulator-always-on;
0221 status = "disabled";
0222 };
0223
0224 sdhci: mmc@7824900 {
0225 compatible = "qcom,sdhci-msm-v4";
0226 reg = <0x7824900 0x11c>, <0x7824000 0x800>;
0227 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
0228 interrupt-names = "hc_irq", "pwr_irq";
0229 bus-width = <8>;
0230 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
0231 <&gcc GCC_DCD_XO_CLK>;
0232 clock-names = "core", "iface", "xo";
0233 status = "disabled";
0234 };
0235
0236 blsp_dma: dma-controller@7884000 {
0237 compatible = "qcom,bam-v1.7.0";
0238 reg = <0x07884000 0x23000>;
0239 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
0240 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
0241 clock-names = "bam_clk";
0242 #dma-cells = <1>;
0243 qcom,ee = <0>;
0244 status = "disabled";
0245 };
0246
0247 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
0248 compatible = "qcom,spi-qup-v2.2.1";
0249 reg = <0x78b5000 0x600>;
0250 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0251 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
0252 <&gcc GCC_BLSP1_AHB_CLK>;
0253 clock-names = "core", "iface";
0254 #address-cells = <1>;
0255 #size-cells = <0>;
0256 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
0257 dma-names = "tx", "rx";
0258 status = "disabled";
0259 };
0260
0261 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
0262 compatible = "qcom,spi-qup-v2.2.1";
0263 reg = <0x78b6000 0x600>;
0264 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0265 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
0266 <&gcc GCC_BLSP1_AHB_CLK>;
0267 clock-names = "core", "iface";
0268 #address-cells = <1>;
0269 #size-cells = <0>;
0270 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
0271 dma-names = "tx", "rx";
0272 status = "disabled";
0273 };
0274
0275 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
0276 compatible = "qcom,i2c-qup-v2.2.1";
0277 reg = <0x78b7000 0x600>;
0278 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0279 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
0280 <&gcc GCC_BLSP1_AHB_CLK>;
0281 clock-names = "core", "iface";
0282 #address-cells = <1>;
0283 #size-cells = <0>;
0284 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
0285 dma-names = "tx", "rx";
0286 status = "disabled";
0287 };
0288
0289 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
0290 compatible = "qcom,i2c-qup-v2.2.1";
0291 reg = <0x78b8000 0x600>;
0292 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0293 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
0294 <&gcc GCC_BLSP1_AHB_CLK>;
0295 clock-names = "core", "iface";
0296 #address-cells = <1>;
0297 #size-cells = <0>;
0298 dmas = <&blsp_dma 10>, <&blsp_dma 11>;
0299 dma-names = "tx", "rx";
0300 status = "disabled";
0301 };
0302
0303 cryptobam: dma-controller@8e04000 {
0304 compatible = "qcom,bam-v1.7.0";
0305 reg = <0x08e04000 0x20000>;
0306 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
0307 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
0308 clock-names = "bam_clk";
0309 #dma-cells = <1>;
0310 qcom,ee = <1>;
0311 qcom,controlled-remotely;
0312 status = "disabled";
0313 };
0314
0315 crypto: crypto@8e3a000 {
0316 compatible = "qcom,crypto-v5.1";
0317 reg = <0x08e3a000 0x6000>;
0318 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
0319 <&gcc GCC_CRYPTO_AXI_CLK>,
0320 <&gcc GCC_CRYPTO_CLK>;
0321 clock-names = "iface", "bus", "core";
0322 dmas = <&cryptobam 2>, <&cryptobam 3>;
0323 dma-names = "rx", "tx";
0324 status = "disabled";
0325 };
0326
0327 acc0: clock-controller@b088000 {
0328 compatible = "qcom,kpss-acc-v2";
0329 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
0330 };
0331
0332 acc1: clock-controller@b098000 {
0333 compatible = "qcom,kpss-acc-v2";
0334 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
0335 };
0336
0337 acc2: clock-controller@b0a8000 {
0338 compatible = "qcom,kpss-acc-v2";
0339 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
0340 };
0341
0342 acc3: clock-controller@b0b8000 {
0343 compatible = "qcom,kpss-acc-v2";
0344 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
0345 };
0346
0347 saw0: regulator@b089000 {
0348 compatible = "qcom,saw2";
0349 reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
0350 regulator;
0351 };
0352
0353 saw1: regulator@b099000 {
0354 compatible = "qcom,saw2";
0355 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
0356 regulator;
0357 };
0358
0359 saw2: regulator@b0a9000 {
0360 compatible = "qcom,saw2";
0361 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
0362 regulator;
0363 };
0364
0365 saw3: regulator@b0b9000 {
0366 compatible = "qcom,saw2";
0367 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
0368 regulator;
0369 };
0370
0371 saw_l2: regulator@b012000 {
0372 compatible = "qcom,saw2";
0373 reg = <0xb012000 0x1000>;
0374 regulator;
0375 };
0376
0377 blsp1_uart1: serial@78af000 {
0378 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0379 reg = <0x78af000 0x200>;
0380 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0381 status = "disabled";
0382 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
0383 <&gcc GCC_BLSP1_AHB_CLK>;
0384 clock-names = "core", "iface";
0385 dmas = <&blsp_dma 0>, <&blsp_dma 1>;
0386 dma-names = "tx", "rx";
0387 };
0388
0389 blsp1_uart2: serial@78b0000 {
0390 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0391 reg = <0x78b0000 0x200>;
0392 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
0393 status = "disabled";
0394 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
0395 <&gcc GCC_BLSP1_AHB_CLK>;
0396 clock-names = "core", "iface";
0397 dmas = <&blsp_dma 2>, <&blsp_dma 3>;
0398 dma-names = "tx", "rx";
0399 };
0400
0401 watchdog: watchdog@b017000 {
0402 compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
0403 reg = <0xb017000 0x40>;
0404 clocks = <&sleep_clk>;
0405 timeout-sec = <10>;
0406 status = "disabled";
0407 };
0408
0409 restart@4ab000 {
0410 compatible = "qcom,pshold";
0411 reg = <0x4ab000 0x4>;
0412 };
0413
0414 pcie0: pci@40000000 {
0415 compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
0416 reg = <0x40000000 0xf1d
0417 0x40000f20 0xa8
0418 0x80000 0x2000
0419 0x40100000 0x1000>;
0420 reg-names = "dbi", "elbi", "parf", "config";
0421 device_type = "pci";
0422 linux,pci-domain = <0>;
0423 bus-range = <0x00 0xff>;
0424 num-lanes = <1>;
0425 #address-cells = <3>;
0426 #size-cells = <2>;
0427
0428 ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
0429 <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
0430
0431 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
0432 interrupt-names = "msi";
0433 #interrupt-cells = <1>;
0434 interrupt-map-mask = <0 0 0 0x7>;
0435 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
0436 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
0437 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
0438 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
0439 clocks = <&gcc GCC_PCIE_AHB_CLK>,
0440 <&gcc GCC_PCIE_AXI_M_CLK>,
0441 <&gcc GCC_PCIE_AXI_S_CLK>;
0442 clock-names = "aux",
0443 "master_bus",
0444 "slave_bus";
0445
0446 resets = <&gcc PCIE_AXI_M_ARES>,
0447 <&gcc PCIE_AXI_S_ARES>,
0448 <&gcc PCIE_PIPE_ARES>,
0449 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
0450 <&gcc PCIE_AXI_S_XPU_ARES>,
0451 <&gcc PCIE_PARF_XPU_ARES>,
0452 <&gcc PCIE_PHY_ARES>,
0453 <&gcc PCIE_AXI_M_STICKY_ARES>,
0454 <&gcc PCIE_PIPE_STICKY_ARES>,
0455 <&gcc PCIE_PWR_ARES>,
0456 <&gcc PCIE_AHB_ARES>,
0457 <&gcc PCIE_PHY_AHB_ARES>;
0458 reset-names = "axi_m",
0459 "axi_s",
0460 "pipe",
0461 "axi_m_vmid",
0462 "axi_s_xpu",
0463 "parf",
0464 "phy",
0465 "axi_m_sticky",
0466 "pipe_sticky",
0467 "pwr",
0468 "ahb",
0469 "phy_ahb";
0470
0471 status = "disabled";
0472 };
0473
0474 qpic_bam: dma-controller@7984000 {
0475 compatible = "qcom,bam-v1.7.0";
0476 reg = <0x7984000 0x1a000>;
0477 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
0478 clocks = <&gcc GCC_QPIC_CLK>;
0479 clock-names = "bam_clk";
0480 #dma-cells = <1>;
0481 qcom,ee = <0>;
0482 status = "disabled";
0483 };
0484
0485 nand: nand-controller@79b0000 {
0486 compatible = "qcom,ipq4019-nand";
0487 reg = <0x79b0000 0x1000>;
0488 #address-cells = <1>;
0489 #size-cells = <0>;
0490 clocks = <&gcc GCC_QPIC_CLK>,
0491 <&gcc GCC_QPIC_AHB_CLK>;
0492 clock-names = "core", "aon";
0493
0494 dmas = <&qpic_bam 0>,
0495 <&qpic_bam 1>,
0496 <&qpic_bam 2>;
0497 dma-names = "tx", "rx", "cmd";
0498 status = "disabled";
0499
0500 nand@0 {
0501 reg = <0>;
0502
0503 nand-ecc-strength = <4>;
0504 nand-ecc-step-size = <512>;
0505 nand-bus-width = <8>;
0506 };
0507 };
0508
0509 wifi0: wifi@a000000 {
0510 compatible = "qcom,ipq4019-wifi";
0511 reg = <0xa000000 0x200000>;
0512 resets = <&gcc WIFI0_CPU_INIT_RESET>,
0513 <&gcc WIFI0_RADIO_SRIF_RESET>,
0514 <&gcc WIFI0_RADIO_WARM_RESET>,
0515 <&gcc WIFI0_RADIO_COLD_RESET>,
0516 <&gcc WIFI0_CORE_WARM_RESET>,
0517 <&gcc WIFI0_CORE_COLD_RESET>;
0518 reset-names = "wifi_cpu_init", "wifi_radio_srif",
0519 "wifi_radio_warm", "wifi_radio_cold",
0520 "wifi_core_warm", "wifi_core_cold";
0521 clocks = <&gcc GCC_WCSS2G_CLK>,
0522 <&gcc GCC_WCSS2G_REF_CLK>,
0523 <&gcc GCC_WCSS2G_RTC_CLK>;
0524 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
0525 "wifi_wcss_rtc";
0526 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
0527 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
0528 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
0529 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
0530 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
0531 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
0532 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
0533 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
0534 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
0535 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
0536 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
0537 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
0538 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
0539 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
0540 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
0541 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
0542 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
0543 interrupt-names = "msi0", "msi1", "msi2", "msi3",
0544 "msi4", "msi5", "msi6", "msi7",
0545 "msi8", "msi9", "msi10", "msi11",
0546 "msi12", "msi13", "msi14", "msi15",
0547 "legacy";
0548 status = "disabled";
0549 };
0550
0551 wifi1: wifi@a800000 {
0552 compatible = "qcom,ipq4019-wifi";
0553 reg = <0xa800000 0x200000>;
0554 resets = <&gcc WIFI1_CPU_INIT_RESET>,
0555 <&gcc WIFI1_RADIO_SRIF_RESET>,
0556 <&gcc WIFI1_RADIO_WARM_RESET>,
0557 <&gcc WIFI1_RADIO_COLD_RESET>,
0558 <&gcc WIFI1_CORE_WARM_RESET>,
0559 <&gcc WIFI1_CORE_COLD_RESET>;
0560 reset-names = "wifi_cpu_init", "wifi_radio_srif",
0561 "wifi_radio_warm", "wifi_radio_cold",
0562 "wifi_core_warm", "wifi_core_cold";
0563 clocks = <&gcc GCC_WCSS5G_CLK>,
0564 <&gcc GCC_WCSS5G_REF_CLK>,
0565 <&gcc GCC_WCSS5G_RTC_CLK>;
0566 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
0567 "wifi_wcss_rtc";
0568 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
0569 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
0570 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
0571 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
0572 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
0573 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
0574 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
0575 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
0576 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
0577 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
0578 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
0579 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
0580 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
0581 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
0582 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
0583 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
0584 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
0585 interrupt-names = "msi0", "msi1", "msi2", "msi3",
0586 "msi4", "msi5", "msi6", "msi7",
0587 "msi8", "msi9", "msi10", "msi11",
0588 "msi12", "msi13", "msi14", "msi15",
0589 "legacy";
0590 status = "disabled";
0591 };
0592
0593 mdio: mdio@90000 {
0594 #address-cells = <1>;
0595 #size-cells = <0>;
0596 compatible = "qcom,ipq4019-mdio";
0597 reg = <0x90000 0x64>;
0598 status = "disabled";
0599
0600 ethphy0: ethernet-phy@0 {
0601 reg = <0>;
0602 };
0603
0604 ethphy1: ethernet-phy@1 {
0605 reg = <1>;
0606 };
0607
0608 ethphy2: ethernet-phy@2 {
0609 reg = <2>;
0610 };
0611
0612 ethphy3: ethernet-phy@3 {
0613 reg = <3>;
0614 };
0615
0616 ethphy4: ethernet-phy@4 {
0617 reg = <4>;
0618 };
0619 };
0620
0621 usb3_ss_phy: ssphy@9a000 {
0622 compatible = "qcom,usb-ss-ipq4019-phy";
0623 #phy-cells = <0>;
0624 reg = <0x9a000 0x800>;
0625 reg-names = "phy_base";
0626 resets = <&gcc USB3_UNIPHY_PHY_ARES>;
0627 reset-names = "por_rst";
0628 status = "disabled";
0629 };
0630
0631 usb3_hs_phy: hsphy@a6000 {
0632 compatible = "qcom,usb-hs-ipq4019-phy";
0633 #phy-cells = <0>;
0634 reg = <0xa6000 0x40>;
0635 reg-names = "phy_base";
0636 resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
0637 reset-names = "por_rst", "srif_rst";
0638 status = "disabled";
0639 };
0640
0641 usb3: usb3@8af8800 {
0642 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
0643 reg = <0x8af8800 0x100>;
0644 #address-cells = <1>;
0645 #size-cells = <1>;
0646 clocks = <&gcc GCC_USB3_MASTER_CLK>,
0647 <&gcc GCC_USB3_SLEEP_CLK>,
0648 <&gcc GCC_USB3_MOCK_UTMI_CLK>;
0649 clock-names = "core", "sleep", "mock_utmi";
0650 ranges;
0651 status = "disabled";
0652
0653 dwc3@8a00000 {
0654 compatible = "snps,dwc3";
0655 reg = <0x8a00000 0xf8000>;
0656 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
0657 phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
0658 phy-names = "usb2-phy", "usb3-phy";
0659 dr_mode = "host";
0660 };
0661 };
0662
0663 usb2_hs_phy: hsphy@a8000 {
0664 compatible = "qcom,usb-hs-ipq4019-phy";
0665 #phy-cells = <0>;
0666 reg = <0xa8000 0x40>;
0667 reg-names = "phy_base";
0668 resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
0669 reset-names = "por_rst", "srif_rst";
0670 status = "disabled";
0671 };
0672
0673 usb2: usb2@60f8800 {
0674 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
0675 reg = <0x60f8800 0x100>;
0676 #address-cells = <1>;
0677 #size-cells = <1>;
0678 clocks = <&gcc GCC_USB2_MASTER_CLK>,
0679 <&gcc GCC_USB2_SLEEP_CLK>,
0680 <&gcc GCC_USB2_MOCK_UTMI_CLK>;
0681 clock-names = "master", "sleep", "mock_utmi";
0682 ranges;
0683 status = "disabled";
0684
0685 dwc3@6000000 {
0686 compatible = "snps,dwc3";
0687 reg = <0x6000000 0xf8000>;
0688 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
0689 phys = <&usb2_hs_phy>;
0690 phy-names = "usb2-phy";
0691 dr_mode = "host";
0692 };
0693 };
0694 };
0695 };
