0001 // SPDX-License-Identifier: GPL-2.0
0002 /dts-v1/;
0003
0004 #include <dt-bindings/interrupt-controller/arm-gic.h>
0005 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
0006 #include <dt-bindings/gpio/gpio.h>
0007
0008 / {
0009 #address-cells = <1>;
0010 #size-cells = <1>;
0011 model = "Qualcomm APQ 8084";
0012 compatible = "qcom,apq8084";
0013 interrupt-parent = <&intc>;
0014
0015 reserved-memory {
0016 #address-cells = <1>;
0017 #size-cells = <1>;
0018 ranges;
0019
0020 smem_mem: smem_region@fa00000 {
0021 reg = <0xfa00000 0x200000>;
0022 no-map;
0023 };
0024 };
0025
0026 cpus {
0027 #address-cells = <1>;
0028 #size-cells = <0>;
0029
0030 cpu@0 {
0031 device_type = "cpu";
0032 compatible = "qcom,krait";
0033 reg = <0>;
0034 enable-method = "qcom,kpss-acc-v2";
0035 next-level-cache = <&L2>;
0036 qcom,acc = <&acc0>;
0037 qcom,saw = <&saw0>;
0038 cpu-idle-states = <&CPU_SPC>;
0039 };
0040
0041 cpu@1 {
0042 device_type = "cpu";
0043 compatible = "qcom,krait";
0044 reg = <1>;
0045 enable-method = "qcom,kpss-acc-v2";
0046 next-level-cache = <&L2>;
0047 qcom,acc = <&acc1>;
0048 qcom,saw = <&saw1>;
0049 cpu-idle-states = <&CPU_SPC>;
0050 };
0051
0052 cpu@2 {
0053 device_type = "cpu";
0054 compatible = "qcom,krait";
0055 reg = <2>;
0056 enable-method = "qcom,kpss-acc-v2";
0057 next-level-cache = <&L2>;
0058 qcom,acc = <&acc2>;
0059 qcom,saw = <&saw2>;
0060 cpu-idle-states = <&CPU_SPC>;
0061 };
0062
0063 cpu@3 {
0064 device_type = "cpu";
0065 compatible = "qcom,krait";
0066 reg = <3>;
0067 enable-method = "qcom,kpss-acc-v2";
0068 next-level-cache = <&L2>;
0069 qcom,acc = <&acc3>;
0070 qcom,saw = <&saw3>;
0071 cpu-idle-states = <&CPU_SPC>;
0072 };
0073
0074 L2: l2-cache {
0075 compatible = "qcom,arch-cache";
0076 cache-level = <2>;
0077 qcom,saw = <&saw_l2>;
0078 };
0079
0080 idle-states {
0081 CPU_SPC: spc {
0082 compatible = "qcom,idle-state-spc",
0083 "arm,idle-state";
0084 entry-latency-us = <150>;
0085 exit-latency-us = <200>;
0086 min-residency-us = <2000>;
0087 };
0088 };
0089 };
0090
0091 memory {
0092 device_type = "memory";
0093 reg = <0x0 0x0>;
0094 };
0095
0096 firmware {
0097 scm {
0098 compatible = "qcom,scm-apq8084", "qcom,scm";
0099 clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
0100 clock-names = "core", "bus", "iface";
0101 };
0102 };
0103
0104 thermal-zones {
0105 cpu0-thermal {
0106 polling-delay-passive = <250>;
0107 polling-delay = <1000>;
0108
0109 thermal-sensors = <&tsens 5>;
0110
0111 trips {
0112 cpu_alert0: trip0 {
0113 temperature = <75000>;
0114 hysteresis = <2000>;
0115 type = "passive";
0116 };
0117 cpu_crit0: trip1 {
0118 temperature = <110000>;
0119 hysteresis = <2000>;
0120 type = "critical";
0121 };
0122 };
0123 };
0124
0125 cpu1-thermal {
0126 polling-delay-passive = <250>;
0127 polling-delay = <1000>;
0128
0129 thermal-sensors = <&tsens 6>;
0130
0131 trips {
0132 cpu_alert1: trip0 {
0133 temperature = <75000>;
0134 hysteresis = <2000>;
0135 type = "passive";
0136 };
0137 cpu_crit1: trip1 {
0138 temperature = <110000>;
0139 hysteresis = <2000>;
0140 type = "critical";
0141 };
0142 };
0143 };
0144
0145 cpu2-thermal {
0146 polling-delay-passive = <250>;
0147 polling-delay = <1000>;
0148
0149 thermal-sensors = <&tsens 7>;
0150
0151 trips {
0152 cpu_alert2: trip0 {
0153 temperature = <75000>;
0154 hysteresis = <2000>;
0155 type = "passive";
0156 };
0157 cpu_crit2: trip1 {
0158 temperature = <110000>;
0159 hysteresis = <2000>;
0160 type = "critical";
0161 };
0162 };
0163 };
0164
0165 cpu3-thermal {
0166 polling-delay-passive = <250>;
0167 polling-delay = <1000>;
0168
0169 thermal-sensors = <&tsens 8>;
0170
0171 trips {
0172 cpu_alert3: trip0 {
0173 temperature = <75000>;
0174 hysteresis = <2000>;
0175 type = "passive";
0176 };
0177 cpu_crit3: trip1 {
0178 temperature = <110000>;
0179 hysteresis = <2000>;
0180 type = "critical";
0181 };
0182 };
0183 };
0184 };
0185
0186 cpu-pmu {
0187 compatible = "qcom,krait-pmu";
0188 interrupts = <GIC_PPI 7 0xf04>;
0189 };
0190
0191 clocks {
0192 xo_board: xo_board {
0193 compatible = "fixed-clock";
0194 #clock-cells = <0>;
0195 clock-frequency = <19200000>;
0196 };
0197
0198 sleep_clk: sleep_clk {
0199 compatible = "fixed-clock";
0200 #clock-cells = <0>;
0201 clock-frequency = <32768>;
0202 };
0203 };
0204
0205 timer {
0206 compatible = "arm,armv7-timer";
0207 interrupts = <GIC_PPI 2 0xf08>,
0208 <GIC_PPI 3 0xf08>,
0209 <GIC_PPI 4 0xf08>,
0210 <GIC_PPI 1 0xf08>;
0211 clock-frequency = <19200000>;
0212 };
0213
0214 smem {
0215 compatible = "qcom,smem";
0216
0217 qcom,rpm-msg-ram = <&rpm_msg_ram>;
0218 memory-region = <&smem_mem>;
0219
0220 hwlocks = <&tcsr_mutex 3>;
0221 };
0222
0223 soc: soc {
0224 #address-cells = <1>;
0225 #size-cells = <1>;
0226 ranges;
0227 compatible = "simple-bus";
0228
0229 intc: interrupt-controller@f9000000 {
0230 compatible = "qcom,msm-qgic2";
0231 interrupt-controller;
0232 #interrupt-cells = <3>;
0233 reg = <0xf9000000 0x1000>,
0234 <0xf9002000 0x1000>;
0235 };
0236
0237 apcs: syscon@f9011000 {
0238 compatible = "syscon";
0239 reg = <0xf9011000 0x1000>;
0240 };
0241
0242 qfprom: qfprom@fc4bc000 {
0243 compatible = "qcom,apq8084-qfprom", "qcom,qfprom";
0244 reg = <0xfc4bc000 0x1000>;
0245 #address-cells = <1>;
0246 #size-cells = <1>;
0247 tsens_calib: calib@d0 {
0248 reg = <0xd0 0x18>;
0249 };
0250 tsens_backup: backup@440 {
0251 reg = <0x440 0x10>;
0252 };
0253 };
0254
0255 tsens: thermal-sensor@fc4a8000 {
0256 compatible = "qcom,msm8974-tsens";
0257 reg = <0xfc4a9000 0x1000>, /* TM */
0258 <0xfc4a8000 0x1000>; /* SROT */
0259 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
0260 nvmem-cell-names = "calib", "calib_backup";
0261 #qcom,sensors = <11>;
0262 #thermal-sensor-cells = <1>;
0263 };
0264 timer@f9020000 {
0265 #address-cells = <1>;
0266 #size-cells = <1>;
0267 ranges;
0268 compatible = "arm,armv7-timer-mem";
0269 reg = <0xf9020000 0x1000>;
0270 clock-frequency = <19200000>;
0271
0272 frame@f9021000 {
0273 frame-number = <0>;
0274 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0275 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0276 reg = <0xf9021000 0x1000>,
0277 <0xf9022000 0x1000>;
0278 };
0279
0280 frame@f9023000 {
0281 frame-number = <1>;
0282 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0283 reg = <0xf9023000 0x1000>;
0284 status = "disabled";
0285 };
0286
0287 frame@f9024000 {
0288 frame-number = <2>;
0289 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0290 reg = <0xf9024000 0x1000>;
0291 status = "disabled";
0292 };
0293
0294 frame@f9025000 {
0295 frame-number = <3>;
0296 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0297 reg = <0xf9025000 0x1000>;
0298 status = "disabled";
0299 };
0300
0301 frame@f9026000 {
0302 frame-number = <4>;
0303 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0304 reg = <0xf9026000 0x1000>;
0305 status = "disabled";
0306 };
0307
0308 frame@f9027000 {
0309 frame-number = <5>;
0310 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0311 reg = <0xf9027000 0x1000>;
0312 status = "disabled";
0313 };
0314
0315 frame@f9028000 {
0316 frame-number = <6>;
0317 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0318 reg = <0xf9028000 0x1000>;
0319 status = "disabled";
0320 };
0321 };
0322
0323 saw0: power-controller@f9089000 {
0324 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
0325 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
0326 };
0327
0328 saw1: power-controller@f9099000 {
0329 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
0330 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
0331 };
0332
0333 saw2: power-controller@f90a9000 {
0334 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
0335 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
0336 };
0337
0338 saw3: power-controller@f90b9000 {
0339 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
0340 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
0341 };
0342
0343 saw_l2: power-controller@f9012000 {
0344 compatible = "qcom,saw2";
0345 reg = <0xf9012000 0x1000>;
0346 regulator;
0347 };
0348
0349 acc0: clock-controller@f9088000 {
0350 compatible = "qcom,kpss-acc-v2";
0351 reg = <0xf9088000 0x1000>,
0352 <0xf9008000 0x1000>;
0353 };
0354
0355 acc1: clock-controller@f9098000 {
0356 compatible = "qcom,kpss-acc-v2";
0357 reg = <0xf9098000 0x1000>,
0358 <0xf9008000 0x1000>;
0359 };
0360
0361 acc2: clock-controller@f90a8000 {
0362 compatible = "qcom,kpss-acc-v2";
0363 reg = <0xf90a8000 0x1000>,
0364 <0xf9008000 0x1000>;
0365 };
0366
0367 acc3: clock-controller@f90b8000 {
0368 compatible = "qcom,kpss-acc-v2";
0369 reg = <0xf90b8000 0x1000>,
0370 <0xf9008000 0x1000>;
0371 };
0372
0373 restart@fc4ab000 {
0374 compatible = "qcom,pshold";
0375 reg = <0xfc4ab000 0x4>;
0376 };
0377
0378 gcc: clock-controller@fc400000 {
0379 compatible = "qcom,gcc-apq8084";
0380 #clock-cells = <1>;
0381 #reset-cells = <1>;
0382 #power-domain-cells = <1>;
0383 reg = <0xfc400000 0x4000>;
0384 };
0385
0386 tcsr_mutex_regs: syscon@fd484000 {
0387 compatible = "syscon";
0388 reg = <0xfd484000 0x2000>;
0389 };
0390
0391 tcsr_mutex: hwlock {
0392 compatible = "qcom,tcsr-mutex";
0393 syscon = <&tcsr_mutex_regs 0 0x80>;
0394 #hwlock-cells = <1>;
0395 };
0396
0397 rpm_msg_ram: memory@fc428000 {
0398 compatible = "qcom,rpm-msg-ram";
0399 reg = <0xfc428000 0x4000>;
0400 };
0401
0402 tlmm: pinctrl@fd510000 {
0403 compatible = "qcom,apq8084-pinctrl";
0404 reg = <0xfd510000 0x4000>;
0405 gpio-controller;
0406 gpio-ranges = <&tlmm 0 0 147>;
0407 #gpio-cells = <2>;
0408 interrupt-controller;
0409 #interrupt-cells = <2>;
0410 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
0411 };
0412
0413 blsp2_uart2: serial@f995e000 {
0414 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0415 reg = <0xf995e000 0x1000>;
0416 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0417 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
0418 clock-names = "core", "iface";
0419 status = "disabled";
0420 };
0421
0422 mmc@f9824900 {
0423 compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
0424 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
0425 reg-names = "hc_mem", "core_mem";
0426 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
0427 interrupt-names = "hc_irq", "pwr_irq";
0428 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
0429 <&gcc GCC_SDCC1_AHB_CLK>,
0430 <&xo_board>;
0431 clock-names = "core", "iface", "xo";
0432 status = "disabled";
0433 };
0434
0435 mmc@f98a4900 {
0436 compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
0437 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
0438 reg-names = "hc_mem", "core_mem";
0439 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
0440 interrupt-names = "hc_irq", "pwr_irq";
0441 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
0442 <&gcc GCC_SDCC2_AHB_CLK>,
0443 <&xo_board>;
0444 clock-names = "core", "iface", "xo";
0445 status = "disabled";
0446 };
0447
0448 spmi_bus: spmi@fc4cf000 {
0449 compatible = "qcom,spmi-pmic-arb";
0450 reg-names = "core", "intr", "cnfg";
0451 reg = <0xfc4cf000 0x1000>,
0452 <0xfc4cb000 0x1000>,
0453 <0xfc4ca000 0x1000>;
0454 interrupt-names = "periph_irq";
0455 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
0456 qcom,ee = <0>;
0457 qcom,channel = <0>;
0458 #address-cells = <2>;
0459 #size-cells = <0>;
0460 interrupt-controller;
0461 #interrupt-cells = <4>;
0462 };
0463 };
0464
0465 smd {
0466 compatible = "qcom,smd";
0467
0468 rpm {
0469 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
0470 qcom,ipc = <&apcs 8 0>;
0471 qcom,smd-edge = <15>;
0472
0473 rpm-requests {
0474 compatible = "qcom,rpm-apq8084";
0475 qcom,smd-channels = "rpm_requests";
0476
0477 pma8084-regulators {
0478 compatible = "qcom,rpm-pma8084-regulators";
0479
0480 pma8084_s1: s1 {};
0481 pma8084_s2: s2 {};
0482 pma8084_s3: s3 {};
0483 pma8084_s4: s4 {};
0484 pma8084_s5: s5 {};
0485 pma8084_s6: s6 {};
0486 pma8084_s7: s7 {};
0487 pma8084_s8: s8 {};
0488 pma8084_s9: s9 {};
0489 pma8084_s10: s10 {};
0490 pma8084_s11: s11 {};
0491 pma8084_s12: s12 {};
0492
0493 pma8084_l1: l1 {};
0494 pma8084_l2: l2 {};
0495 pma8084_l3: l3 {};
0496 pma8084_l4: l4 {};
0497 pma8084_l5: l5 {};
0498 pma8084_l6: l6 {};
0499 pma8084_l7: l7 {};
0500 pma8084_l8: l8 {};
0501 pma8084_l9: l9 {};
0502 pma8084_l10: l10 {};
0503 pma8084_l11: l11 {};
0504 pma8084_l12: l12 {};
0505 pma8084_l13: l13 {};
0506 pma8084_l14: l14 {};
0507 pma8084_l15: l15 {};
0508 pma8084_l16: l16 {};
0509 pma8084_l17: l17 {};
0510 pma8084_l18: l18 {};
0511 pma8084_l19: l19 {};
0512 pma8084_l20: l20 {};
0513 pma8084_l21: l21 {};
0514 pma8084_l22: l22 {};
0515 pma8084_l23: l23 {};
0516 pma8084_l24: l24 {};
0517 pma8084_l25: l25 {};
0518 pma8084_l26: l26 {};
0519 pma8084_l27: l27 {};
0520
0521 pma8084_lvs1: lvs1 {};
0522 pma8084_lvs2: lvs2 {};
0523 pma8084_lvs3: lvs3 {};
0524 pma8084_lvs4: lvs4 {};
0525
0526 pma8084_5vs1: 5vs1 {};
0527 };
0528 };
0529 };
0530 };
0531 };
