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0001 // SPDX-License-Identifier: GPL-2.0
0002 /dts-v1/;
0003
0004 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
0005 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
0006 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
0007 #include <dt-bindings/clock/qcom,rpmcc.h>
0008 #include <dt-bindings/soc/qcom,gsbi.h>
0009 #include <dt-bindings/interrupt-controller/irq.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 / {
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 model = "Qualcomm APQ8064";
0015 compatible = "qcom,apq8064";
0016 interrupt-parent = <&intc>;
0017
0018 reserved-memory {
0019 #address-cells = <1>;
0020 #size-cells = <1>;
0021 ranges;
0022
0023 smem_region: smem@80000000 {
0024 reg = <0x80000000 0x200000>;
0025 no-map;
0026 };
0027
0028 wcnss_mem: wcnss@8f000000 {
0029 reg = <0x8f000000 0x700000>;
0030 no-map;
0031 };
0032 };
0033
0034 cpus {
0035 #address-cells = <1>;
0036 #size-cells = <0>;
0037
0038 CPU0: cpu@0 {
0039 compatible = "qcom,krait";
0040 enable-method = "qcom,kpss-acc-v1";
0041 device_type = "cpu";
0042 reg = <0>;
0043 next-level-cache = <&L2>;
0044 qcom,acc = <&acc0>;
0045 qcom,saw = <&saw0>;
0046 cpu-idle-states = <&CPU_SPC>;
0047 };
0048
0049 CPU1: cpu@1 {
0050 compatible = "qcom,krait";
0051 enable-method = "qcom,kpss-acc-v1";
0052 device_type = "cpu";
0053 reg = <1>;
0054 next-level-cache = <&L2>;
0055 qcom,acc = <&acc1>;
0056 qcom,saw = <&saw1>;
0057 cpu-idle-states = <&CPU_SPC>;
0058 };
0059
0060 CPU2: cpu@2 {
0061 compatible = "qcom,krait";
0062 enable-method = "qcom,kpss-acc-v1";
0063 device_type = "cpu";
0064 reg = <2>;
0065 next-level-cache = <&L2>;
0066 qcom,acc = <&acc2>;
0067 qcom,saw = <&saw2>;
0068 cpu-idle-states = <&CPU_SPC>;
0069 };
0070
0071 CPU3: cpu@3 {
0072 compatible = "qcom,krait";
0073 enable-method = "qcom,kpss-acc-v1";
0074 device_type = "cpu";
0075 reg = <3>;
0076 next-level-cache = <&L2>;
0077 qcom,acc = <&acc3>;
0078 qcom,saw = <&saw3>;
0079 cpu-idle-states = <&CPU_SPC>;
0080 };
0081
0082 L2: l2-cache {
0083 compatible = "cache";
0084 cache-level = <2>;
0085 };
0086
0087 idle-states {
0088 CPU_SPC: spc {
0089 compatible = "qcom,idle-state-spc",
0090 "arm,idle-state";
0091 entry-latency-us = <400>;
0092 exit-latency-us = <900>;
0093 min-residency-us = <3000>;
0094 };
0095 };
0096 };
0097
0098 memory@0 {
0099 device_type = "memory";
0100 reg = <0x0 0x0>;
0101 };
0102
0103 thermal-zones {
0104 cpu0-thermal {
0105 polling-delay-passive = <250>;
0106 polling-delay = <1000>;
0107
0108 thermal-sensors = <&tsens 7>;
0109 coefficients = <1199 0>;
0110
0111 trips {
0112 cpu_alert0: trip0 {
0113 temperature = <75000>;
0114 hysteresis = <2000>;
0115 type = "passive";
0116 };
0117 cpu_crit0: trip1 {
0118 temperature = <110000>;
0119 hysteresis = <2000>;
0120 type = "critical";
0121 };
0122 };
0123 };
0124
0125 cpu1-thermal {
0126 polling-delay-passive = <250>;
0127 polling-delay = <1000>;
0128
0129 thermal-sensors = <&tsens 8>;
0130 coefficients = <1132 0>;
0131
0132 trips {
0133 cpu_alert1: trip0 {
0134 temperature = <75000>;
0135 hysteresis = <2000>;
0136 type = "passive";
0137 };
0138 cpu_crit1: trip1 {
0139 temperature = <110000>;
0140 hysteresis = <2000>;
0141 type = "critical";
0142 };
0143 };
0144 };
0145
0146 cpu2-thermal {
0147 polling-delay-passive = <250>;
0148 polling-delay = <1000>;
0149
0150 thermal-sensors = <&tsens 9>;
0151 coefficients = <1199 0>;
0152
0153 trips {
0154 cpu_alert2: trip0 {
0155 temperature = <75000>;
0156 hysteresis = <2000>;
0157 type = "passive";
0158 };
0159 cpu_crit2: trip1 {
0160 temperature = <110000>;
0161 hysteresis = <2000>;
0162 type = "critical";
0163 };
0164 };
0165 };
0166
0167 cpu3-thermal {
0168 polling-delay-passive = <250>;
0169 polling-delay = <1000>;
0170
0171 thermal-sensors = <&tsens 10>;
0172 coefficients = <1132 0>;
0173
0174 trips {
0175 cpu_alert3: trip0 {
0176 temperature = <75000>;
0177 hysteresis = <2000>;
0178 type = "passive";
0179 };
0180 cpu_crit3: trip1 {
0181 temperature = <110000>;
0182 hysteresis = <2000>;
0183 type = "critical";
0184 };
0185 };
0186 };
0187 };
0188
0189 cpu-pmu {
0190 compatible = "qcom,krait-pmu";
0191 interrupts = <1 10 0x304>;
0192 };
0193
0194 clocks {
0195 cxo_board: cxo_board {
0196 compatible = "fixed-clock";
0197 #clock-cells = <0>;
0198 clock-frequency = <19200000>;
0199 };
0200
0201 pxo_board: pxo_board {
0202 compatible = "fixed-clock";
0203 #clock-cells = <0>;
0204 clock-frequency = <27000000>;
0205 };
0206
0207 sleep_clk: sleep_clk {
0208 compatible = "fixed-clock";
0209 #clock-cells = <0>;
0210 clock-frequency = <32768>;
0211 };
0212 };
0213
0214 sfpb_mutex: hwmutex {
0215 compatible = "qcom,sfpb-mutex";
0216 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
0217 #hwlock-cells = <1>;
0218 };
0219
0220 smem {
0221 compatible = "qcom,smem";
0222 memory-region = <&smem_region>;
0223
0224 hwlocks = <&sfpb_mutex 3>;
0225 };
0226
0227 smd {
0228 compatible = "qcom,smd";
0229
0230 modem-edge {
0231 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
0232
0233 qcom,ipc = <&l2cc 8 3>;
0234 qcom,smd-edge = <0>;
0235
0236 status = "disabled";
0237 };
0238
0239 q6-edge {
0240 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
0241
0242 qcom,ipc = <&l2cc 8 15>;
0243 qcom,smd-edge = <1>;
0244
0245 status = "disabled";
0246 };
0247
0248 dsps-edge {
0249 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
0250
0251 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
0252 qcom,smd-edge = <3>;
0253
0254 status = "disabled";
0255 };
0256
0257 riva-edge {
0258 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
0259
0260 qcom,ipc = <&l2cc 8 25>;
0261 qcom,smd-edge = <6>;
0262
0263 status = "disabled";
0264 };
0265 };
0266
0267 smsm {
0268 compatible = "qcom,smsm";
0269
0270 #address-cells = <1>;
0271 #size-cells = <0>;
0272
0273 qcom,ipc-1 = <&l2cc 8 4>;
0274 qcom,ipc-2 = <&l2cc 8 14>;
0275 qcom,ipc-3 = <&l2cc 8 23>;
0276 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
0277
0278 apps_smsm: apps@0 {
0279 reg = <0>;
0280 #qcom,smem-state-cells = <1>;
0281 };
0282
0283 modem_smsm: modem@1 {
0284 reg = <1>;
0285 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
0286
0287 interrupt-controller;
0288 #interrupt-cells = <2>;
0289 };
0290
0291 q6_smsm: q6@2 {
0292 reg = <2>;
0293 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
0294
0295 interrupt-controller;
0296 #interrupt-cells = <2>;
0297 };
0298
0299 wcnss_smsm: wcnss@3 {
0300 reg = <3>;
0301 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
0302
0303 interrupt-controller;
0304 #interrupt-cells = <2>;
0305 };
0306
0307 dsps_smsm: dsps@4 {
0308 reg = <4>;
0309 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
0310
0311 interrupt-controller;
0312 #interrupt-cells = <2>;
0313 };
0314 };
0315
0316 firmware {
0317 scm {
0318 compatible = "qcom,scm-apq8064", "qcom,scm";
0319
0320 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
0321 clock-names = "core";
0322 };
0323 };
0324
0325
0326 /*
0327 * These channels from the ADC are simply hardware monitors.
0328 * That is why the ADC is referred to as "HKADC" - HouseKeeping
0329 * ADC.
0330 */
0331 iio-hwmon {
0332 compatible = "iio-hwmon";
0333 io-channels = <&xoadc 0x00 0x01>, /* Battery */
0334 <&xoadc 0x00 0x02>, /* DC in (charger) */
0335 <&xoadc 0x00 0x04>, /* VPH the main system voltage */
0336 <&xoadc 0x00 0x0b>, /* Die temperature */
0337 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
0338 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
0339 <&xoadc 0x00 0x0e>; /* Charger temperature */
0340 };
0341
0342 soc: soc {
0343 #address-cells = <1>;
0344 #size-cells = <1>;
0345 ranges;
0346 compatible = "simple-bus";
0347
0348 tlmm_pinmux: pinctrl@800000 {
0349 compatible = "qcom,apq8064-pinctrl";
0350 reg = <0x800000 0x4000>;
0351
0352 gpio-controller;
0353 gpio-ranges = <&tlmm_pinmux 0 0 90>;
0354 #gpio-cells = <2>;
0355 interrupt-controller;
0356 #interrupt-cells = <2>;
0357 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
0358
0359 pinctrl-names = "default";
0360 pinctrl-0 = <&ps_hold>;
0361 };
0362
0363 sfpb_wrapper_mutex: syscon@1200000 {
0364 compatible = "syscon";
0365 reg = <0x01200000 0x8000>;
0366 };
0367
0368 intc: interrupt-controller@2000000 {
0369 compatible = "qcom,msm-qgic2";
0370 interrupt-controller;
0371 #interrupt-cells = <3>;
0372 reg = <0x02000000 0x1000>,
0373 <0x02002000 0x1000>;
0374 };
0375
0376 timer@200a000 {
0377 compatible = "qcom,kpss-timer",
0378 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
0379 interrupts = <1 1 0x301>,
0380 <1 2 0x301>,
0381 <1 3 0x301>;
0382 reg = <0x0200a000 0x100>;
0383 clock-frequency = <27000000>,
0384 <32768>;
0385 cpu-offset = <0x80000>;
0386 };
0387
0388 acc0: clock-controller@2088000 {
0389 compatible = "qcom,kpss-acc-v1";
0390 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
0391 };
0392
0393 acc1: clock-controller@2098000 {
0394 compatible = "qcom,kpss-acc-v1";
0395 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
0396 };
0397
0398 acc2: clock-controller@20a8000 {
0399 compatible = "qcom,kpss-acc-v1";
0400 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
0401 };
0402
0403 acc3: clock-controller@20b8000 {
0404 compatible = "qcom,kpss-acc-v1";
0405 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
0406 };
0407
0408 saw0: power-controller@2089000 {
0409 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
0410 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
0411 regulator;
0412 };
0413
0414 saw1: power-controller@2099000 {
0415 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
0416 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
0417 regulator;
0418 };
0419
0420 saw2: power-controller@20a9000 {
0421 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
0422 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
0423 regulator;
0424 };
0425
0426 saw3: power-controller@20b9000 {
0427 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
0428 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
0429 regulator;
0430 };
0431
0432 sps_sic_non_secure: sps-sic-non-secure@12100000 {
0433 compatible = "syscon";
0434 reg = <0x12100000 0x10000>;
0435 };
0436
0437 gsbi1: gsbi@12440000 {
0438 status = "disabled";
0439 compatible = "qcom,gsbi-v1.0.0";
0440 cell-index = <1>;
0441 reg = <0x12440000 0x100>;
0442 clocks = <&gcc GSBI1_H_CLK>;
0443 clock-names = "iface";
0444 #address-cells = <1>;
0445 #size-cells = <1>;
0446 ranges;
0447
0448 syscon-tcsr = <&tcsr>;
0449
0450 gsbi1_serial: serial@12450000 {
0451 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
0452 reg = <0x12450000 0x100>,
0453 <0x12400000 0x03>;
0454 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
0455 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
0456 clock-names = "core", "iface";
0457 status = "disabled";
0458 };
0459
0460 gsbi1_i2c: i2c@12460000 {
0461 compatible = "qcom,i2c-qup-v1.1.1";
0462 pinctrl-0 = <&i2c1_pins>;
0463 pinctrl-1 = <&i2c1_pins_sleep>;
0464 pinctrl-names = "default", "sleep";
0465 reg = <0x12460000 0x1000>;
0466 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
0467 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
0468 clock-names = "core", "iface";
0469 #address-cells = <1>;
0470 #size-cells = <0>;
0471 status = "disabled";
0472 };
0473
0474 };
0475
0476 gsbi2: gsbi@12480000 {
0477 status = "disabled";
0478 compatible = "qcom,gsbi-v1.0.0";
0479 cell-index = <2>;
0480 reg = <0x12480000 0x100>;
0481 clocks = <&gcc GSBI2_H_CLK>;
0482 clock-names = "iface";
0483 #address-cells = <1>;
0484 #size-cells = <1>;
0485 ranges;
0486
0487 syscon-tcsr = <&tcsr>;
0488
0489 gsbi2_i2c: i2c@124a0000 {
0490 compatible = "qcom,i2c-qup-v1.1.1";
0491 reg = <0x124a0000 0x1000>;
0492 pinctrl-0 = <&i2c2_pins>;
0493 pinctrl-1 = <&i2c2_pins_sleep>;
0494 pinctrl-names = "default", "sleep";
0495 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
0496 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
0497 clock-names = "core", "iface";
0498 #address-cells = <1>;
0499 #size-cells = <0>;
0500 status = "disabled";
0501 };
0502 };
0503
0504 gsbi3: gsbi@16200000 {
0505 status = "disabled";
0506 compatible = "qcom,gsbi-v1.0.0";
0507 cell-index = <3>;
0508 reg = <0x16200000 0x100>;
0509 clocks = <&gcc GSBI3_H_CLK>;
0510 clock-names = "iface";
0511 #address-cells = <1>;
0512 #size-cells = <1>;
0513 ranges;
0514 gsbi3_i2c: i2c@16280000 {
0515 compatible = "qcom,i2c-qup-v1.1.1";
0516 pinctrl-0 = <&i2c3_pins>;
0517 pinctrl-1 = <&i2c3_pins_sleep>;
0518 pinctrl-names = "default", "sleep";
0519 reg = <0x16280000 0x1000>;
0520 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
0521 clocks = <&gcc GSBI3_QUP_CLK>,
0522 <&gcc GSBI3_H_CLK>;
0523 clock-names = "core", "iface";
0524 #address-cells = <1>;
0525 #size-cells = <0>;
0526 status = "disabled";
0527 };
0528 };
0529
0530 gsbi4: gsbi@16300000 {
0531 status = "disabled";
0532 compatible = "qcom,gsbi-v1.0.0";
0533 cell-index = <4>;
0534 reg = <0x16300000 0x03>;
0535 clocks = <&gcc GSBI4_H_CLK>;
0536 clock-names = "iface";
0537 #address-cells = <1>;
0538 #size-cells = <1>;
0539 ranges;
0540
0541 gsbi4_i2c: i2c@16380000 {
0542 compatible = "qcom,i2c-qup-v1.1.1";
0543 pinctrl-0 = <&i2c4_pins>;
0544 pinctrl-1 = <&i2c4_pins_sleep>;
0545 pinctrl-names = "default", "sleep";
0546 reg = <0x16380000 0x1000>;
0547 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
0548 clocks = <&gcc GSBI4_QUP_CLK>,
0549 <&gcc GSBI4_H_CLK>;
0550 clock-names = "core", "iface";
0551 status = "disabled";
0552 };
0553 };
0554
0555 gsbi5: gsbi@1a200000 {
0556 status = "disabled";
0557 compatible = "qcom,gsbi-v1.0.0";
0558 cell-index = <5>;
0559 reg = <0x1a200000 0x03>;
0560 clocks = <&gcc GSBI5_H_CLK>;
0561 clock-names = "iface";
0562 #address-cells = <1>;
0563 #size-cells = <1>;
0564 ranges;
0565
0566 gsbi5_serial: serial@1a240000 {
0567 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
0568 reg = <0x1a240000 0x100>,
0569 <0x1a200000 0x03>;
0570 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
0571 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
0572 clock-names = "core", "iface";
0573 status = "disabled";
0574 };
0575
0576 gsbi5_spi: spi@1a280000 {
0577 compatible = "qcom,spi-qup-v1.1.1";
0578 reg = <0x1a280000 0x1000>;
0579 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
0580 pinctrl-0 = <&spi5_default>;
0581 pinctrl-1 = <&spi5_sleep>;
0582 pinctrl-names = "default", "sleep";
0583 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
0584 clock-names = "core", "iface";
0585 status = "disabled";
0586 #address-cells = <1>;
0587 #size-cells = <0>;
0588 };
0589 };
0590
0591 gsbi6: gsbi@16500000 {
0592 status = "disabled";
0593 compatible = "qcom,gsbi-v1.0.0";
0594 cell-index = <6>;
0595 reg = <0x16500000 0x03>;
0596 clocks = <&gcc GSBI6_H_CLK>;
0597 clock-names = "iface";
0598 #address-cells = <1>;
0599 #size-cells = <1>;
0600 ranges;
0601
0602 gsbi6_serial: serial@16540000 {
0603 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
0604 reg = <0x16540000 0x100>,
0605 <0x16500000 0x03>;
0606 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
0607 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
0608 clock-names = "core", "iface";
0609 status = "disabled";
0610 };
0611
0612 gsbi6_i2c: i2c@16580000 {
0613 compatible = "qcom,i2c-qup-v1.1.1";
0614 pinctrl-0 = <&i2c6_pins>;
0615 pinctrl-1 = <&i2c6_pins_sleep>;
0616 pinctrl-names = "default", "sleep";
0617 reg = <0x16580000 0x1000>;
0618 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
0619 clocks = <&gcc GSBI6_QUP_CLK>,
0620 <&gcc GSBI6_H_CLK>;
0621 clock-names = "core", "iface";
0622 status = "disabled";
0623 };
0624 };
0625
0626 gsbi7: gsbi@16600000 {
0627 status = "disabled";
0628 compatible = "qcom,gsbi-v1.0.0";
0629 cell-index = <7>;
0630 reg = <0x16600000 0x100>;
0631 clocks = <&gcc GSBI7_H_CLK>;
0632 clock-names = "iface";
0633 #address-cells = <1>;
0634 #size-cells = <1>;
0635 ranges;
0636 syscon-tcsr = <&tcsr>;
0637
0638 gsbi7_serial: serial@16640000 {
0639 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
0640 reg = <0x16640000 0x1000>,
0641 <0x16600000 0x1000>;
0642 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
0643 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
0644 clock-names = "core", "iface";
0645 status = "disabled";
0646 };
0647
0648 gsbi7_i2c: i2c@16680000 {
0649 compatible = "qcom,i2c-qup-v1.1.1";
0650 pinctrl-0 = <&i2c7_pins>;
0651 pinctrl-1 = <&i2c7_pins_sleep>;
0652 pinctrl-names = "default", "sleep";
0653 reg = <0x16680000 0x1000>;
0654 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
0655 clocks = <&gcc GSBI7_QUP_CLK>,
0656 <&gcc GSBI7_H_CLK>;
0657 clock-names = "core", "iface";
0658 status = "disabled";
0659 };
0660 };
0661
0662 rng@1a500000 {
0663 compatible = "qcom,prng";
0664 reg = <0x1a500000 0x200>;
0665 clocks = <&gcc PRNG_CLK>;
0666 clock-names = "core";
0667 };
0668
0669 ssbi@c00000 {
0670 compatible = "qcom,ssbi";
0671 reg = <0x00c00000 0x1000>;
0672 qcom,controller-type = "pmic-arbiter";
0673
0674 pm8821: pmic@1 {
0675 compatible = "qcom,pm8821";
0676 interrupt-parent = <&tlmm_pinmux>;
0677 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
0678 #interrupt-cells = <2>;
0679 interrupt-controller;
0680 #address-cells = <1>;
0681 #size-cells = <0>;
0682
0683 pm8821_mpps: mpps@50 {
0684 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
0685 reg = <0x50>;
0686 interrupt-controller;
0687 #interrupt-cells = <2>;
0688 gpio-controller;
0689 #gpio-cells = <2>;
0690 gpio-ranges = <&pm8821_mpps 0 0 4>;
0691 };
0692 };
0693 };
0694
0695 qcom,ssbi@500000 {
0696 compatible = "qcom,ssbi";
0697 reg = <0x00500000 0x1000>;
0698 qcom,controller-type = "pmic-arbiter";
0699
0700 pmicintc: pmic@0 {
0701 compatible = "qcom,pm8921";
0702 interrupt-parent = <&tlmm_pinmux>;
0703 interrupts = <74 8>;
0704 #interrupt-cells = <2>;
0705 interrupt-controller;
0706 #address-cells = <1>;
0707 #size-cells = <0>;
0708
0709 pm8921_gpio: gpio@150 {
0710
0711 compatible = "qcom,pm8921-gpio",
0712 "qcom,ssbi-gpio";
0713 reg = <0x150>;
0714 interrupt-controller;
0715 #interrupt-cells = <2>;
0716 gpio-controller;
0717 gpio-ranges = <&pm8921_gpio 0 0 44>;
0718 #gpio-cells = <2>;
0719
0720 };
0721
0722 pm8921_mpps: mpps@50 {
0723 compatible = "qcom,pm8921-mpp",
0724 "qcom,ssbi-mpp";
0725 reg = <0x50>;
0726 gpio-controller;
0727 #gpio-cells = <2>;
0728 gpio-ranges = <&pm8921_mpps 0 0 12>;
0729 interrupt-controller;
0730 #interrupt-cells = <2>;
0731 };
0732
0733 rtc@11d {
0734 compatible = "qcom,pm8921-rtc";
0735 interrupt-parent = <&pmicintc>;
0736 interrupts = <39 1>;
0737 reg = <0x11d>;
0738 allow-set-time;
0739 };
0740
0741 pwrkey@1c {
0742 compatible = "qcom,pm8921-pwrkey";
0743 reg = <0x1c>;
0744 interrupt-parent = <&pmicintc>;
0745 interrupts = <50 1>, <51 1>;
0746 debounce = <15625>;
0747 pull-up;
0748 };
0749
0750 xoadc: xoadc@197 {
0751 compatible = "qcom,pm8921-adc";
0752 reg = <197>;
0753 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
0754 #address-cells = <2>;
0755 #size-cells = <0>;
0756 #io-channel-cells = <2>;
0757
0758 vcoin: adc-channel@0 {
0759 reg = <0x00 0x00>;
0760 };
0761 vbat: adc-channel@1 {
0762 reg = <0x00 0x01>;
0763 };
0764 dcin: adc-channel@2 {
0765 reg = <0x00 0x02>;
0766 };
0767 vph_pwr: adc-channel@4 {
0768 reg = <0x00 0x04>;
0769 };
0770 batt_therm: adc-channel@8 {
0771 reg = <0x00 0x08>;
0772 };
0773 batt_id: adc-channel@9 {
0774 reg = <0x00 0x09>;
0775 };
0776 usb_vbus: adc-channel@a {
0777 reg = <0x00 0x0a>;
0778 };
0779 die_temp: adc-channel@b {
0780 reg = <0x00 0x0b>;
0781 };
0782 ref_625mv: adc-channel@c {
0783 reg = <0x00 0x0c>;
0784 };
0785 ref_1250mv: adc-channel@d {
0786 reg = <0x00 0x0d>;
0787 };
0788 chg_temp: adc-channel@e {
0789 reg = <0x00 0x0e>;
0790 };
0791 ref_muxoff: adc-channel@f {
0792 reg = <0x00 0x0f>;
0793 };
0794 };
0795 };
0796 };
0797
0798 qfprom: qfprom@700000 {
0799 compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
0800 reg = <0x00700000 0x1000>;
0801 #address-cells = <1>;
0802 #size-cells = <1>;
0803 ranges;
0804 tsens_calib: calib@404 {
0805 reg = <0x404 0x10>;
0806 };
0807 tsens_backup: backup_calib@414 {
0808 reg = <0x414 0x10>;
0809 };
0810 };
0811
0812 gcc: clock-controller@900000 {
0813 compatible = "qcom,gcc-apq8064", "syscon";
0814 reg = <0x00900000 0x4000>;
0815 #clock-cells = <1>;
0816 #power-domain-cells = <1>;
0817 #reset-cells = <1>;
0818
0819 tsens: thermal-sensor {
0820 compatible = "qcom,msm8960-tsens";
0821
0822 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
0823 nvmem-cell-names = "calib", "calib_backup";
0824 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
0825 interrupt-names = "uplow";
0826
0827 #qcom,sensors = <11>;
0828 #thermal-sensor-cells = <1>;
0829 };
0830 };
0831
0832 lcc: clock-controller@28000000 {
0833 compatible = "qcom,lcc-apq8064";
0834 reg = <0x28000000 0x1000>;
0835 #clock-cells = <1>;
0836 #reset-cells = <1>;
0837 };
0838
0839 mmcc: clock-controller@4000000 {
0840 compatible = "qcom,mmcc-apq8064";
0841 reg = <0x4000000 0x1000>;
0842 #clock-cells = <1>;
0843 #power-domain-cells = <1>;
0844 #reset-cells = <1>;
0845 };
0846
0847 l2cc: clock-controller@2011000 {
0848 compatible = "qcom,kpss-gcc", "syscon";
0849 reg = <0x2011000 0x1000>;
0850 };
0851
0852 rpm@108000 {
0853 compatible = "qcom,rpm-apq8064";
0854 reg = <0x108000 0x1000>;
0855 qcom,ipc = <&l2cc 0x8 2>;
0856
0857 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
0858 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
0859 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
0860 interrupt-names = "ack", "err", "wakeup";
0861
0862 rpmcc: clock-controller {
0863 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
0864 #clock-cells = <1>;
0865 clocks = <&pxo_board>, <&cxo_board>;
0866 clock-names = "pxo", "cxo";
0867 };
0868
0869 regulators {
0870 compatible = "qcom,rpm-pm8921-regulators";
0871
0872 pm8921_s1: s1 {};
0873 pm8921_s2: s2 {};
0874 pm8921_s3: s3 {};
0875 pm8921_s4: s4 {};
0876 pm8921_s7: s7 {};
0877 pm8921_s8: s8 {};
0878
0879 pm8921_l1: l1 {};
0880 pm8921_l2: l2 {};
0881 pm8921_l3: l3 {};
0882 pm8921_l4: l4 {};
0883 pm8921_l5: l5 {};
0884 pm8921_l6: l6 {};
0885 pm8921_l7: l7 {};
0886 pm8921_l8: l8 {};
0887 pm8921_l9: l9 {};
0888 pm8921_l10: l10 {};
0889 pm8921_l11: l11 {};
0890 pm8921_l12: l12 {};
0891 pm8921_l14: l14 {};
0892 pm8921_l15: l15 {};
0893 pm8921_l16: l16 {};
0894 pm8921_l17: l17 {};
0895 pm8921_l18: l18 {};
0896 pm8921_l21: l21 {};
0897 pm8921_l22: l22 {};
0898 pm8921_l23: l23 {};
0899 pm8921_l24: l24 {};
0900 pm8921_l25: l25 {};
0901 pm8921_l26: l26 {};
0902 pm8921_l27: l27 {};
0903 pm8921_l28: l28 {};
0904 pm8921_l29: l29 {};
0905
0906 pm8921_lvs1: lvs1 {};
0907 pm8921_lvs2: lvs2 {};
0908 pm8921_lvs3: lvs3 {};
0909 pm8921_lvs4: lvs4 {};
0910 pm8921_lvs5: lvs5 {};
0911 pm8921_lvs6: lvs6 {};
0912 pm8921_lvs7: lvs7 {};
0913
0914 pm8921_usb_switch: usb-switch {};
0915
0916 pm8921_hdmi_switch: hdmi-switch {
0917 bias-pull-down;
0918 };
0919
0920 pm8921_ncp: ncp {};
0921 };
0922 };
0923
0924 usb1: usb@12500000 {
0925 compatible = "qcom,ci-hdrc";
0926 reg = <0x12500000 0x200>,
0927 <0x12500200 0x200>;
0928 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0929 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
0930 clock-names = "core", "iface";
0931 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
0932 assigned-clock-rates = <60000000>;
0933 resets = <&gcc USB_HS1_RESET>;
0934 reset-names = "core";
0935 phy_type = "ulpi";
0936 ahb-burst-config = <0>;
0937 phys = <&usb_hs1_phy>;
0938 phy-names = "usb-phy";
0939 status = "disabled";
0940 #reset-cells = <1>;
0941
0942 ulpi {
0943 usb_hs1_phy: phy {
0944 compatible = "qcom,usb-hs-phy-apq8064",
0945 "qcom,usb-hs-phy";
0946 clocks = <&sleep_clk>, <&cxo_board>;
0947 clock-names = "sleep", "ref";
0948 resets = <&usb1 0>;
0949 reset-names = "por";
0950 #phy-cells = <0>;
0951 };
0952 };
0953 };
0954
0955 usb3: usb@12520000 {
0956 compatible = "qcom,ci-hdrc";
0957 reg = <0x12520000 0x200>,
0958 <0x12520200 0x200>;
0959 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
0960 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
0961 clock-names = "core", "iface";
0962 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
0963 assigned-clock-rates = <60000000>;
0964 resets = <&gcc USB_HS3_RESET>;
0965 reset-names = "core";
0966 phy_type = "ulpi";
0967 ahb-burst-config = <0>;
0968 phys = <&usb_hs3_phy>;
0969 phy-names = "usb-phy";
0970 status = "disabled";
0971 #reset-cells = <1>;
0972
0973 ulpi {
0974 usb_hs3_phy: phy {
0975 compatible = "qcom,usb-hs-phy-apq8064",
0976 "qcom,usb-hs-phy";
0977 #phy-cells = <0>;
0978 clocks = <&sleep_clk>, <&cxo_board>;
0979 clock-names = "sleep", "ref";
0980 resets = <&usb3 0>;
0981 reset-names = "por";
0982 };
0983 };
0984 };
0985
0986 usb4: usb@12530000 {
0987 compatible = "qcom,ci-hdrc";
0988 reg = <0x12530000 0x200>,
0989 <0x12530200 0x200>;
0990 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
0991 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
0992 clock-names = "core", "iface";
0993 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
0994 assigned-clock-rates = <60000000>;
0995 resets = <&gcc USB_HS4_RESET>;
0996 reset-names = "core";
0997 phy_type = "ulpi";
0998 ahb-burst-config = <0>;
0999 phys = <&usb_hs4_phy>;
1000 phy-names = "usb-phy";
1001 status = "disabled";
1002 #reset-cells = <1>;
1003
1004 ulpi {
1005 usb_hs4_phy: phy {
1006 compatible = "qcom,usb-hs-phy-apq8064",
1007 "qcom,usb-hs-phy";
1008 #phy-cells = <0>;
1009 clocks = <&sleep_clk>, <&cxo_board>;
1010 clock-names = "sleep", "ref";
1011 resets = <&usb4 0>;
1012 reset-names = "por";
1013 };
1014 };
1015 };
1016
1017 sata_phy0: phy@1b400000 {
1018 compatible = "qcom,apq8064-sata-phy";
1019 status = "disabled";
1020 reg = <0x1b400000 0x200>;
1021 reg-names = "phy_mem";
1022 clocks = <&gcc SATA_PHY_CFG_CLK>;
1023 clock-names = "cfg";
1024 #phy-cells = <0>;
1025 };
1026
1027 sata0: sata@29000000 {
1028 compatible = "qcom,apq8064-ahci", "generic-ahci";
1029 status = "disabled";
1030 reg = <0x29000000 0x180>;
1031 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1032
1033 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1034 <&gcc SATA_H_CLK>,
1035 <&gcc SATA_A_CLK>,
1036 <&gcc SATA_RXOOB_CLK>,
1037 <&gcc SATA_PMALIVE_CLK>;
1038 clock-names = "slave_iface",
1039 "iface",
1040 "bus",
1041 "rxoob",
1042 "core_pmalive";
1043
1044 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1045 <&gcc SATA_PMALIVE_CLK>;
1046 assigned-clock-rates = <100000000>, <100000000>;
1047
1048 phys = <&sata_phy0>;
1049 phy-names = "sata-phy";
1050 ports-implemented = <0x1>;
1051 };
1052
1053 /* Temporary fixed regulator */
1054 sdcc1bam: dma-controller@12402000{
1055 compatible = "qcom,bam-v1.3.0";
1056 reg = <0x12402000 0x8000>;
1057 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1058 clocks = <&gcc SDC1_H_CLK>;
1059 clock-names = "bam_clk";
1060 #dma-cells = <1>;
1061 qcom,ee = <0>;
1062 };
1063
1064 sdcc3bam: dma-controller@12182000{
1065 compatible = "qcom,bam-v1.3.0";
1066 reg = <0x12182000 0x8000>;
1067 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
1068 clocks = <&gcc SDC3_H_CLK>;
1069 clock-names = "bam_clk";
1070 #dma-cells = <1>;
1071 qcom,ee = <0>;
1072 };
1073
1074 sdcc4bam: dma-controller@121c2000{
1075 compatible = "qcom,bam-v1.3.0";
1076 reg = <0x121c2000 0x8000>;
1077 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&gcc SDC4_H_CLK>;
1079 clock-names = "bam_clk";
1080 #dma-cells = <1>;
1081 qcom,ee = <0>;
1082 };
1083
1084 amba {
1085 compatible = "simple-bus";
1086 #address-cells = <1>;
1087 #size-cells = <1>;
1088 ranges;
1089 sdcc1: mmc@12400000 {
1090 status = "disabled";
1091 compatible = "arm,pl18x", "arm,primecell";
1092 pinctrl-names = "default";
1093 pinctrl-0 = <&sdcc1_pins>;
1094 arm,primecell-periphid = <0x00051180>;
1095 reg = <0x12400000 0x2000>;
1096 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1097 interrupt-names = "cmd_irq";
1098 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1099 clock-names = "mclk", "apb_pclk";
1100 bus-width = <8>;
1101 max-frequency = <96000000>;
1102 non-removable;
1103 cap-sd-highspeed;
1104 cap-mmc-highspeed;
1105 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1106 dma-names = "tx", "rx";
1107 };
1108
1109 sdcc3: mmc@12180000 {
1110 compatible = "arm,pl18x", "arm,primecell";
1111 arm,primecell-periphid = <0x00051180>;
1112 status = "disabled";
1113 reg = <0x12180000 0x2000>;
1114 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1115 interrupt-names = "cmd_irq";
1116 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1117 clock-names = "mclk", "apb_pclk";
1118 bus-width = <4>;
1119 cap-sd-highspeed;
1120 cap-mmc-highspeed;
1121 max-frequency = <192000000>;
1122 no-1-8-v;
1123 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1124 dma-names = "tx", "rx";
1125 };
1126
1127 sdcc4: mmc@121c0000 {
1128 compatible = "arm,pl18x", "arm,primecell";
1129 arm,primecell-periphid = <0x00051180>;
1130 status = "disabled";
1131 reg = <0x121c0000 0x2000>;
1132 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1133 interrupt-names = "cmd_irq";
1134 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1135 clock-names = "mclk", "apb_pclk";
1136 bus-width = <4>;
1137 cap-sd-highspeed;
1138 cap-mmc-highspeed;
1139 max-frequency = <48000000>;
1140 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1141 dma-names = "tx", "rx";
1142 pinctrl-names = "default";
1143 pinctrl-0 = <&sdc4_gpios>;
1144 };
1145 };
1146
1147 tcsr: syscon@1a400000 {
1148 compatible = "qcom,tcsr-apq8064", "syscon";
1149 reg = <0x1a400000 0x100>;
1150 };
1151
1152 gpu: adreno-3xx@4300000 {
1153 compatible = "qcom,adreno-320.2", "qcom,adreno";
1154 reg = <0x04300000 0x20000>;
1155 reg-names = "kgsl_3d0_reg_memory";
1156 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1157 interrupt-names = "kgsl_3d0_irq";
1158 clock-names =
1159 "core",
1160 "iface",
1161 "mem",
1162 "mem_iface";
1163 clocks =
1164 <&mmcc GFX3D_CLK>,
1165 <&mmcc GFX3D_AHB_CLK>,
1166 <&mmcc GFX3D_AXI_CLK>,
1167 <&mmcc MMSS_IMEM_AHB_CLK>;
1168
1169 iommus = <&gfx3d 0
1170 &gfx3d 1
1171 &gfx3d 2
1172 &gfx3d 3
1173 &gfx3d 4
1174 &gfx3d 5
1175 &gfx3d 6
1176 &gfx3d 7
1177 &gfx3d 8
1178 &gfx3d 9
1179 &gfx3d 10
1180 &gfx3d 11
1181 &gfx3d 12
1182 &gfx3d 13
1183 &gfx3d 14
1184 &gfx3d 15
1185 &gfx3d 16
1186 &gfx3d 17
1187 &gfx3d 18
1188 &gfx3d 19
1189 &gfx3d 20
1190 &gfx3d 21
1191 &gfx3d 22
1192 &gfx3d 23
1193 &gfx3d 24
1194 &gfx3d 25
1195 &gfx3d 26
1196 &gfx3d 27
1197 &gfx3d 28
1198 &gfx3d 29
1199 &gfx3d 30
1200 &gfx3d 31
1201 &gfx3d1 0
1202 &gfx3d1 1
1203 &gfx3d1 2
1204 &gfx3d1 3
1205 &gfx3d1 4
1206 &gfx3d1 5
1207 &gfx3d1 6
1208 &gfx3d1 7
1209 &gfx3d1 8
1210 &gfx3d1 9
1211 &gfx3d1 10
1212 &gfx3d1 11
1213 &gfx3d1 12
1214 &gfx3d1 13
1215 &gfx3d1 14
1216 &gfx3d1 15
1217 &gfx3d1 16
1218 &gfx3d1 17
1219 &gfx3d1 18
1220 &gfx3d1 19
1221 &gfx3d1 20
1222 &gfx3d1 21
1223 &gfx3d1 22
1224 &gfx3d1 23
1225 &gfx3d1 24
1226 &gfx3d1 25
1227 &gfx3d1 26
1228 &gfx3d1 27
1229 &gfx3d1 28
1230 &gfx3d1 29
1231 &gfx3d1 30
1232 &gfx3d1 31>;
1233
1234 operating-points-v2 = <&gpu_opp_table>;
1235
1236 gpu_opp_table: opp-table {
1237 compatible = "operating-points-v2";
1238
1239 opp-320000000 {
1240 opp-hz = /bits/ 64 <450000000>;
1241 };
1242
1243 opp-27000000 {
1244 opp-hz = /bits/ 64 <27000000>;
1245 };
1246 };
1247 };
1248
1249 mmss_sfpb: syscon@5700000 {
1250 compatible = "syscon";
1251 reg = <0x5700000 0x70>;
1252 };
1253
1254 dsi0: dsi@4700000 {
1255 compatible = "qcom,mdss-dsi-ctrl";
1256 label = "MDSS DSI CTRL->0";
1257 #address-cells = <1>;
1258 #size-cells = <0>;
1259 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1260 reg = <0x04700000 0x200>;
1261 reg-names = "dsi_ctrl";
1262
1263 clocks = <&mmcc DSI_M_AHB_CLK>,
1264 <&mmcc DSI_S_AHB_CLK>,
1265 <&mmcc AMP_AHB_CLK>,
1266 <&mmcc DSI_CLK>,
1267 <&mmcc DSI1_BYTE_CLK>,
1268 <&mmcc DSI_PIXEL_CLK>,
1269 <&mmcc DSI1_ESC_CLK>;
1270 clock-names = "iface", "bus", "core_mmss",
1271 "src", "byte", "pixel",
1272 "core";
1273
1274 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1275 <&mmcc DSI1_ESC_SRC>,
1276 <&mmcc DSI_SRC>,
1277 <&mmcc DSI_PIXEL_SRC>;
1278 assigned-clock-parents = <&dsi0_phy 0>,
1279 <&dsi0_phy 0>,
1280 <&dsi0_phy 1>,
1281 <&dsi0_phy 1>;
1282 syscon-sfpb = <&mmss_sfpb>;
1283 phys = <&dsi0_phy>;
1284 phy-names = "dsi";
1285 status = "disabled";
1286
1287 ports {
1288 #address-cells = <1>;
1289 #size-cells = <0>;
1290
1291 port@0 {
1292 reg = <0>;
1293 dsi0_in: endpoint {
1294 };
1295 };
1296
1297 port@1 {
1298 reg = <1>;
1299 dsi0_out: endpoint {
1300 };
1301 };
1302 };
1303 };
1304
1305
1306 dsi0_phy: dsi-phy@4700200 {
1307 compatible = "qcom,dsi-phy-28nm-8960";
1308 #clock-cells = <1>;
1309 #phy-cells = <0>;
1310
1311 reg = <0x04700200 0x100>,
1312 <0x04700300 0x200>,
1313 <0x04700500 0x5c>;
1314 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1315 clock-names = "iface", "ref";
1316 clocks = <&mmcc DSI_M_AHB_CLK>,
1317 <&pxo_board>;
1318 status = "disabled";
1319 };
1320
1321
1322 mdp_port0: iommu@7500000 {
1323 compatible = "qcom,apq8064-iommu";
1324 #iommu-cells = <1>;
1325 clock-names =
1326 "smmu_pclk",
1327 "iommu_clk";
1328 clocks =
1329 <&mmcc SMMU_AHB_CLK>,
1330 <&mmcc MDP_AXI_CLK>;
1331 reg = <0x07500000 0x100000>;
1332 interrupts =
1333 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1335 qcom,ncb = <2>;
1336 };
1337
1338 mdp_port1: iommu@7600000 {
1339 compatible = "qcom,apq8064-iommu";
1340 #iommu-cells = <1>;
1341 clock-names =
1342 "smmu_pclk",
1343 "iommu_clk";
1344 clocks =
1345 <&mmcc SMMU_AHB_CLK>,
1346 <&mmcc MDP_AXI_CLK>;
1347 reg = <0x07600000 0x100000>;
1348 interrupts =
1349 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1350 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1351 qcom,ncb = <2>;
1352 };
1353
1354 gfx3d: iommu@7c00000 {
1355 compatible = "qcom,apq8064-iommu";
1356 #iommu-cells = <1>;
1357 clock-names =
1358 "smmu_pclk",
1359 "iommu_clk";
1360 clocks =
1361 <&mmcc SMMU_AHB_CLK>,
1362 <&mmcc GFX3D_AXI_CLK>;
1363 reg = <0x07c00000 0x100000>;
1364 interrupts =
1365 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1367 qcom,ncb = <3>;
1368 };
1369
1370 gfx3d1: iommu@7d00000 {
1371 compatible = "qcom,apq8064-iommu";
1372 #iommu-cells = <1>;
1373 clock-names =
1374 "smmu_pclk",
1375 "iommu_clk";
1376 clocks =
1377 <&mmcc SMMU_AHB_CLK>,
1378 <&mmcc GFX3D_AXI_CLK>;
1379 reg = <0x07d00000 0x100000>;
1380 interrupts =
1381 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1383 qcom,ncb = <3>;
1384 };
1385
1386 pcie: pci@1b500000 {
1387 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1388 reg = <0x1b500000 0x1000>,
1389 <0x1b502000 0x80>,
1390 <0x1b600000 0x100>,
1391 <0x0ff00000 0x100000>;
1392 reg-names = "dbi", "elbi", "parf", "config";
1393 device_type = "pci";
1394 linux,pci-domain = <0>;
1395 bus-range = <0x00 0xff>;
1396 num-lanes = <1>;
1397 #address-cells = <3>;
1398 #size-cells = <2>;
1399 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, /* I/O */
1400 <0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* mem */
1401 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1402 interrupt-names = "msi";
1403 #interrupt-cells = <1>;
1404 interrupt-map-mask = <0 0 0 0x7>;
1405 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1406 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1407 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1408 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1409 clocks = <&gcc PCIE_A_CLK>,
1410 <&gcc PCIE_H_CLK>,
1411 <&gcc PCIE_PHY_REF_CLK>;
1412 clock-names = "core", "iface", "phy";
1413 resets = <&gcc PCIE_ACLK_RESET>,
1414 <&gcc PCIE_HCLK_RESET>,
1415 <&gcc PCIE_POR_RESET>,
1416 <&gcc PCIE_PCI_RESET>,
1417 <&gcc PCIE_PHY_RESET>;
1418 reset-names = "axi", "ahb", "por", "pci", "phy";
1419 status = "disabled";
1420 };
1421
1422 hdmi: hdmi-tx@4a00000 {
1423 compatible = "qcom,hdmi-tx-8960";
1424 pinctrl-names = "default";
1425 pinctrl-0 = <&hdmi_pinctrl>;
1426 reg = <0x04a00000 0x2f0>;
1427 reg-names = "core_physical";
1428 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1429 clocks = <&mmcc HDMI_APP_CLK>,
1430 <&mmcc HDMI_M_AHB_CLK>,
1431 <&mmcc HDMI_S_AHB_CLK>;
1432 clock-names = "core",
1433 "master_iface",
1434 "slave_iface";
1435
1436 phys = <&hdmi_phy>;
1437
1438 ports {
1439 #address-cells = <1>;
1440 #size-cells = <0>;
1441
1442 port@0 {
1443 reg = <0>;
1444 hdmi_in: endpoint {
1445 };
1446 };
1447
1448 port@1 {
1449 reg = <1>;
1450 hdmi_out: endpoint {
1451 };
1452 };
1453 };
1454 };
1455
1456 hdmi_phy: hdmi-phy@4a00400 {
1457 compatible = "qcom,hdmi-phy-8960";
1458 reg = <0x4a00400 0x60>,
1459 <0x4a00500 0x100>;
1460 reg-names = "hdmi_phy",
1461 "hdmi_pll";
1462
1463 clocks = <&mmcc HDMI_S_AHB_CLK>;
1464 clock-names = "slave_iface";
1465 #phy-cells = <0>;
1466 };
1467
1468 mdp: mdp@5100000 {
1469 compatible = "qcom,mdp4";
1470 reg = <0x05100000 0xf0000>;
1471 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1472 clocks = <&mmcc MDP_CLK>,
1473 <&mmcc MDP_AHB_CLK>,
1474 <&mmcc MDP_AXI_CLK>,
1475 <&mmcc MDP_LUT_CLK>,
1476 <&mmcc HDMI_TV_CLK>,
1477 <&mmcc MDP_TV_CLK>;
1478 clock-names = "core_clk",
1479 "iface_clk",
1480 "bus_clk",
1481 "lut_clk",
1482 "hdmi_clk",
1483 "tv_clk";
1484
1485 iommus = <&mdp_port0 0
1486 &mdp_port0 2
1487 &mdp_port1 0
1488 &mdp_port1 2>;
1489
1490 ports {
1491 #address-cells = <1>;
1492 #size-cells = <0>;
1493
1494 port@0 {
1495 reg = <0>;
1496 mdp_lvds_out: endpoint {
1497 };
1498 };
1499
1500 port@1 {
1501 reg = <1>;
1502 mdp_dsi1_out: endpoint {
1503 };
1504 };
1505
1506 port@2 {
1507 reg = <2>;
1508 mdp_dsi2_out: endpoint {
1509 };
1510 };
1511
1512 port@3 {
1513 reg = <3>;
1514 mdp_dtv_out: endpoint {
1515 };
1516 };
1517 };
1518 };
1519
1520 riva: riva-pil@3204000 {
1521 compatible = "qcom,riva-pil";
1522
1523 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1524 reg-names = "ccu", "dxe", "pmu";
1525
1526 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1527 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1528 interrupt-names = "wdog", "fatal";
1529
1530 memory-region = <&wcnss_mem>;
1531
1532 vddcx-supply = <&pm8921_s3>;
1533 vddmx-supply = <&pm8921_l24>;
1534 vddpx-supply = <&pm8921_s4>;
1535
1536 status = "disabled";
1537
1538 iris {
1539 compatible = "qcom,wcn3660";
1540
1541 clocks = <&cxo_board>;
1542 clock-names = "xo";
1543
1544 vddxo-supply = <&pm8921_l4>;
1545 vddrfa-supply = <&pm8921_s2>;
1546 vddpa-supply = <&pm8921_l10>;
1547 vdddig-supply = <&pm8921_lvs2>;
1548 };
1549
1550 smd-edge {
1551 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1552
1553 qcom,ipc = <&l2cc 8 25>;
1554 qcom,smd-edge = <6>;
1555
1556 label = "riva";
1557
1558 wcnss {
1559 compatible = "qcom,wcnss";
1560 qcom,smd-channels = "WCNSS_CTRL";
1561
1562 qcom,mmio = <&riva>;
1563
1564 bluetooth {
1565 compatible = "qcom,wcnss-bt";
1566 };
1567
1568 wifi {
1569 compatible = "qcom,wcnss-wlan";
1570
1571 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1572 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1573 interrupt-names = "tx", "rx";
1574
1575 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1576 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1577 };
1578 };
1579 };
1580 };
1581
1582 etb@1a01000 {
1583 compatible = "coresight-etb10", "arm,primecell";
1584 reg = <0x1a01000 0x1000>;
1585
1586 clocks = <&rpmcc RPM_QDSS_CLK>;
1587 clock-names = "apb_pclk";
1588
1589 in-ports {
1590 port {
1591 etb_in: endpoint {
1592 remote-endpoint = <&replicator_out0>;
1593 };
1594 };
1595 };
1596 };
1597
1598 tpiu@1a03000 {
1599 compatible = "arm,coresight-tpiu", "arm,primecell";
1600 reg = <0x1a03000 0x1000>;
1601
1602 clocks = <&rpmcc RPM_QDSS_CLK>;
1603 clock-names = "apb_pclk";
1604
1605 in-ports {
1606 port {
1607 tpiu_in: endpoint {
1608 remote-endpoint = <&replicator_out1>;
1609 };
1610 };
1611 };
1612 };
1613
1614 replicator {
1615 compatible = "arm,coresight-static-replicator";
1616
1617 clocks = <&rpmcc RPM_QDSS_CLK>;
1618 clock-names = "apb_pclk";
1619
1620 out-ports {
1621 #address-cells = <1>;
1622 #size-cells = <0>;
1623
1624 port@0 {
1625 reg = <0>;
1626 replicator_out0: endpoint {
1627 remote-endpoint = <&etb_in>;
1628 };
1629 };
1630 port@1 {
1631 reg = <1>;
1632 replicator_out1: endpoint {
1633 remote-endpoint = <&tpiu_in>;
1634 };
1635 };
1636 };
1637
1638 in-ports {
1639 port {
1640 replicator_in: endpoint {
1641 remote-endpoint = <&funnel_out>;
1642 };
1643 };
1644 };
1645 };
1646
1647 funnel@1a04000 {
1648 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1649 reg = <0x1a04000 0x1000>;
1650
1651 clocks = <&rpmcc RPM_QDSS_CLK>;
1652 clock-names = "apb_pclk";
1653
1654 in-ports {
1655 #address-cells = <1>;
1656 #size-cells = <0>;
1657
1658 /*
1659 * Not described input ports:
1660 * 2 - connected to STM component
1661 * 3 - not-connected
1662 * 6 - not-connected
1663 * 7 - not-connected
1664 */
1665 port@0 {
1666 reg = <0>;
1667 funnel_in0: endpoint {
1668 remote-endpoint = <&etm0_out>;
1669 };
1670 };
1671 port@1 {
1672 reg = <1>;
1673 funnel_in1: endpoint {
1674 remote-endpoint = <&etm1_out>;
1675 };
1676 };
1677 port@4 {
1678 reg = <4>;
1679 funnel_in4: endpoint {
1680 remote-endpoint = <&etm2_out>;
1681 };
1682 };
1683 port@5 {
1684 reg = <5>;
1685 funnel_in5: endpoint {
1686 remote-endpoint = <&etm3_out>;
1687 };
1688 };
1689 };
1690
1691 out-ports {
1692 port {
1693 funnel_out: endpoint {
1694 remote-endpoint = <&replicator_in>;
1695 };
1696 };
1697 };
1698 };
1699
1700 etm@1a1c000 {
1701 compatible = "arm,coresight-etm3x", "arm,primecell";
1702 reg = <0x1a1c000 0x1000>;
1703
1704 clocks = <&rpmcc RPM_QDSS_CLK>;
1705 clock-names = "apb_pclk";
1706
1707 cpu = <&CPU0>;
1708
1709 out-ports {
1710 port {
1711 etm0_out: endpoint {
1712 remote-endpoint = <&funnel_in0>;
1713 };
1714 };
1715 };
1716 };
1717
1718 etm@1a1d000 {
1719 compatible = "arm,coresight-etm3x", "arm,primecell";
1720 reg = <0x1a1d000 0x1000>;
1721
1722 clocks = <&rpmcc RPM_QDSS_CLK>;
1723 clock-names = "apb_pclk";
1724
1725 cpu = <&CPU1>;
1726
1727 out-ports {
1728 port {
1729 etm1_out: endpoint {
1730 remote-endpoint = <&funnel_in1>;
1731 };
1732 };
1733 };
1734 };
1735
1736 etm@1a1e000 {
1737 compatible = "arm,coresight-etm3x", "arm,primecell";
1738 reg = <0x1a1e000 0x1000>;
1739
1740 clocks = <&rpmcc RPM_QDSS_CLK>;
1741 clock-names = "apb_pclk";
1742
1743 cpu = <&CPU2>;
1744
1745 out-ports {
1746 port {
1747 etm2_out: endpoint {
1748 remote-endpoint = <&funnel_in4>;
1749 };
1750 };
1751 };
1752 };
1753
1754 etm@1a1f000 {
1755 compatible = "arm,coresight-etm3x", "arm,primecell";
1756 reg = <0x1a1f000 0x1000>;
1757
1758 clocks = <&rpmcc RPM_QDSS_CLK>;
1759 clock-names = "apb_pclk";
1760
1761 cpu = <&CPU3>;
1762
1763 out-ports {
1764 port {
1765 etm3_out: endpoint {
1766 remote-endpoint = <&funnel_in5>;
1767 };
1768 };
1769 };
1770 };
1771 };
1772 };
1773 #include "qcom-apq8064-pins.dtsi"
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