0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2012 Marvell Technology Group Ltd.
0004 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
0005 */
0006
0007 #include <dt-bindings/clock/marvell,pxa910.h>
0008
0009 / {
0010 #address-cells = <1>;
0011 #size-cells = <1>;
0012
0013 aliases {
0014 serial0 = &uart1;
0015 serial1 = &uart2;
0016 serial2 = &uart3;
0017 i2c0 = &twsi1;
0018 i2c1 = &twsi2;
0019 };
0020
0021 soc {
0022 #address-cells = <1>;
0023 #size-cells = <1>;
0024 compatible = "simple-bus";
0025 interrupt-parent = <&intc>;
0026 ranges;
0027
0028 L2: l2-cache {
0029 compatible = "marvell,tauros2-cache";
0030 marvell,tauros2-cache-features = <0x3>;
0031 };
0032
0033 axi@d4200000 { /* AXI */
0034 compatible = "mrvl,axi-bus", "simple-bus";
0035 #address-cells = <1>;
0036 #size-cells = <1>;
0037 reg = <0xd4200000 0x00200000>;
0038 ranges;
0039
0040 intc: interrupt-controller@d4282000 {
0041 compatible = "mrvl,mmp-intc";
0042 interrupt-controller;
0043 #interrupt-cells = <1>;
0044 reg = <0xd4282000 0x1000>;
0045 mrvl,intc-nr-irqs = <64>;
0046 };
0047
0048 };
0049
0050 apb@d4000000 { /* APB */
0051 compatible = "mrvl,apb-bus", "simple-bus";
0052 #address-cells = <1>;
0053 #size-cells = <1>;
0054 reg = <0xd4000000 0x00200000>;
0055 ranges;
0056
0057 timer0: timer@d4014000 {
0058 compatible = "mrvl,mmp-timer";
0059 reg = <0xd4014000 0x100>;
0060 interrupts = <13>;
0061 };
0062
0063 timer1: timer@d4016000 {
0064 compatible = "mrvl,mmp-timer";
0065 reg = <0xd4016000 0x100>;
0066 interrupts = <29>;
0067 status = "disabled";
0068 };
0069
0070 uart1: serial@d4017000 {
0071 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
0072 reg = <0xd4017000 0x1000>;
0073 reg-shift = <2>;
0074 interrupts = <27>;
0075 clocks = <&soc_clocks PXA910_CLK_UART0>;
0076 resets = <&soc_clocks PXA910_CLK_UART0>;
0077 status = "disabled";
0078 };
0079
0080 uart2: serial@d4018000 {
0081 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
0082 reg = <0xd4018000 0x1000>;
0083 reg-shift = <2>;
0084 interrupts = <28>;
0085 clocks = <&soc_clocks PXA910_CLK_UART1>;
0086 resets = <&soc_clocks PXA910_CLK_UART1>;
0087 status = "disabled";
0088 };
0089
0090 uart3: serial@d4036000 {
0091 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
0092 reg = <0xd4036000 0x1000>;
0093 reg-shift = <2>;
0094 interrupts = <59>;
0095 clocks = <&soc_clocks PXA910_CLK_UART2>;
0096 resets = <&soc_clocks PXA910_CLK_UART2>;
0097 status = "disabled";
0098 };
0099
0100 gpio@d4019000 {
0101 compatible = "marvell,mmp-gpio";
0102 #address-cells = <1>;
0103 #size-cells = <1>;
0104 reg = <0xd4019000 0x1000>;
0105 gpio-controller;
0106 #gpio-cells = <2>;
0107 interrupts = <49>;
0108 interrupt-names = "gpio_mux";
0109 clocks = <&soc_clocks PXA910_CLK_GPIO>;
0110 resets = <&soc_clocks PXA910_CLK_GPIO>;
0111 interrupt-controller;
0112 #interrupt-cells = <2>;
0113 ranges;
0114
0115 gcb0: gpio@d4019000 {
0116 reg = <0xd4019000 0x4>;
0117 };
0118
0119 gcb1: gpio@d4019004 {
0120 reg = <0xd4019004 0x4>;
0121 };
0122
0123 gcb2: gpio@d4019008 {
0124 reg = <0xd4019008 0x4>;
0125 };
0126
0127 gcb3: gpio@d4019100 {
0128 reg = <0xd4019100 0x4>;
0129 };
0130 };
0131
0132 twsi1: i2c@d4011000 {
0133 compatible = "mrvl,mmp-twsi";
0134 #address-cells = <1>;
0135 #size-cells = <0>;
0136 reg = <0xd4011000 0x1000>;
0137 interrupts = <7>;
0138 clocks = <&soc_clocks PXA910_CLK_TWSI0>;
0139 resets = <&soc_clocks PXA910_CLK_TWSI0>;
0140 mrvl,i2c-fast-mode;
0141 status = "disabled";
0142 };
0143
0144 twsi2: i2c@d4037000 {
0145 compatible = "mrvl,mmp-twsi";
0146 #address-cells = <1>;
0147 #size-cells = <0>;
0148 reg = <0xd4037000 0x1000>;
0149 interrupts = <54>;
0150 clocks = <&soc_clocks PXA910_CLK_TWSI1>;
0151 resets = <&soc_clocks PXA910_CLK_TWSI1>;
0152 status = "disabled";
0153 };
0154
0155 rtc: rtc@d4010000 {
0156 compatible = "mrvl,mmp-rtc";
0157 reg = <0xd4010000 0x1000>;
0158 interrupts = <5>, <6>;
0159 interrupt-names = "rtc 1Hz", "rtc alarm";
0160 clocks = <&soc_clocks PXA910_CLK_RTC>;
0161 resets = <&soc_clocks PXA910_CLK_RTC>;
0162 status = "disabled";
0163 };
0164 };
0165
0166 soc_clocks: clocks{
0167 compatible = "marvell,pxa910-clock";
0168 reg = <0xd4050000 0x1000>,
0169 <0xd4282800 0x400>,
0170 <0xd4015000 0x1000>,
0171 <0xd403b000 0x1000>;
0172 reg-names = "mpmu", "apmu", "apbc", "apbcp";
0173 #clock-cells = <1>;
0174 #reset-cells = <1>;
0175 };
0176 };
0177 };
