0001 // SPDX-License-Identifier: GPL-2.0
0002 /* The pxa3xx skeleton simply augments the 2xx version */
0003 #include "pxa2xx.dtsi"
0004
0005 #define MFP_PIN_PXA300(gpio) \
0006 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
0007 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
0008 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
0009 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
0010 0)
0011 #define MFP_PIN_PXA300_2(gpio) \
0012 ((gpio <= 1) ? (0x674 + 4 * gpio) : \
0013 (gpio <= 6) ? (0x2dc + 4 * gpio) : \
0014 0)
0015
0016 #define MFP_PIN_PXA310(gpio) \
0017 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
0018 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
0019 (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \
0020 (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \
0021 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
0022 (gpio <= 262) ? 0 : \
0023 (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \
0024 0)
0025 #define MFP_PIN_PXA310_2(gpio) \
0026 ((gpio <= 1) ? (0x674 + 4 * gpio) : \
0027 (gpio <= 6) ? (0x2dc + 4 * gpio) : \
0028 (gpio <= 10) ? (0x52c + 4 * gpio) : \
0029 0)
0030
0031 #define MFP_PIN_PXA320(gpio) \
0032 ((gpio <= 4) ? (0x0124 + 4 * gpio) : \
0033 (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \
0034 (gpio <= 10) ? (0x0458 + 4 * (gpio - 10)) : \
0035 (gpio <= 26) ? (0x02a0 + 4 * (gpio - 11)) : \
0036 (gpio <= 48) ? (0x0400 + 4 * (gpio - 27)) : \
0037 (gpio <= 62) ? (0x045c + 4 * (gpio - 49)) : \
0038 (gpio <= 73) ? (0x04b4 + 4 * (gpio - 63)) : \
0039 (gpio <= 98) ? (0x04f0 + 4 * (gpio - 74)) : \
0040 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
0041 0)
0042 #define MFP_PIN_PXA320_2(gpio) \
0043 ((gpio <= 3) ? (0x674 + 4 * gpio) : \
0044 (gpio <= 5) ? (0x284 + 4 * gpio) : \
0045 0)
0046
0047 /*
0048 * MFP Alternate functions for pins having a gpio.
0049 * Example of use: pinctrl-single,pins = < MFP_PIN_PXA310(21) MFP_AF1 >
0050 */
0051 #define MFP_AF0 (0 << 0)
0052 #define MFP_AF1 (1 << 0)
0053 #define MFP_AF2 (2 << 0)
0054 #define MFP_AF3 (3 << 0)
0055 #define MFP_AF4 (4 << 0)
0056 #define MFP_AF5 (5 << 0)
0057 #define MFP_AF6 (6 << 0)
0058
0059 /*
0060 * MFP drive strength functions for pins.
0061 * Example of use: pinctrl-single,drive-strength = MFP_DS03X;
0062 */
0063 #define MFP_DSMSK (0x7 << 10)
0064 #define MFP_DS01X < (0x0 << 10) MFP_DSMSK >
0065 #define MFP_DS02X < (0x1 << 10) MFP_DSMSK >
0066 #define MFP_DS03X < (0x2 << 10) MFP_DSMSK >
0067 #define MFP_DS04X < (0x3 << 10) MFP_DSMSK >
0068 #define MFP_DS06X < (0x4 << 10) MFP_DSMSK >
0069 #define MFP_DS08X < (0x5 << 10) MFP_DSMSK >
0070 #define MFP_DS10X < (0x6 << 10) MFP_DSMSK >
0071 #define MFP_DS13X < (0x7 << 10) MFP_DSMSK >
0072
0073 /*
0074 * MFP bias pull mode for pins.
0075 * Example of use: pinctrl-single,bias-pullup = MPF_PULL_UP;
0076 */
0077 #define MPF_PULL_MSK (0x7 << 13)
0078 #define MPF_PULL_DOWN < (0x5 << 13) (0x5 << 13) 0 MPF_PULL_MSK >
0079 #define MPF_PULL_UP < (0x6 << 13) (0x6 << 13) 0 MPF_PULL_MSK >
0080
0081 /*
0082 * MFP low power mode for pins.
0083 * Example of use:
0084 * pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW|MFP_LPM_EDGE_FALL);
0085 *
0086 * Table that determines the low power modes outputs, with actual settings
0087 * used in parentheses for don't-care values. Except for the float output,
0088 * the configured driven and pulled levels match, so if there is a need for
0089 * non-LPM pulled output, the same configuration could probably be used.
0090 *
0091 * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
0092 * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15)
0093 *
0094 * Input 0 X(0) X(0) X(0) 0
0095 * Drive 0 0 0 0 X(1) 0
0096 * Drive 1 0 1 X(1) 0 0
0097 * Pull hi (1) 1 X(1) 1 0 0
0098 * Pull lo (0) 1 X(0) 0 1 0
0099 * Z (float) 1 X(0) 0 0 0
0100 */
0101 #define MFP_LPM(x) < (x) MFP_LPM_MSK >
0102
0103 #define MFP_LPM_MSK 0xe1f0
0104 #define MFP_LPM_INPUT 0x0000
0105 #define MFP_LPM_DRIVE_LOW 0x2000
0106 #define MFP_LPM_DRIVE_HIGH 0x4100
0107 #define MFP_LPM_PULL_LOW 0x2080
0108 #define MFP_LPM_PULL_HIGH 0x4180
0109 #define MFP_LPM_FLOAT 0x0080
0110
0111 #define MFP_LPM_EDGE_NONE 0x0000
0112 #define MFP_LPM_EDGE_RISE 0x0010
0113 #define MFP_LPM_EDGE_FALL 0x0020
0114 #define MFP_LPM_EDGE_BOTH 0x0030
0115
0116 / {
0117 model = "Marvell PXA3xx familiy SoC";
0118 compatible = "marvell,pxa3xx";
0119
0120 pxabus {
0121 pdma: dma-controller@40000000 {
0122 compatible = "marvell,pdma-1.0";
0123 reg = <0x40000000 0x10000>;
0124 interrupts = <25>;
0125 #dma-cells = <2>;
0126 /* For backwards compatibility: */
0127 #dma-channels = <32>;
0128 dma-channels = <32>;
0129 #dma-requests = <100>;
0130 dma-requests = <100>;
0131 status = "okay";
0132 };
0133
0134 pwri2c: i2c@40f500c0 {
0135 compatible = "mrvl,pwri2c";
0136 reg = <0x40f500c0 0x30>;
0137 interrupts = <6>;
0138 clocks = <&clks CLK_PWRI2C>;
0139 #address-cells = <0x1>;
0140 #size-cells = <0>;
0141 status = "disabled";
0142 };
0143
0144 nand_controller: nand-controller@43100000 {
0145 compatible = "marvell,pxa3xx-nand-controller";
0146 reg = <0x43100000 90>;
0147 interrupts = <45>;
0148 clocks = <&clks CLK_NAND>;
0149 clock-names = "core";
0150 dmas = <&pdma 97 3>;
0151 dma-names = "data";
0152 #address-cells = <1>;
0153 #size-cells = <0>;
0154 status = "disabled";
0155 };
0156
0157 pxairq: interrupt-controller@40d00000 {
0158 marvell,intc-priority;
0159 marvell,intc-nr-irqs = <56>;
0160 };
0161
0162 pinctrl: pinctrl@40e10000 {
0163 compatible = "pinconf-single";
0164 reg = <0x40e10000 0xffff>;
0165 #pinctrl-cells = <1>;
0166 pinctrl-single,register-width = <32>;
0167 pinctrl-single,function-mask = <0x7>;
0168 };
0169
0170 gpio: gpio@40e00000 {
0171 compatible = "intel,pxa3xx-gpio";
0172 reg = <0x40e00000 0x10000>;
0173 clocks = <&clks CLK_GPIO>;
0174 gpio-ranges = <&pinctrl 0 0 128>;
0175 interrupt-names = "gpio0", "gpio1", "gpio_mux";
0176 interrupts = <8>, <9>, <10>;
0177 gpio-controller;
0178 #gpio-cells = <0x2>;
0179 interrupt-controller;
0180 #interrupt-cells = <0x2>;
0181 };
0182
0183 mmc0: mmc@41100000 {
0184 compatible = "marvell,pxa-mmc";
0185 reg = <0x41100000 0x1000>;
0186 interrupts = <23>;
0187 clocks = <&clks CLK_MMC1>;
0188 dmas = <&pdma 21 3
0189 &pdma 22 3>;
0190 dma-names = "rx", "tx";
0191 status = "disabled";
0192 };
0193
0194 mmc1: mmc@42000000 {
0195 compatible = "marvell,pxa-mmc";
0196 reg = <0x42000000 0x1000>;
0197 interrupts = <41>;
0198 clocks = <&clks CLK_MMC2>;
0199 dmas = <&pdma 93 3
0200 &pdma 94 3>;
0201 dma-names = "rx", "tx";
0202 status = "disabled";
0203 };
0204
0205 mmc2: mmc@42500000 {
0206 compatible = "marvell,pxa-mmc";
0207 reg = <0x42500000 0x1000>;
0208 interrupts = <55>;
0209 clocks = <&clks CLK_MMC3>;
0210 dmas = <&pdma 46 3
0211 &pdma 47 3>;
0212 dma-names = "rx", "tx";
0213 status = "disabled";
0214 };
0215
0216 usb0: usb@4c000000 {
0217 compatible = "marvell,pxa-ohci";
0218 reg = <0x4c000000 0x10000>;
0219 interrupts = <3>;
0220 clocks = <&clks CLK_USBH>;
0221 status = "disabled";
0222 };
0223
0224 pwm0: pwm@40b00000 {
0225 compatible = "marvell,pxa270-pwm";
0226 reg = <0x40b00000 0x10>;
0227 #pwm-cells = <1>;
0228 clocks = <&clks CLK_PWM0>;
0229 status = "disabled";
0230 };
0231
0232 pwm1: pwm@40b00010 {
0233 compatible = "marvell,pxa270-pwm";
0234 reg = <0x40b00010 0x10>;
0235 #pwm-cells = <1>;
0236 clocks = <&clks CLK_PWM1>;
0237 status = "disabled";
0238 };
0239
0240 pwm2: pwm@40c00000 {
0241 compatible = "marvell,pxa270-pwm";
0242 reg = <0x40c00000 0x10>;
0243 #pwm-cells = <1>;
0244 clocks = <&clks CLK_PWM0>;
0245 status = "disabled";
0246 };
0247
0248 pwm3: pwm@40c00010 {
0249 compatible = "marvell,pxa270-pwm";
0250 reg = <0x40c00010 0x10>;
0251 #pwm-cells = <1>;
0252 clocks = <&clks CLK_PWM1>;
0253 status = "disabled";
0254 };
0255
0256 ssp1: ssp@41000000 {
0257 compatible = "mrvl,pxa3xx-ssp";
0258 reg = <0x41000000 0x40>;
0259 interrupts = <24>;
0260 clocks = <&clks CLK_SSP1>;
0261 status = "disabled";
0262 };
0263
0264 ssp2: ssp@41700000 {
0265 compatible = "mrvl,pxa3xx-ssp";
0266 reg = <0x41700000 0x40>;
0267 interrupts = <16>;
0268 clocks = <&clks CLK_SSP2>;
0269 status = "disabled";
0270 };
0271
0272 ssp3: ssp@41900000 {
0273 compatible = "mrvl,pxa3xx-ssp";
0274 reg = <0x41900000 0x40>;
0275 interrupts = <0>;
0276 clocks = <&clks CLK_SSP3>;
0277 status = "disabled";
0278 };
0279
0280 ssp4: ssp@41a00000 {
0281 compatible = "mrvl,pxa3xx-ssp";
0282 reg = <0x41a00000 0x40>;
0283 interrupts = <13>;
0284 clocks = <&clks CLK_SSP4>;
0285 status = "disabled";
0286 };
0287
0288 timer@40a00000 {
0289 compatible = "marvell,pxa-timer";
0290 reg = <0x40a00000 0x20>;
0291 interrupts = <26>;
0292 clocks = <&clks CLK_OSTIMER>;
0293 status = "okay";
0294 };
0295
0296 gcu: display-controller@54000000 {
0297 compatible = "marvell,pxa300-gcu";
0298 reg = <0x54000000 0x1000>;
0299 interrupts = <39>;
0300 clocks = <&clks CLK_PXA300_GCU>;
0301 status = "disabled";
0302 };
0303 };
0304
0305 clocks {
0306 /*
0307 * The muxing of external clocks/internal dividers for osc* clock
0308 * sources has been hidden under the carpet by now.
0309 */
0310 #address-cells = <1>;
0311 #size-cells = <1>;
0312 ranges;
0313
0314 clks: clocks {
0315 compatible = "marvell,pxa300-clocks";
0316 #clock-cells = <1>;
0317 status = "okay";
0318 };
0319 };
0320 };
