0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2012 Marvell Technology Group Ltd.
0004 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
0005 */
0006
0007 #include <dt-bindings/clock/marvell,pxa168.h>
0008
0009 / {
0010 #address-cells = <1>;
0011 #size-cells = <1>;
0012
0013 aliases {
0014 serial0 = &uart1;
0015 serial1 = &uart2;
0016 serial2 = &uart3;
0017 i2c0 = &twsi1;
0018 i2c1 = &twsi2;
0019 };
0020
0021 soc {
0022 #address-cells = <1>;
0023 #size-cells = <1>;
0024 compatible = "simple-bus";
0025 interrupt-parent = <&intc>;
0026 ranges;
0027
0028 axi@d4200000 { /* AXI */
0029 compatible = "mrvl,axi-bus", "simple-bus";
0030 #address-cells = <1>;
0031 #size-cells = <1>;
0032 reg = <0xd4200000 0x00200000>;
0033 ranges;
0034
0035 intc: interrupt-controller@d4282000 {
0036 compatible = "mrvl,mmp-intc";
0037 interrupt-controller;
0038 #interrupt-cells = <1>;
0039 reg = <0xd4282000 0x1000>;
0040 mrvl,intc-nr-irqs = <64>;
0041 };
0042
0043 };
0044
0045 apb@d4000000 { /* APB */
0046 compatible = "mrvl,apb-bus", "simple-bus";
0047 #address-cells = <1>;
0048 #size-cells = <1>;
0049 reg = <0xd4000000 0x00200000>;
0050 ranges;
0051
0052 timer0: timer@d4014000 {
0053 compatible = "mrvl,mmp-timer";
0054 reg = <0xd4014000 0x100>;
0055 interrupts = <13>;
0056 };
0057
0058 uart1: serial@d4017000 {
0059 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
0060 reg = <0xd4017000 0x1000>;
0061 reg-shift = <2>;
0062 interrupts = <27>;
0063 clocks = <&soc_clocks PXA168_CLK_UART0>;
0064 resets = <&soc_clocks PXA168_CLK_UART0>;
0065 status = "disabled";
0066 };
0067
0068 uart2: serial@d4018000 {
0069 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
0070 reg = <0xd4018000 0x1000>;
0071 reg-shift = <2>;
0072 interrupts = <28>;
0073 clocks = <&soc_clocks PXA168_CLK_UART1>;
0074 resets = <&soc_clocks PXA168_CLK_UART1>;
0075 status = "disabled";
0076 };
0077
0078 uart3: serial@d4026000 {
0079 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
0080 reg = <0xd4026000 0x1000>;
0081 reg-shift = <2>;
0082 interrupts = <29>;
0083 clocks = <&soc_clocks PXA168_CLK_UART2>;
0084 resets = <&soc_clocks PXA168_CLK_UART2>;
0085 status = "disabled";
0086 };
0087
0088 gpio@d4019000 {
0089 compatible = "marvell,mmp-gpio";
0090 #address-cells = <1>;
0091 #size-cells = <1>;
0092 reg = <0xd4019000 0x1000>;
0093 gpio-controller;
0094 #gpio-cells = <2>;
0095 interrupts = <49>;
0096 clocks = <&soc_clocks PXA168_CLK_GPIO>;
0097 resets = <&soc_clocks PXA168_CLK_GPIO>;
0098 interrupt-names = "gpio_mux";
0099 interrupt-controller;
0100 #interrupt-cells = <2>;
0101 ranges;
0102
0103 gcb0: gpio@d4019000 {
0104 reg = <0xd4019000 0x4>;
0105 };
0106
0107 gcb1: gpio@d4019004 {
0108 reg = <0xd4019004 0x4>;
0109 };
0110
0111 gcb2: gpio@d4019008 {
0112 reg = <0xd4019008 0x4>;
0113 };
0114
0115 gcb3: gpio@d4019100 {
0116 reg = <0xd4019100 0x4>;
0117 };
0118 };
0119
0120 twsi1: i2c@d4011000 {
0121 compatible = "mrvl,mmp-twsi";
0122 #address-cells = <1>;
0123 #size-cells = <0>;
0124 reg = <0xd4011000 0x1000>;
0125 interrupts = <7>;
0126 clocks = <&soc_clocks PXA168_CLK_TWSI0>;
0127 resets = <&soc_clocks PXA168_CLK_TWSI0>;
0128 mrvl,i2c-fast-mode;
0129 status = "disabled";
0130 };
0131
0132 twsi2: i2c@d4025000 {
0133 compatible = "mrvl,mmp-twsi";
0134 #address-cells = <1>;
0135 #size-cells = <0>;
0136 reg = <0xd4025000 0x1000>;
0137 interrupts = <58>;
0138 clocks = <&soc_clocks PXA168_CLK_TWSI1>;
0139 resets = <&soc_clocks PXA168_CLK_TWSI1>;
0140 status = "disabled";
0141 };
0142
0143 rtc: rtc@d4010000 {
0144 compatible = "mrvl,mmp-rtc";
0145 reg = <0xd4010000 0x1000>;
0146 interrupts = <5>, <6>;
0147 interrupt-names = "rtc 1Hz", "rtc alarm";
0148 clocks = <&soc_clocks PXA168_CLK_RTC>;
0149 resets = <&soc_clocks PXA168_CLK_RTC>;
0150 status = "disabled";
0151 };
0152 };
0153
0154 soc_clocks: clocks{
0155 compatible = "marvell,pxa168-clock";
0156 reg = <0xd4050000 0x1000>,
0157 <0xd4282800 0x400>,
0158 <0xd4015000 0x1000>;
0159 reg-names = "mpmu", "apmu", "apbc";
0160 #clock-cells = <1>;
0161 #reset-cells = <1>;
0162 };
0163 };
0164 };
