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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC
0004 *
0005 * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
0006 */
0007
0008 #include <dt-bindings/interrupt-controller/arm-gic.h>
0009 #include <dt-bindings/clock/oxsemi,ox820.h>
0010 #include <dt-bindings/reset/oxsemi,ox820.h>
0011
0012 / {
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015 compatible = "oxsemi,ox820";
0016
0017 cpus {
0018 #address-cells = <1>;
0019 #size-cells = <0>;
0020 enable-method = "oxsemi,ox820-smp";
0021
0022 cpu@0 {
0023 device_type = "cpu";
0024 compatible = "arm,arm11mpcore";
0025 clocks = <&armclk>;
0026 reg = <0>;
0027 };
0028
0029 cpu@1 {
0030 device_type = "cpu";
0031 compatible = "arm,arm11mpcore";
0032 clocks = <&armclk>;
0033 reg = <1>;
0034 };
0035 };
0036
0037 memory {
0038 device_type = "memory";
0039 /* Max 512MB @ 0x60000000 */
0040 reg = <0x60000000 0x20000000>;
0041 };
0042
0043 clocks {
0044 osc: oscillator {
0045 compatible = "fixed-clock";
0046 #clock-cells = <0>;
0047 clock-frequency = <25000000>;
0048 };
0049
0050 gmacclk: gmacclk {
0051 compatible = "fixed-clock";
0052 #clock-cells = <0>;
0053 clock-frequency = <125000000>;
0054 };
0055
0056 sysclk: sysclk {
0057 compatible = "fixed-factor-clock";
0058 #clock-cells = <0>;
0059 clock-div = <4>;
0060 clock-mult = <1>;
0061 clocks = <&osc>;
0062 };
0063
0064 plla: plla {
0065 compatible = "fixed-clock";
0066 #clock-cells = <0>;
0067 clock-frequency = <850000000>;
0068 };
0069
0070 armclk: armclk {
0071 compatible = "fixed-factor-clock";
0072 #clock-cells = <0>;
0073 clock-div = <2>;
0074 clock-mult = <1>;
0075 clocks = <&plla>;
0076 };
0077 };
0078
0079 soc {
0080 #address-cells = <1>;
0081 #size-cells = <1>;
0082 compatible = "simple-bus";
0083 ranges;
0084 interrupt-parent = <&gic>;
0085
0086 nandc: nand-controller@41000000 {
0087 compatible = "oxsemi,ox820-nand";
0088 reg = <0x41000000 0x100000>;
0089 clocks = <&stdclk CLK_820_NAND>;
0090 resets = <&reset RESET_NAND>;
0091 #address-cells = <1>;
0092 #size-cells = <0>;
0093 status = "disabled";
0094 };
0095
0096 etha: ethernet@40400000 {
0097 compatible = "oxsemi,ox820-dwmac", "snps,dwmac";
0098 reg = <0x40400000 0x2000>;
0099 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0100 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0101 interrupt-names = "macirq", "eth_wake_irq";
0102 mac-address = [000000000000]; /* Filled in by U-Boot */
0103 phy-mode = "rgmii";
0104
0105 clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>;
0106 clock-names = "gmac", "stmmaceth";
0107 resets = <&reset RESET_MAC>;
0108
0109 /* Regmap for sys registers */
0110 oxsemi,sys-ctrl = <&sys>;
0111
0112 status = "disabled";
0113 };
0114
0115 apb-bridge@44000000 {
0116 #address-cells = <1>;
0117 #size-cells = <1>;
0118 compatible = "simple-bus";
0119 ranges = <0 0x44000000 0x1000000>;
0120
0121 pinctrl: pinctrl {
0122 compatible = "oxsemi,ox820-pinctrl";
0123
0124 /* Regmap for sys registers */
0125 oxsemi,sys-ctrl = <&sys>;
0126
0127 pinctrl_uart0: uart0 {
0128 uart0 {
0129 pins = "gpio30", "gpio31";
0130 function = "fct5";
0131 };
0132 };
0133
0134 pinctrl_uart0_modem: uart0_modem {
0135 uart0_modem_a {
0136 pins = "gpio24", "gpio24", "gpio26", "gpio27";
0137 function = "fct4";
0138 };
0139 uart0_modem_b {
0140 pins = "gpio28", "gpio29";
0141 function = "fct5";
0142 };
0143 };
0144
0145 pinctrl_uart1: uart1 {
0146 uart1 {
0147 pins = "gpio7", "gpio8";
0148 function = "fct4";
0149 };
0150 };
0151
0152 pinctrl_uart1_modem: uart1_modem {
0153 uart1_modem {
0154 pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43";
0155 function = "fct4";
0156 };
0157 };
0158
0159 pinctrl_etha_mdio: etha_mdio {
0160 etha_mdio {
0161 pins = "gpio3", "gpio4";
0162 function = "fct1";
0163 };
0164 };
0165
0166 pinctrl_nand: nand {
0167 nand {
0168 pins = "gpio12", "gpio13", "gpio14", "gpio15",
0169 "gpio16", "gpio17", "gpio18", "gpio19",
0170 "gpio20", "gpio21", "gpio22", "gpio23",
0171 "gpio24";
0172 function = "fct1";
0173 };
0174 };
0175 };
0176
0177 gpio0: gpio@0 {
0178 compatible = "oxsemi,ox820-gpio";
0179 reg = <0x000000 0x100000>;
0180 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0181 #gpio-cells = <2>;
0182 gpio-controller;
0183 interrupt-controller;
0184 #interrupt-cells = <2>;
0185 ngpios = <32>;
0186 oxsemi,gpio-bank = <0>;
0187 gpio-ranges = <&pinctrl 0 0 32>;
0188 };
0189
0190 gpio1: gpio@100000 {
0191 compatible = "oxsemi,ox820-gpio";
0192 reg = <0x100000 0x100000>;
0193 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0194 #gpio-cells = <2>;
0195 gpio-controller;
0196 interrupt-controller;
0197 #interrupt-cells = <2>;
0198 ngpios = <18>;
0199 oxsemi,gpio-bank = <1>;
0200 gpio-ranges = <&pinctrl 0 32 18>;
0201 };
0202
0203 uart0: serial@200000 {
0204 compatible = "ns16550a";
0205 reg = <0x200000 0x100000>;
0206 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0207 reg-shift = <0>;
0208 fifo-size = <16>;
0209 reg-io-width = <1>;
0210 current-speed = <115200>;
0211 no-loopback-test;
0212 status = "disabled";
0213 clocks = <&sysclk>;
0214 resets = <&reset RESET_UART1>;
0215 };
0216
0217 uart1: serial@300000 {
0218 compatible = "ns16550a";
0219 reg = <0x200000 0x100000>;
0220 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0221 reg-shift = <0>;
0222 fifo-size = <16>;
0223 reg-io-width = <1>;
0224 current-speed = <115200>;
0225 no-loopback-test;
0226 status = "disabled";
0227 clocks = <&sysclk>;
0228 resets = <&reset RESET_UART2>;
0229 };
0230
0231 rps@400000 {
0232 #address-cells = <1>;
0233 #size-cells = <1>;
0234 compatible = "simple-bus";
0235 ranges = <0 0x400000 0x100000>;
0236
0237 intc: interrupt-controller@0 {
0238 compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq";
0239 interrupt-controller;
0240 reg = <0 0x200>;
0241 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0242 #interrupt-cells = <1>;
0243 valid-mask = <0xffffffff>;
0244 clear-mask = <0xffffffff>;
0245 };
0246
0247 timer0: timer@200 {
0248 compatible = "oxsemi,ox820-rps-timer";
0249 reg = <0x200 0x40>;
0250 clocks = <&sysclk>;
0251 interrupt-parent = <&intc>;
0252 interrupts = <4>;
0253 };
0254 };
0255
0256 sys: sys-ctrl@e00000 {
0257 compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
0258 reg = <0xe00000 0x200000>;
0259
0260 reset: reset-controller {
0261 compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset";
0262 #reset-cells = <1>;
0263 };
0264
0265 stdclk: stdclk {
0266 compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk";
0267 #clock-cells = <1>;
0268 };
0269 };
0270 };
0271
0272 apb-bridge@47000000 {
0273 #address-cells = <1>;
0274 #size-cells = <1>;
0275 compatible = "simple-bus";
0276 ranges = <0 0x47000000 0x1000000>;
0277
0278 scu: scu@0 {
0279 compatible = "arm,arm11mp-scu";
0280 reg = <0x0 0x100>;
0281 };
0282
0283 local-timer@600 {
0284 compatible = "arm,arm11mp-twd-timer";
0285 reg = <0x600 0x20>;
0286 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;
0287 clocks = <&armclk>;
0288 };
0289
0290 gic: interrupt-controller@1000 {
0291 compatible = "arm,arm11mp-gic";
0292 interrupt-controller;
0293 #interrupt-cells = <3>;
0294 reg = <0x1000 0x1000>,
0295 <0x100 0x500>;
0296 };
0297 };
0298 };
0299 };
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