OSCL-LXR |
|
|
|
|||
0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC
0004 *
0005 * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
0006 */
0007
0008 #include <dt-bindings/clock/oxsemi,ox810se.h>
0009 #include <dt-bindings/reset/oxsemi,ox810se.h>
0010
0011 / {
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014 compatible = "oxsemi,ox810se";
0015
0016 cpus {
0017 #address-cells = <0>;
0018 #size-cells = <0>;
0019
0020 cpu {
0021 device_type = "cpu";
0022 compatible = "arm,arm926ej-s";
0023 clocks = <&armclk>;
0024 };
0025 };
0026
0027 memory {
0028 device_type = "memory";
0029 /* Max 256MB @ 0x48000000 */
0030 reg = <0x48000000 0x10000000>;
0031 };
0032
0033 clocks {
0034 osc: oscillator {
0035 compatible = "fixed-clock";
0036 #clock-cells = <0>;
0037 clock-frequency = <25000000>;
0038 };
0039
0040 gmacclk: gmacclk {
0041 compatible = "fixed-clock";
0042 #clock-cells = <0>;
0043 clock-frequency = <125000000>;
0044 };
0045
0046 rpsclk: rpsclk {
0047 compatible = "fixed-factor-clock";
0048 #clock-cells = <0>;
0049 clock-div = <1>;
0050 clock-mult = <1>;
0051 clocks = <&osc>;
0052 };
0053
0054 pll400: pll400 {
0055 compatible = "fixed-clock";
0056 #clock-cells = <0>;
0057 clock-frequency = <733333333>;
0058 };
0059
0060 sysclk: sysclk {
0061 compatible = "fixed-factor-clock";
0062 #clock-cells = <0>;
0063 clock-div = <4>;
0064 clock-mult = <1>;
0065 clocks = <&pll400>;
0066 };
0067
0068 armclk: armclk {
0069 compatible = "fixed-factor-clock";
0070 #clock-cells = <0>;
0071 clock-div = <2>;
0072 clock-mult = <1>;
0073 clocks = <&pll400>;
0074 };
0075 };
0076
0077 soc {
0078 #address-cells = <1>;
0079 #size-cells = <1>;
0080 compatible = "simple-bus";
0081 ranges;
0082 interrupt-parent = <&intc>;
0083
0084 etha: ethernet@40400000 {
0085 compatible = "oxsemi,ox810se-dwmac", "snps,dwmac";
0086 reg = <0x40400000 0x2000>;
0087 interrupts = <8>;
0088 interrupt-names = "macirq";
0089 mac-address = [000000000000]; /* Filled in by U-Boot */
0090 phy-mode = "rgmii";
0091
0092 clocks = <&stdclk 6>, <&gmacclk>;
0093 clock-names = "gmac", "stmmaceth";
0094 resets = <&reset 6>;
0095
0096 /* Regmap for sys registers */
0097 oxsemi,sys-ctrl = <&sys>;
0098
0099 status = "disabled";
0100 };
0101
0102 apb-bridge@44000000 {
0103 #address-cells = <1>;
0104 #size-cells = <1>;
0105 compatible = "simple-bus";
0106 ranges = <0 0x44000000 0x1000000>;
0107
0108 pinctrl: pinctrl {
0109 compatible = "oxsemi,ox810se-pinctrl";
0110
0111 /* Regmap for sys registers */
0112 oxsemi,sys-ctrl = <&sys>;
0113
0114 pinctrl_uart0: uart0 {
0115 uart0a {
0116 pins = "gpio31";
0117 function = "fct3";
0118 };
0119 uart0b {
0120 pins = "gpio32";
0121 function = "fct3";
0122 };
0123 };
0124
0125 pinctrl_uart0_modem: uart0_modem {
0126 uart0c {
0127 pins = "gpio27";
0128 function = "fct3";
0129 };
0130 uart0d {
0131 pins = "gpio28";
0132 function = "fct3";
0133 };
0134 uart0e {
0135 pins = "gpio29";
0136 function = "fct3";
0137 };
0138 uart0f {
0139 pins = "gpio30";
0140 function = "fct3";
0141 };
0142 uart0g {
0143 pins = "gpio33";
0144 function = "fct3";
0145 };
0146 uart0h {
0147 pins = "gpio34";
0148 function = "fct3";
0149 };
0150 };
0151
0152 pinctrl_uart1: uart1 {
0153 uart1a {
0154 pins = "gpio20";
0155 function = "fct3";
0156 };
0157 uart1b {
0158 pins = "gpio22";
0159 function = "fct3";
0160 };
0161 };
0162
0163 pinctrl_uart1_modem: uart1_modem {
0164 uart1c {
0165 pins = "gpio8";
0166 function = "fct3";
0167 };
0168 uart1d {
0169 pins = "gpio9";
0170 function = "fct3";
0171 };
0172 uart1e {
0173 pins = "gpio23";
0174 function = "fct3";
0175 };
0176 uart1f {
0177 pins = "gpio24";
0178 function = "fct3";
0179 };
0180 uart1g {
0181 pins = "gpio25";
0182 function = "fct3";
0183 };
0184 uart1h {
0185 pins = "gpio26";
0186 function = "fct3";
0187 };
0188 };
0189
0190 pinctrl_uart2: uart2 {
0191 uart2a {
0192 pins = "gpio6";
0193 function = "fct3";
0194 };
0195 uart2b {
0196 pins = "gpio7";
0197 function = "fct3";
0198 };
0199 };
0200
0201 pinctrl_uart2_modem: uart2_modem {
0202 uart2c {
0203 pins = "gpio0";
0204 function = "fct3";
0205 };
0206 uart2d {
0207 pins = "gpio1";
0208 function = "fct3";
0209 };
0210 uart2e {
0211 pins = "gpio2";
0212 function = "fct3";
0213 };
0214 uart2f {
0215 pins = "gpio3";
0216 function = "fct3";
0217 };
0218 uart2g {
0219 pins = "gpio4";
0220 function = "fct3";
0221 };
0222 uart2h {
0223 pins = "gpio5";
0224 function = "fct3";
0225 };
0226 };
0227 };
0228
0229 gpio0: gpio@0 {
0230 compatible = "oxsemi,ox810se-gpio";
0231 reg = <0x000000 0x100000>;
0232 interrupts = <21>;
0233 #gpio-cells = <2>;
0234 gpio-controller;
0235 interrupt-controller;
0236 #interrupt-cells = <2>;
0237 ngpios = <32>;
0238 oxsemi,gpio-bank = <0>;
0239 gpio-ranges = <&pinctrl 0 0 32>;
0240 };
0241
0242 gpio1: gpio@100000 {
0243 compatible = "oxsemi,ox810se-gpio";
0244 reg = <0x100000 0x100000>;
0245 interrupts = <22>;
0246 #gpio-cells = <2>;
0247 gpio-controller;
0248 interrupt-controller;
0249 #interrupt-cells = <2>;
0250 ngpios = <3>;
0251 oxsemi,gpio-bank = <1>;
0252 gpio-ranges = <&pinctrl 0 32 3>;
0253 };
0254
0255 uart0: serial@200000 {
0256 compatible = "ns16550a";
0257 reg = <0x200000 0x100000>;
0258 clocks = <&sysclk>;
0259 interrupts = <23>;
0260 reg-shift = <0>;
0261 fifo-size = <16>;
0262 reg-io-width = <1>;
0263 current-speed = <115200>;
0264 no-loopback-test;
0265 status = "disabled";
0266 resets = <&reset RESET_UART1>;
0267 };
0268
0269 uart1: serial@300000 {
0270 compatible = "ns16550a";
0271 reg = <0x300000 0x100000>;
0272 clocks = <&sysclk>;
0273 interrupts = <24>;
0274 reg-shift = <0>;
0275 fifo-size = <16>;
0276 reg-io-width = <1>;
0277 current-speed = <115200>;
0278 no-loopback-test;
0279 status = "disabled";
0280 resets = <&reset RESET_UART2>;
0281 };
0282
0283 uart2: serial@900000 {
0284 compatible = "ns16550a";
0285 reg = <0x900000 0x100000>;
0286 clocks = <&sysclk>;
0287 interrupts = <29>;
0288 reg-shift = <0>;
0289 fifo-size = <16>;
0290 reg-io-width = <1>;
0291 current-speed = <115200>;
0292 no-loopback-test;
0293 status = "disabled";
0294 resets = <&reset RESET_UART3>;
0295 };
0296
0297 uart3: serial@a00000 {
0298 compatible = "ns16550a";
0299 reg = <0xa00000 0x100000>;
0300 clocks = <&sysclk>;
0301 interrupts = <30>;
0302 reg-shift = <0>;
0303 fifo-size = <16>;
0304 reg-io-width = <1>;
0305 current-speed = <115200>;
0306 no-loopback-test;
0307 status = "disabled";
0308 resets = <&reset RESET_UART4>;
0309 };
0310 };
0311
0312 apb-bridge@45000000 {
0313 #address-cells = <1>;
0314 #size-cells = <1>;
0315 compatible = "simple-bus";
0316 ranges = <0 0x45000000 0x1000000>;
0317
0318 sys: sys-ctrl@0 {
0319 compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
0320 reg = <0x000000 0x100000>;
0321
0322 reset: reset-controller {
0323 compatible = "oxsemi,ox810se-reset";
0324 #reset-cells = <1>;
0325 };
0326
0327 stdclk: stdclk {
0328 compatible = "oxsemi,ox810se-stdclk";
0329 #clock-cells = <1>;
0330 };
0331 };
0332
0333 rps@300000 {
0334 #address-cells = <1>;
0335 #size-cells = <1>;
0336 compatible = "simple-bus";
0337 ranges = <0 0x300000 0x100000>;
0338
0339 intc: interrupt-controller@0 {
0340 compatible = "oxsemi,ox810se-rps-irq";
0341 interrupt-controller;
0342 reg = <0 0x200>;
0343 #interrupt-cells = <1>;
0344 valid-mask = <0xffffffff>;
0345 clear-mask = <0xffffffff>;
0346 };
0347
0348 timer0: timer@200 {
0349 compatible = "oxsemi,ox810se-rps-timer";
0350 reg = <0x200 0x40>;
0351 clocks = <&rpsclk>;
0352 interrupts = <4 5>;
0353 };
0354 };
0355 };
0356 };
0357 };
| [ Source navigation ] | [ Diff markup ] | [ Identifier search ] | [ general search ] |
|
This page was automatically generated by the 2.1.0 LXR engine. The LXR team |
|