0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * Actions Semi S500 SoC
0004 *
0005 * Copyright (c) 2016-2017 Andreas Färber
0006 */
0007
0008 #include <dt-bindings/clock/actions,s500-cmu.h>
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/power/owl-s500-powergate.h>
0012 #include <dt-bindings/reset/actions,s500-reset.h>
0013
0014 / {
0015 compatible = "actions,s500";
0016 interrupt-parent = <&gic>;
0017 #address-cells = <1>;
0018 #size-cells = <1>;
0019
0020 aliases {
0021 };
0022
0023 chosen {
0024 };
0025
0026 cpus {
0027 #address-cells = <1>;
0028 #size-cells = <0>;
0029
0030 cpu0: cpu@0 {
0031 device_type = "cpu";
0032 compatible = "arm,cortex-a9";
0033 reg = <0x0>;
0034 enable-method = "actions,s500-smp";
0035 };
0036
0037 cpu1: cpu@1 {
0038 device_type = "cpu";
0039 compatible = "arm,cortex-a9";
0040 reg = <0x1>;
0041 enable-method = "actions,s500-smp";
0042 };
0043
0044 cpu2: cpu@2 {
0045 device_type = "cpu";
0046 compatible = "arm,cortex-a9";
0047 reg = <0x2>;
0048 enable-method = "actions,s500-smp";
0049 power-domains = <&sps S500_PD_CPU2>;
0050 };
0051
0052 cpu3: cpu@3 {
0053 device_type = "cpu";
0054 compatible = "arm,cortex-a9";
0055 reg = <0x3>;
0056 enable-method = "actions,s500-smp";
0057 power-domains = <&sps S500_PD_CPU3>;
0058 };
0059 };
0060
0061 arm-pmu {
0062 compatible = "arm,cortex-a9-pmu";
0063 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0064 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0065 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0066 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0067 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0068 };
0069
0070 hosc: hosc {
0071 compatible = "fixed-clock";
0072 clock-frequency = <24000000>;
0073 #clock-cells = <0>;
0074 };
0075
0076 losc: losc {
0077 compatible = "fixed-clock";
0078 clock-frequency = <32768>;
0079 #clock-cells = <0>;
0080 };
0081
0082 soc {
0083 compatible = "simple-bus";
0084 #address-cells = <1>;
0085 #size-cells = <1>;
0086 ranges;
0087
0088 scu: scu@b0020000 {
0089 compatible = "arm,cortex-a9-scu";
0090 reg = <0xb0020000 0x100>;
0091 };
0092
0093 global_timer: timer@b0020200 {
0094 compatible = "arm,cortex-a9-global-timer";
0095 reg = <0xb0020200 0x100>;
0096 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
0097 status = "disabled";
0098 };
0099
0100 twd_timer: timer@b0020600 {
0101 compatible = "arm,cortex-a9-twd-timer";
0102 reg = <0xb0020600 0x20>;
0103 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
0104 status = "disabled";
0105 };
0106
0107 twd_wdt: wdt@b0020620 {
0108 compatible = "arm,cortex-a9-twd-wdt";
0109 reg = <0xb0020620 0xe0>;
0110 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
0111 status = "disabled";
0112 };
0113
0114 gic: interrupt-controller@b0021000 {
0115 compatible = "arm,cortex-a9-gic";
0116 reg = <0xb0021000 0x1000>,
0117 <0xb0020100 0x0100>;
0118 interrupt-controller;
0119 #interrupt-cells = <3>;
0120 };
0121
0122 l2: cache-controller@b0022000 {
0123 compatible = "arm,pl310-cache";
0124 reg = <0xb0022000 0x1000>;
0125 cache-unified;
0126 cache-level = <2>;
0127 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0128 arm,tag-latency = <3 3 2>;
0129 arm,data-latency = <5 3 3>;
0130 };
0131
0132 uart0: serial@b0120000 {
0133 compatible = "actions,s500-uart", "actions,owl-uart";
0134 reg = <0xb0120000 0x2000>;
0135 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0136 clocks = <&cmu CLK_UART0>;
0137 status = "disabled";
0138 };
0139
0140 uart1: serial@b0122000 {
0141 compatible = "actions,s500-uart", "actions,owl-uart";
0142 reg = <0xb0122000 0x2000>;
0143 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0144 clocks = <&cmu CLK_UART1>;
0145 status = "disabled";
0146 };
0147
0148 uart2: serial@b0124000 {
0149 compatible = "actions,s500-uart", "actions,owl-uart";
0150 reg = <0xb0124000 0x2000>;
0151 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0152 clocks = <&cmu CLK_UART2>;
0153 status = "disabled";
0154 };
0155
0156 uart3: serial@b0126000 {
0157 compatible = "actions,s500-uart", "actions,owl-uart";
0158 reg = <0xb0126000 0x2000>;
0159 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0160 clocks = <&cmu CLK_UART3>;
0161 status = "disabled";
0162 };
0163
0164 uart4: serial@b0128000 {
0165 compatible = "actions,s500-uart", "actions,owl-uart";
0166 reg = <0xb0128000 0x2000>;
0167 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0168 clocks = <&cmu CLK_UART4>;
0169 status = "disabled";
0170 };
0171
0172 uart5: serial@b012a000 {
0173 compatible = "actions,s500-uart", "actions,owl-uart";
0174 reg = <0xb012a000 0x2000>;
0175 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0176 clocks = <&cmu CLK_UART5>;
0177 status = "disabled";
0178 };
0179
0180 uart6: serial@b012c000 {
0181 compatible = "actions,s500-uart", "actions,owl-uart";
0182 reg = <0xb012c000 0x2000>;
0183 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0184 clocks = <&cmu CLK_UART6>;
0185 status = "disabled";
0186 };
0187
0188 cmu: clock-controller@b0160000 {
0189 compatible = "actions,s500-cmu";
0190 reg = <0xb0160000 0x8000>;
0191 clocks = <&hosc>, <&losc>;
0192 #clock-cells = <1>;
0193 #reset-cells = <1>;
0194 };
0195
0196 i2c0: i2c@b0170000 {
0197 compatible = "actions,s500-i2c";
0198 reg = <0xb0170000 0x4000>;
0199 clocks = <&cmu CLK_I2C0>;
0200 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0201 #address-cells = <1>;
0202 #size-cells = <0>;
0203 status = "disabled";
0204 };
0205
0206 i2c1: i2c@b0174000 {
0207 compatible = "actions,s500-i2c";
0208 reg = <0xb0174000 0x4000>;
0209 clocks = <&cmu CLK_I2C1>;
0210 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0211 #address-cells = <1>;
0212 #size-cells = <0>;
0213 status = "disabled";
0214 };
0215
0216 i2c2: i2c@b0178000 {
0217 compatible = "actions,s500-i2c";
0218 reg = <0xb0178000 0x4000>;
0219 clocks = <&cmu CLK_I2C2>;
0220 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0221 #address-cells = <1>;
0222 #size-cells = <0>;
0223 status = "disabled";
0224 };
0225
0226 i2c3: i2c@b017c000 {
0227 compatible = "actions,s500-i2c";
0228 reg = <0xb017c000 0x4000>;
0229 clocks = <&cmu CLK_I2C3>;
0230 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0231 #address-cells = <1>;
0232 #size-cells = <0>;
0233 status = "disabled";
0234 };
0235
0236 sirq: interrupt-controller@b01b0200 {
0237 compatible = "actions,s500-sirq";
0238 reg = <0xb01b0200 0x4>;
0239 interrupt-controller;
0240 #interrupt-cells = <2>;
0241 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */
0242 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */
0243 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */
0244 };
0245
0246 timer: timer@b0168000 {
0247 compatible = "actions,s500-timer";
0248 reg = <0xb0168000 0x8000>;
0249 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
0250 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0251 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0252 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0253 interrupt-names = "2hz0", "2hz1", "timer0", "timer1";
0254 };
0255
0256 sps: power-controller@b01b0100 {
0257 compatible = "actions,s500-sps";
0258 reg = <0xb01b0100 0x100>;
0259 #power-domain-cells = <1>;
0260 };
0261
0262 pinctrl: pinctrl@b01b0000 {
0263 compatible = "actions,s500-pinctrl";
0264 reg = <0xb01b0000 0x40>, /* GPIO */
0265 <0xb01b0040 0x10>, /* Multiplexing Control */
0266 <0xb01b0060 0x18>, /* PAD Control */
0267 <0xb01b0080 0xc>; /* PAD Drive Capacity */
0268 clocks = <&cmu CLK_GPIO>;
0269 gpio-controller;
0270 gpio-ranges = <&pinctrl 0 0 132>;
0271 #gpio-cells = <2>;
0272 interrupt-controller;
0273 #interrupt-cells = <2>;
0274 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, /* GPIOA */
0275 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, /* GPIOB */
0276 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, /* GPIOC */
0277 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, /* GPIOD */
0278 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; /* GPIOE */
0279 };
0280
0281 dma: dma-controller@b0260000 {
0282 compatible = "actions,s500-dma";
0283 reg = <0xb0260000 0xd00>;
0284 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
0285 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
0286 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
0287 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0288 #dma-cells = <1>;
0289 dma-channels = <12>;
0290 dma-requests = <46>;
0291 clocks = <&cmu CLK_DMAC>;
0292 power-domains = <&sps S500_PD_DMA>;
0293 };
0294
0295 mmc0: mmc@b0230000 {
0296 compatible = "actions,s500-mmc", "actions,owl-mmc";
0297 reg = <0xb0230000 0x38>;
0298 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0299 clocks = <&cmu CLK_SD0>;
0300 resets = <&cmu RESET_SD0>;
0301 dmas = <&dma 2>;
0302 dma-names = "mmc";
0303 status = "disabled";
0304 };
0305
0306 mmc1: mmc@b0234000 {
0307 compatible = "actions,s500-mmc", "actions,owl-mmc";
0308 reg = <0xb0234000 0x38>;
0309 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
0310 clocks = <&cmu CLK_SD1>;
0311 resets = <&cmu RESET_SD1>;
0312 dmas = <&dma 3>;
0313 dma-names = "mmc";
0314 status = "disabled";
0315 };
0316
0317 mmc2: mmc@b0238000 {
0318 compatible = "actions,s500-mmc", "actions,owl-mmc";
0319 reg = <0xb0238000 0x38>;
0320 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
0321 clocks = <&cmu CLK_SD2>;
0322 resets = <&cmu RESET_SD2>;
0323 dmas = <&dma 4>;
0324 dma-names = "mmc";
0325 status = "disabled";
0326 };
0327
0328 ethernet: ethernet@b0310000 {
0329 compatible = "actions,s500-emac", "actions,owl-emac";
0330 reg = <0xb0310000 0x10000>;
0331 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0332 clocks = <&cmu CLK_ETHERNET>, <&cmu CLK_RMII_REF>;
0333 clock-names = "eth", "rmii";
0334 resets = <&cmu RESET_ETHERNET>;
0335 status = "disabled";
0336 };
0337 };
0338 };
