0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0003
0004 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
0005
0006 / {
0007 #address-cells = <1>;
0008 #size-cells = <1>;
0009 model = "Marvell Orion5x SoC";
0010 compatible = "marvell,orion5x";
0011 interrupt-parent = <&intc>;
0012
0013 aliases {
0014 gpio0 = &gpio0;
0015 };
0016
0017 soc {
0018 #address-cells = <2>;
0019 #size-cells = <1>;
0020 controller = <&mbusc>;
0021
0022 devbus_bootcs: devbus-bootcs {
0023 compatible = "marvell,orion-devbus";
0024 reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
0025 ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
0026 #address-cells = <1>;
0027 #size-cells = <1>;
0028 clocks = <&core_clk 0>;
0029 status = "disabled";
0030 };
0031
0032 devbus_cs0: devbus-cs0 {
0033 compatible = "marvell,orion-devbus";
0034 reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
0035 ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
0036 #address-cells = <1>;
0037 #size-cells = <1>;
0038 clocks = <&core_clk 0>;
0039 status = "disabled";
0040 };
0041
0042 devbus_cs1: devbus-cs1 {
0043 compatible = "marvell,orion-devbus";
0044 reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
0045 ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
0046 #address-cells = <1>;
0047 #size-cells = <1>;
0048 clocks = <&core_clk 0>;
0049 status = "disabled";
0050 };
0051
0052 devbus_cs2: devbus-cs2 {
0053 compatible = "marvell,orion-devbus";
0054 reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
0055 ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>;
0056 #address-cells = <1>;
0057 #size-cells = <1>;
0058 clocks = <&core_clk 0>;
0059 status = "disabled";
0060 };
0061
0062 internal-regs {
0063 compatible = "simple-bus";
0064 #address-cells = <1>;
0065 #size-cells = <1>;
0066 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
0067
0068 gpio0: gpio@10100 {
0069 compatible = "marvell,orion-gpio";
0070 #gpio-cells = <2>;
0071 gpio-controller;
0072 reg = <0x10100 0x40>;
0073 ngpios = <32>;
0074 interrupt-controller;
0075 #interrupt-cells = <2>;
0076 interrupts = <6>, <7>, <8>, <9>;
0077 };
0078
0079 spi: spi@10600 {
0080 compatible = "marvell,orion-spi";
0081 #address-cells = <1>;
0082 #size-cells = <0>;
0083 cell-index = <0>;
0084 reg = <0x10600 0x28>;
0085 status = "disabled";
0086 };
0087
0088 i2c: i2c@11000 {
0089 compatible = "marvell,mv64xxx-i2c";
0090 reg = <0x11000 0x20>;
0091 #address-cells = <1>;
0092 #size-cells = <0>;
0093 interrupts = <5>;
0094 clocks = <&core_clk 0>;
0095 status = "disabled";
0096 };
0097
0098 uart0: serial@12000 {
0099 compatible = "ns16550a";
0100 reg = <0x12000 0x100>;
0101 reg-shift = <2>;
0102 interrupts = <3>;
0103 clocks = <&core_clk 0>;
0104 status = "disabled";
0105 };
0106
0107 uart1: serial@12100 {
0108 compatible = "ns16550a";
0109 reg = <0x12100 0x100>;
0110 reg-shift = <2>;
0111 interrupts = <4>;
0112 clocks = <&core_clk 0>;
0113 status = "disabled";
0114 };
0115
0116 bridge_intc: bridge-interrupt-ctrl@20110 {
0117 compatible = "marvell,orion-bridge-intc";
0118 interrupt-controller;
0119 #interrupt-cells = <1>;
0120 reg = <0x20110 0x8>;
0121 interrupts = <0>;
0122 marvell,#interrupts = <4>;
0123 };
0124
0125 intc: interrupt-controller@20200 {
0126 compatible = "marvell,orion-intc";
0127 interrupt-controller;
0128 #interrupt-cells = <1>;
0129 reg = <0x20200 0x08>;
0130 };
0131
0132 timer: timer@20300 {
0133 compatible = "marvell,orion-timer";
0134 reg = <0x20300 0x20>;
0135 interrupt-parent = <&bridge_intc>;
0136 interrupts = <1>, <2>;
0137 clocks = <&core_clk 0>;
0138 };
0139
0140 wdt: wdt@20300 {
0141 compatible = "marvell,orion-wdt";
0142 reg = <0x20300 0x28>, <0x20108 0x4>;
0143 interrupt-parent = <&bridge_intc>;
0144 interrupts = <3>;
0145 clocks = <&core_clk 0>;
0146 status = "okay";
0147 };
0148
0149 ehci0: ehci@50000 {
0150 compatible = "marvell,orion-ehci";
0151 reg = <0x50000 0x1000>;
0152 interrupts = <17>;
0153 status = "disabled";
0154 };
0155
0156 xor: dma-controller@60900 {
0157 compatible = "marvell,orion-xor";
0158 reg = <0x60900 0x100
0159 0x60b00 0x100>;
0160 status = "okay";
0161
0162 xor00 {
0163 interrupts = <30>;
0164 dmacap,memcpy;
0165 dmacap,xor;
0166 };
0167 xor01 {
0168 interrupts = <31>;
0169 dmacap,memcpy;
0170 dmacap,xor;
0171 dmacap,memset;
0172 };
0173 };
0174
0175 eth: ethernet-controller@72000 {
0176 compatible = "marvell,orion-eth";
0177 #address-cells = <1>;
0178 #size-cells = <0>;
0179 reg = <0x72000 0x4000>;
0180 marvell,tx-checksum-limit = <1600>;
0181 status = "disabled";
0182
0183 ethport: ethernet-port@0 {
0184 compatible = "marvell,orion-eth-port";
0185 reg = <0>;
0186 interrupts = <21>;
0187 /* overwrite MAC address in bootloader */
0188 local-mac-address = [00 00 00 00 00 00];
0189 /* set phy-handle property in board file */
0190 };
0191 };
0192
0193 mdio: mdio-bus@72004 {
0194 compatible = "marvell,orion-mdio";
0195 #address-cells = <1>;
0196 #size-cells = <0>;
0197 reg = <0x72004 0x84>;
0198 interrupts = <22>;
0199 status = "disabled";
0200
0201 /* add phy nodes in board file */
0202 };
0203
0204 sata: sata@80000 {
0205 compatible = "marvell,orion-sata";
0206 reg = <0x80000 0x5000>;
0207 interrupts = <29>;
0208 status = "disabled";
0209 };
0210
0211 cesa: crypto@90000 {
0212 compatible = "marvell,orion-crypto";
0213 reg = <0x90000 0x10000>;
0214 reg-names = "regs";
0215 interrupts = <28>;
0216 marvell,crypto-srams = <&crypto_sram>;
0217 marvell,crypto-sram-size = <0x800>;
0218 status = "okay";
0219 };
0220
0221 ehci1: ehci@a0000 {
0222 compatible = "marvell,orion-ehci";
0223 reg = <0xa0000 0x1000>;
0224 interrupts = <12>;
0225 status = "disabled";
0226 };
0227 };
0228
0229 crypto_sram: sa-sram {
0230 compatible = "mmio-sram";
0231 reg = <MBUS_ID(0x09, 0x00) 0x0 0x800>;
0232 #address-cells = <1>;
0233 #size-cells = <1>;
0234 };
0235 };
0236 };
