0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for OMAP5 clock data
0004 *
0005 * Copyright (C) 2013 Texas Instruments, Inc.
0006 */
0007 &cm_core_aon_clocks {
0008 pad_clks_src_ck: pad_clks_src_ck {
0009 #clock-cells = <0>;
0010 compatible = "fixed-clock";
0011 clock-output-names = "pad_clks_src_ck";
0012 clock-frequency = <12000000>;
0013 };
0014
0015 pad_clks_ck: pad_clks_ck@108 {
0016 #clock-cells = <0>;
0017 compatible = "ti,gate-clock";
0018 clock-output-names = "pad_clks_ck";
0019 clocks = <&pad_clks_src_ck>;
0020 ti,bit-shift = <8>;
0021 reg = <0x0108>;
0022 };
0023
0024 secure_32k_clk_src_ck: secure_32k_clk_src_ck {
0025 #clock-cells = <0>;
0026 compatible = "fixed-clock";
0027 clock-output-names = "secure_32k_clk_src_ck";
0028 clock-frequency = <32768>;
0029 };
0030
0031 slimbus_src_clk: slimbus_src_clk {
0032 #clock-cells = <0>;
0033 compatible = "fixed-clock";
0034 clock-output-names = "slimbus_src_clk";
0035 clock-frequency = <12000000>;
0036 };
0037
0038 slimbus_clk: slimbus_clk@108 {
0039 #clock-cells = <0>;
0040 compatible = "ti,gate-clock";
0041 clock-output-names = "slimbus_clk";
0042 clocks = <&slimbus_src_clk>;
0043 ti,bit-shift = <10>;
0044 reg = <0x0108>;
0045 };
0046
0047 sys_32k_ck: sys_32k_ck {
0048 #clock-cells = <0>;
0049 compatible = "fixed-clock";
0050 clock-output-names = "sys_32k_ck";
0051 clock-frequency = <32768>;
0052 };
0053
0054 virt_12000000_ck: virt_12000000_ck {
0055 #clock-cells = <0>;
0056 compatible = "fixed-clock";
0057 clock-output-names = "virt_12000000_ck";
0058 clock-frequency = <12000000>;
0059 };
0060
0061 virt_13000000_ck: virt_13000000_ck {
0062 #clock-cells = <0>;
0063 compatible = "fixed-clock";
0064 clock-output-names = "virt_13000000_ck";
0065 clock-frequency = <13000000>;
0066 };
0067
0068 virt_16800000_ck: virt_16800000_ck {
0069 #clock-cells = <0>;
0070 compatible = "fixed-clock";
0071 clock-output-names = "virt_16800000_ck";
0072 clock-frequency = <16800000>;
0073 };
0074
0075 virt_19200000_ck: virt_19200000_ck {
0076 #clock-cells = <0>;
0077 compatible = "fixed-clock";
0078 clock-output-names = "virt_19200000_ck";
0079 clock-frequency = <19200000>;
0080 };
0081
0082 virt_26000000_ck: virt_26000000_ck {
0083 #clock-cells = <0>;
0084 compatible = "fixed-clock";
0085 clock-output-names = "virt_26000000_ck";
0086 clock-frequency = <26000000>;
0087 };
0088
0089 virt_27000000_ck: virt_27000000_ck {
0090 #clock-cells = <0>;
0091 compatible = "fixed-clock";
0092 clock-output-names = "virt_27000000_ck";
0093 clock-frequency = <27000000>;
0094 };
0095
0096 virt_38400000_ck: virt_38400000_ck {
0097 #clock-cells = <0>;
0098 compatible = "fixed-clock";
0099 clock-output-names = "virt_38400000_ck";
0100 clock-frequency = <38400000>;
0101 };
0102
0103 xclk60mhsp1_ck: xclk60mhsp1_ck {
0104 #clock-cells = <0>;
0105 compatible = "fixed-clock";
0106 clock-output-names = "xclk60mhsp1_ck";
0107 clock-frequency = <60000000>;
0108 };
0109
0110 xclk60mhsp2_ck: xclk60mhsp2_ck {
0111 #clock-cells = <0>;
0112 compatible = "fixed-clock";
0113 clock-output-names = "xclk60mhsp2_ck";
0114 clock-frequency = <60000000>;
0115 };
0116
0117 dpll_abe_ck: dpll_abe_ck@1e0 {
0118 #clock-cells = <0>;
0119 compatible = "ti,omap4-dpll-m4xen-clock";
0120 clock-output-names = "dpll_abe_ck";
0121 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
0122 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
0123 };
0124
0125 dpll_abe_x2_ck: dpll_abe_x2_ck {
0126 #clock-cells = <0>;
0127 compatible = "ti,omap4-dpll-x2-clock";
0128 clock-output-names = "dpll_abe_x2_ck";
0129 clocks = <&dpll_abe_ck>;
0130 };
0131
0132 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
0133 #clock-cells = <0>;
0134 compatible = "ti,divider-clock";
0135 clock-output-names = "dpll_abe_m2x2_ck";
0136 clocks = <&dpll_abe_x2_ck>;
0137 ti,max-div = <31>;
0138 reg = <0x01f0>;
0139 ti,index-starts-at-one;
0140 };
0141
0142 abe_24m_fclk: abe_24m_fclk {
0143 #clock-cells = <0>;
0144 compatible = "fixed-factor-clock";
0145 clock-output-names = "abe_24m_fclk";
0146 clocks = <&dpll_abe_m2x2_ck>;
0147 clock-mult = <1>;
0148 clock-div = <8>;
0149 };
0150
0151 abe_clk: abe_clk@108 {
0152 #clock-cells = <0>;
0153 compatible = "ti,divider-clock";
0154 clock-output-names = "abe_clk";
0155 clocks = <&dpll_abe_m2x2_ck>;
0156 ti,max-div = <4>;
0157 reg = <0x0108>;
0158 ti,index-power-of-two;
0159 };
0160
0161 abe_iclk: abe_iclk@528 {
0162 #clock-cells = <0>;
0163 compatible = "ti,divider-clock";
0164 clock-output-names = "abe_iclk";
0165 clocks = <&aess_fclk>;
0166 ti,bit-shift = <24>;
0167 reg = <0x0528>;
0168 ti,dividers = <2>, <1>;
0169 };
0170
0171 abe_lp_clk_div: abe_lp_clk_div {
0172 #clock-cells = <0>;
0173 compatible = "fixed-factor-clock";
0174 clock-output-names = "abe_lp_clk_div";
0175 clocks = <&dpll_abe_m2x2_ck>;
0176 clock-mult = <1>;
0177 clock-div = <16>;
0178 };
0179
0180 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
0181 #clock-cells = <0>;
0182 compatible = "ti,divider-clock";
0183 clock-output-names = "dpll_abe_m3x2_ck";
0184 clocks = <&dpll_abe_x2_ck>;
0185 ti,max-div = <31>;
0186 reg = <0x01f4>;
0187 ti,index-starts-at-one;
0188 };
0189
0190 dpll_core_byp_mux: dpll_core_byp_mux@12c {
0191 #clock-cells = <0>;
0192 compatible = "ti,mux-clock";
0193 clock-output-names = "dpll_core_byp_mux";
0194 clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
0195 ti,bit-shift = <23>;
0196 reg = <0x012c>;
0197 };
0198
0199 dpll_core_ck: dpll_core_ck@120 {
0200 #clock-cells = <0>;
0201 compatible = "ti,omap4-dpll-core-clock";
0202 clock-output-names = "dpll_core_ck";
0203 clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
0204 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
0205 };
0206
0207 dpll_core_x2_ck: dpll_core_x2_ck {
0208 #clock-cells = <0>;
0209 compatible = "ti,omap4-dpll-x2-clock";
0210 clock-output-names = "dpll_core_x2_ck";
0211 clocks = <&dpll_core_ck>;
0212 };
0213
0214 dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 {
0215 #clock-cells = <0>;
0216 compatible = "ti,divider-clock";
0217 clock-output-names = "dpll_core_h21x2_ck";
0218 clocks = <&dpll_core_x2_ck>;
0219 ti,max-div = <63>;
0220 reg = <0x0150>;
0221 ti,index-starts-at-one;
0222 };
0223
0224 c2c_fclk: c2c_fclk {
0225 #clock-cells = <0>;
0226 compatible = "fixed-factor-clock";
0227 clock-output-names = "c2c_fclk";
0228 clocks = <&dpll_core_h21x2_ck>;
0229 clock-mult = <1>;
0230 clock-div = <1>;
0231 };
0232
0233 c2c_iclk: c2c_iclk {
0234 #clock-cells = <0>;
0235 compatible = "fixed-factor-clock";
0236 clock-output-names = "c2c_iclk";
0237 clocks = <&c2c_fclk>;
0238 clock-mult = <1>;
0239 clock-div = <2>;
0240 };
0241
0242 dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 {
0243 #clock-cells = <0>;
0244 compatible = "ti,divider-clock";
0245 clock-output-names = "dpll_core_h11x2_ck";
0246 clocks = <&dpll_core_x2_ck>;
0247 ti,max-div = <63>;
0248 reg = <0x0138>;
0249 ti,index-starts-at-one;
0250 };
0251
0252 dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
0253 #clock-cells = <0>;
0254 compatible = "ti,divider-clock";
0255 clock-output-names = "dpll_core_h12x2_ck";
0256 clocks = <&dpll_core_x2_ck>;
0257 ti,max-div = <63>;
0258 reg = <0x013c>;
0259 ti,index-starts-at-one;
0260 };
0261
0262 dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
0263 #clock-cells = <0>;
0264 compatible = "ti,divider-clock";
0265 clock-output-names = "dpll_core_h13x2_ck";
0266 clocks = <&dpll_core_x2_ck>;
0267 ti,max-div = <63>;
0268 reg = <0x0140>;
0269 ti,index-starts-at-one;
0270 };
0271
0272 dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
0273 #clock-cells = <0>;
0274 compatible = "ti,divider-clock";
0275 clock-output-names = "dpll_core_h14x2_ck";
0276 clocks = <&dpll_core_x2_ck>;
0277 ti,max-div = <63>;
0278 reg = <0x0144>;
0279 ti,index-starts-at-one;
0280 };
0281
0282 dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
0283 #clock-cells = <0>;
0284 compatible = "ti,divider-clock";
0285 clock-output-names = "dpll_core_h22x2_ck";
0286 clocks = <&dpll_core_x2_ck>;
0287 ti,max-div = <63>;
0288 reg = <0x0154>;
0289 ti,index-starts-at-one;
0290 };
0291
0292 dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
0293 #clock-cells = <0>;
0294 compatible = "ti,divider-clock";
0295 clock-output-names = "dpll_core_h23x2_ck";
0296 clocks = <&dpll_core_x2_ck>;
0297 ti,max-div = <63>;
0298 reg = <0x0158>;
0299 ti,index-starts-at-one;
0300 };
0301
0302 dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
0303 #clock-cells = <0>;
0304 compatible = "ti,divider-clock";
0305 clock-output-names = "dpll_core_h24x2_ck";
0306 clocks = <&dpll_core_x2_ck>;
0307 ti,max-div = <63>;
0308 reg = <0x015c>;
0309 ti,index-starts-at-one;
0310 };
0311
0312 dpll_core_m2_ck: dpll_core_m2_ck@130 {
0313 #clock-cells = <0>;
0314 compatible = "ti,divider-clock";
0315 clock-output-names = "dpll_core_m2_ck";
0316 clocks = <&dpll_core_ck>;
0317 ti,max-div = <31>;
0318 reg = <0x0130>;
0319 ti,index-starts-at-one;
0320 };
0321
0322 dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 {
0323 #clock-cells = <0>;
0324 compatible = "ti,divider-clock";
0325 clock-output-names = "dpll_core_m3x2_ck";
0326 clocks = <&dpll_core_x2_ck>;
0327 ti,max-div = <31>;
0328 reg = <0x0134>;
0329 ti,index-starts-at-one;
0330 };
0331
0332 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
0333 #clock-cells = <0>;
0334 compatible = "fixed-factor-clock";
0335 clock-output-names = "iva_dpll_hs_clk_div";
0336 clocks = <&dpll_core_h12x2_ck>;
0337 clock-mult = <1>;
0338 clock-div = <1>;
0339 };
0340
0341 dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
0342 #clock-cells = <0>;
0343 compatible = "ti,mux-clock";
0344 clock-output-names = "dpll_iva_byp_mux";
0345 clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
0346 ti,bit-shift = <23>;
0347 reg = <0x01ac>;
0348 };
0349
0350 dpll_iva_ck: dpll_iva_ck@1a0 {
0351 #clock-cells = <0>;
0352 compatible = "ti,omap4-dpll-clock";
0353 clock-output-names = "dpll_iva_ck";
0354 clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
0355 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
0356 assigned-clocks = <&dpll_iva_ck>;
0357 assigned-clock-rates = <1165000000>;
0358 };
0359
0360 dpll_iva_x2_ck: dpll_iva_x2_ck {
0361 #clock-cells = <0>;
0362 compatible = "ti,omap4-dpll-x2-clock";
0363 clock-output-names = "dpll_iva_x2_ck";
0364 clocks = <&dpll_iva_ck>;
0365 };
0366
0367 dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 {
0368 #clock-cells = <0>;
0369 compatible = "ti,divider-clock";
0370 clock-output-names = "dpll_iva_h11x2_ck";
0371 clocks = <&dpll_iva_x2_ck>;
0372 ti,max-div = <63>;
0373 reg = <0x01b8>;
0374 ti,index-starts-at-one;
0375 assigned-clocks = <&dpll_iva_h11x2_ck>;
0376 assigned-clock-rates = <465920000>;
0377 };
0378
0379 dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
0380 #clock-cells = <0>;
0381 compatible = "ti,divider-clock";
0382 clock-output-names = "dpll_iva_h12x2_ck";
0383 clocks = <&dpll_iva_x2_ck>;
0384 ti,max-div = <63>;
0385 reg = <0x01bc>;
0386 ti,index-starts-at-one;
0387 assigned-clocks = <&dpll_iva_h12x2_ck>;
0388 assigned-clock-rates = <388300000>;
0389 };
0390
0391 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
0392 #clock-cells = <0>;
0393 compatible = "fixed-factor-clock";
0394 clock-output-names = "mpu_dpll_hs_clk_div";
0395 clocks = <&dpll_core_h12x2_ck>;
0396 clock-mult = <1>;
0397 clock-div = <1>;
0398 };
0399
0400 dpll_mpu_ck: dpll_mpu_ck@160 {
0401 #clock-cells = <0>;
0402 compatible = "ti,omap5-mpu-dpll-clock";
0403 clock-output-names = "dpll_mpu_ck";
0404 clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
0405 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
0406 };
0407
0408 dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
0409 #clock-cells = <0>;
0410 compatible = "ti,divider-clock";
0411 clock-output-names = "dpll_mpu_m2_ck";
0412 clocks = <&dpll_mpu_ck>;
0413 ti,max-div = <31>;
0414 reg = <0x0170>;
0415 ti,index-starts-at-one;
0416 };
0417
0418 per_dpll_hs_clk_div: per_dpll_hs_clk_div {
0419 #clock-cells = <0>;
0420 compatible = "fixed-factor-clock";
0421 clock-output-names = "per_dpll_hs_clk_div";
0422 clocks = <&dpll_abe_m3x2_ck>;
0423 clock-mult = <1>;
0424 clock-div = <2>;
0425 };
0426
0427 usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
0428 #clock-cells = <0>;
0429 compatible = "fixed-factor-clock";
0430 clock-output-names = "usb_dpll_hs_clk_div";
0431 clocks = <&dpll_abe_m3x2_ck>;
0432 clock-mult = <1>;
0433 clock-div = <3>;
0434 };
0435
0436 l3_iclk_div: l3_iclk_div@100 {
0437 #clock-cells = <0>;
0438 compatible = "ti,divider-clock";
0439 clock-output-names = "l3_iclk_div";
0440 ti,max-div = <2>;
0441 ti,bit-shift = <4>;
0442 reg = <0x100>;
0443 clocks = <&dpll_core_h12x2_ck>;
0444 ti,index-power-of-two;
0445 };
0446
0447 gpu_l3_iclk: gpu_l3_iclk {
0448 #clock-cells = <0>;
0449 compatible = "fixed-factor-clock";
0450 clock-output-names = "gpu_l3_iclk";
0451 clocks = <&l3_iclk_div>;
0452 clock-mult = <1>;
0453 clock-div = <1>;
0454 };
0455
0456 l4_root_clk_div: l4_root_clk_div@100 {
0457 #clock-cells = <0>;
0458 compatible = "ti,divider-clock";
0459 clock-output-names = "l4_root_clk_div";
0460 ti,max-div = <2>;
0461 ti,bit-shift = <8>;
0462 reg = <0x100>;
0463 clocks = <&l3_iclk_div>;
0464 ti,index-power-of-two;
0465 };
0466
0467 slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
0468 #clock-cells = <0>;
0469 compatible = "ti,gate-clock";
0470 clock-output-names = "slimbus1_slimbus_clk";
0471 clocks = <&slimbus_clk>;
0472 ti,bit-shift = <11>;
0473 reg = <0x0560>;
0474 };
0475
0476 aess_fclk: aess_fclk@528 {
0477 #clock-cells = <0>;
0478 compatible = "ti,divider-clock";
0479 clock-output-names = "aess_fclk";
0480 clocks = <&abe_clk>;
0481 ti,bit-shift = <24>;
0482 ti,max-div = <2>;
0483 reg = <0x0528>;
0484 };
0485
0486 mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
0487 #clock-cells = <0>;
0488 compatible = "ti,mux-clock";
0489 clock-output-names = "mcasp_sync_mux_ck";
0490 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
0491 ti,bit-shift = <26>;
0492 reg = <0x0540>;
0493 };
0494
0495 mcasp_gfclk: mcasp_gfclk@540 {
0496 #clock-cells = <0>;
0497 compatible = "ti,mux-clock";
0498 clock-output-names = "mcasp_gfclk";
0499 clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
0500 ti,bit-shift = <24>;
0501 reg = <0x0540>;
0502 };
0503
0504 dummy_ck: dummy_ck {
0505 #clock-cells = <0>;
0506 compatible = "fixed-clock";
0507 clock-output-names = "dummy_ck";
0508 clock-frequency = <0>;
0509 };
0510 };
0511 &prm_clocks {
0512 sys_clkin: sys_clkin@110 {
0513 #clock-cells = <0>;
0514 compatible = "ti,mux-clock";
0515 clock-output-names = "sys_clkin";
0516 clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
0517 reg = <0x0110>;
0518 ti,index-starts-at-one;
0519 };
0520
0521 abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
0522 #clock-cells = <0>;
0523 compatible = "ti,mux-clock";
0524 clock-output-names = "abe_dpll_bypass_clk_mux";
0525 clocks = <&sys_clkin>, <&sys_32k_ck>;
0526 reg = <0x0108>;
0527 };
0528
0529 abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
0530 #clock-cells = <0>;
0531 compatible = "ti,mux-clock";
0532 clock-output-names = "abe_dpll_clk_mux";
0533 clocks = <&sys_clkin>, <&sys_32k_ck>;
0534 reg = <0x010c>;
0535 };
0536
0537 custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
0538 #clock-cells = <0>;
0539 compatible = "fixed-factor-clock";
0540 clock-output-names = "custefuse_sys_gfclk_div";
0541 clocks = <&sys_clkin>;
0542 clock-mult = <1>;
0543 clock-div = <2>;
0544 };
0545
0546 dss_syc_gfclk_div: dss_syc_gfclk_div {
0547 #clock-cells = <0>;
0548 compatible = "fixed-factor-clock";
0549 clock-output-names = "dss_syc_gfclk_div";
0550 clocks = <&sys_clkin>;
0551 clock-mult = <1>;
0552 clock-div = <1>;
0553 };
0554
0555 wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
0556 #clock-cells = <0>;
0557 compatible = "ti,mux-clock";
0558 clock-output-names = "wkupaon_iclk_mux";
0559 clocks = <&sys_clkin>, <&abe_lp_clk_div>;
0560 reg = <0x0108>;
0561 };
0562
0563 l3instr_ts_gclk_div: l3instr_ts_gclk_div {
0564 #clock-cells = <0>;
0565 compatible = "fixed-factor-clock";
0566 clock-output-names = "l3instr_ts_gclk_div";
0567 clocks = <&wkupaon_iclk_mux>;
0568 clock-mult = <1>;
0569 clock-div = <1>;
0570 };
0571 };
0572
0573 &cm_core_clocks {
0574
0575 dpll_per_byp_mux: dpll_per_byp_mux@14c {
0576 #clock-cells = <0>;
0577 compatible = "ti,mux-clock";
0578 clock-output-names = "dpll_per_byp_mux";
0579 clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
0580 ti,bit-shift = <23>;
0581 reg = <0x014c>;
0582 };
0583
0584 dpll_per_ck: dpll_per_ck@140 {
0585 #clock-cells = <0>;
0586 compatible = "ti,omap4-dpll-clock";
0587 clock-output-names = "dpll_per_ck";
0588 clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
0589 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
0590 };
0591
0592 dpll_per_x2_ck: dpll_per_x2_ck {
0593 #clock-cells = <0>;
0594 compatible = "ti,omap4-dpll-x2-clock";
0595 clock-output-names = "dpll_per_x2_ck";
0596 clocks = <&dpll_per_ck>;
0597 };
0598
0599 dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
0600 #clock-cells = <0>;
0601 compatible = "ti,divider-clock";
0602 clock-output-names = "dpll_per_h11x2_ck";
0603 clocks = <&dpll_per_x2_ck>;
0604 ti,max-div = <63>;
0605 reg = <0x0158>;
0606 ti,index-starts-at-one;
0607 };
0608
0609 dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
0610 #clock-cells = <0>;
0611 compatible = "ti,divider-clock";
0612 clock-output-names = "dpll_per_h12x2_ck";
0613 clocks = <&dpll_per_x2_ck>;
0614 ti,max-div = <63>;
0615 reg = <0x015c>;
0616 ti,index-starts-at-one;
0617 };
0618
0619 dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
0620 #clock-cells = <0>;
0621 compatible = "ti,divider-clock";
0622 clock-output-names = "dpll_per_h14x2_ck";
0623 clocks = <&dpll_per_x2_ck>;
0624 ti,max-div = <63>;
0625 reg = <0x0164>;
0626 ti,index-starts-at-one;
0627 };
0628
0629 dpll_per_m2_ck: dpll_per_m2_ck@150 {
0630 #clock-cells = <0>;
0631 compatible = "ti,divider-clock";
0632 clock-output-names = "dpll_per_m2_ck";
0633 clocks = <&dpll_per_ck>;
0634 ti,max-div = <31>;
0635 reg = <0x0150>;
0636 ti,index-starts-at-one;
0637 };
0638
0639 dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
0640 #clock-cells = <0>;
0641 compatible = "ti,divider-clock";
0642 clock-output-names = "dpll_per_m2x2_ck";
0643 clocks = <&dpll_per_x2_ck>;
0644 ti,max-div = <31>;
0645 reg = <0x0150>;
0646 ti,index-starts-at-one;
0647 };
0648
0649 dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 {
0650 #clock-cells = <0>;
0651 compatible = "ti,divider-clock";
0652 clock-output-names = "dpll_per_m3x2_ck";
0653 clocks = <&dpll_per_x2_ck>;
0654 ti,max-div = <31>;
0655 reg = <0x0154>;
0656 ti,index-starts-at-one;
0657 };
0658
0659 dpll_unipro1_ck: dpll_unipro1_ck@200 {
0660 #clock-cells = <0>;
0661 compatible = "ti,omap4-dpll-clock";
0662 clock-output-names = "dpll_unipro1_ck";
0663 clocks = <&sys_clkin>, <&sys_clkin>;
0664 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
0665 };
0666
0667 dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
0668 #clock-cells = <0>;
0669 compatible = "fixed-factor-clock";
0670 clock-output-names = "dpll_unipro1_clkdcoldo";
0671 clocks = <&dpll_unipro1_ck>;
0672 clock-mult = <1>;
0673 clock-div = <1>;
0674 };
0675
0676 dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 {
0677 #clock-cells = <0>;
0678 compatible = "ti,divider-clock";
0679 clock-output-names = "dpll_unipro1_m2_ck";
0680 clocks = <&dpll_unipro1_ck>;
0681 ti,max-div = <127>;
0682 reg = <0x0210>;
0683 ti,index-starts-at-one;
0684 };
0685
0686 dpll_unipro2_ck: dpll_unipro2_ck@1c0 {
0687 #clock-cells = <0>;
0688 compatible = "ti,omap4-dpll-clock";
0689 clock-output-names = "dpll_unipro2_ck";
0690 clocks = <&sys_clkin>, <&sys_clkin>;
0691 reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
0692 };
0693
0694 dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
0695 #clock-cells = <0>;
0696 compatible = "fixed-factor-clock";
0697 clock-output-names = "dpll_unipro2_clkdcoldo";
0698 clocks = <&dpll_unipro2_ck>;
0699 clock-mult = <1>;
0700 clock-div = <1>;
0701 };
0702
0703 dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 {
0704 #clock-cells = <0>;
0705 compatible = "ti,divider-clock";
0706 clock-output-names = "dpll_unipro2_m2_ck";
0707 clocks = <&dpll_unipro2_ck>;
0708 ti,max-div = <127>;
0709 reg = <0x01d0>;
0710 ti,index-starts-at-one;
0711 };
0712
0713 dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
0714 #clock-cells = <0>;
0715 compatible = "ti,mux-clock";
0716 clock-output-names = "dpll_usb_byp_mux";
0717 clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
0718 ti,bit-shift = <23>;
0719 reg = <0x018c>;
0720 };
0721
0722 dpll_usb_ck: dpll_usb_ck@180 {
0723 #clock-cells = <0>;
0724 compatible = "ti,omap4-dpll-j-type-clock";
0725 clock-output-names = "dpll_usb_ck";
0726 clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
0727 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
0728 };
0729
0730 dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
0731 #clock-cells = <0>;
0732 compatible = "fixed-factor-clock";
0733 clock-output-names = "dpll_usb_clkdcoldo";
0734 clocks = <&dpll_usb_ck>;
0735 clock-mult = <1>;
0736 clock-div = <1>;
0737 };
0738
0739 dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
0740 #clock-cells = <0>;
0741 compatible = "ti,divider-clock";
0742 clock-output-names = "dpll_usb_m2_ck";
0743 clocks = <&dpll_usb_ck>;
0744 ti,max-div = <127>;
0745 reg = <0x0190>;
0746 ti,index-starts-at-one;
0747 };
0748
0749 func_128m_clk: func_128m_clk {
0750 #clock-cells = <0>;
0751 compatible = "fixed-factor-clock";
0752 clock-output-names = "func_128m_clk";
0753 clocks = <&dpll_per_h11x2_ck>;
0754 clock-mult = <1>;
0755 clock-div = <2>;
0756 };
0757
0758 func_12m_fclk: func_12m_fclk {
0759 #clock-cells = <0>;
0760 compatible = "fixed-factor-clock";
0761 clock-output-names = "func_12m_fclk";
0762 clocks = <&dpll_per_m2x2_ck>;
0763 clock-mult = <1>;
0764 clock-div = <16>;
0765 };
0766
0767 func_24m_clk: func_24m_clk {
0768 #clock-cells = <0>;
0769 compatible = "fixed-factor-clock";
0770 clock-output-names = "func_24m_clk";
0771 clocks = <&dpll_per_m2_ck>;
0772 clock-mult = <1>;
0773 clock-div = <4>;
0774 };
0775
0776 func_48m_fclk: func_48m_fclk {
0777 #clock-cells = <0>;
0778 compatible = "fixed-factor-clock";
0779 clock-output-names = "func_48m_fclk";
0780 clocks = <&dpll_per_m2x2_ck>;
0781 clock-mult = <1>;
0782 clock-div = <4>;
0783 };
0784
0785 func_96m_fclk: func_96m_fclk {
0786 #clock-cells = <0>;
0787 compatible = "fixed-factor-clock";
0788 clock-output-names = "func_96m_fclk";
0789 clocks = <&dpll_per_m2x2_ck>;
0790 clock-mult = <1>;
0791 clock-div = <2>;
0792 };
0793
0794 l3init_60m_fclk: l3init_60m_fclk@104 {
0795 #clock-cells = <0>;
0796 compatible = "ti,divider-clock";
0797 clock-output-names = "l3init_60m_fclk";
0798 clocks = <&dpll_usb_m2_ck>;
0799 reg = <0x0104>;
0800 ti,dividers = <1>, <8>;
0801 };
0802
0803 iss_ctrlclk: iss_ctrlclk@1320 {
0804 #clock-cells = <0>;
0805 compatible = "ti,gate-clock";
0806 clock-output-names = "iss_ctrlclk";
0807 clocks = <&func_96m_fclk>;
0808 ti,bit-shift = <8>;
0809 reg = <0x1320>;
0810 };
0811
0812 lli_txphy_clk: lli_txphy_clk@f20 {
0813 #clock-cells = <0>;
0814 compatible = "ti,gate-clock";
0815 clock-output-names = "lli_txphy_clk";
0816 clocks = <&dpll_unipro1_clkdcoldo>;
0817 ti,bit-shift = <8>;
0818 reg = <0x0f20>;
0819 };
0820
0821 lli_txphy_ls_clk: lli_txphy_ls_clk@f20 {
0822 #clock-cells = <0>;
0823 compatible = "ti,gate-clock";
0824 clock-output-names = "lli_txphy_ls_clk";
0825 clocks = <&dpll_unipro1_m2_ck>;
0826 ti,bit-shift = <9>;
0827 reg = <0x0f20>;
0828 };
0829
0830 usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
0831 #clock-cells = <0>;
0832 compatible = "ti,gate-clock";
0833 clock-output-names = "usb_phy_cm_clk32k";
0834 clocks = <&sys_32k_ck>;
0835 ti,bit-shift = <8>;
0836 reg = <0x0640>;
0837 };
0838
0839 fdif_fclk: fdif_fclk@1328 {
0840 #clock-cells = <0>;
0841 compatible = "ti,divider-clock";
0842 clock-output-names = "fdif_fclk";
0843 clocks = <&dpll_per_h11x2_ck>;
0844 ti,bit-shift = <24>;
0845 ti,max-div = <2>;
0846 reg = <0x1328>;
0847 };
0848
0849 gpu_core_gclk_mux: gpu_core_gclk_mux@1520 {
0850 #clock-cells = <0>;
0851 compatible = "ti,mux-clock";
0852 clock-output-names = "gpu_core_gclk_mux";
0853 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
0854 ti,bit-shift = <24>;
0855 reg = <0x1520>;
0856 };
0857
0858 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 {
0859 #clock-cells = <0>;
0860 compatible = "ti,mux-clock";
0861 clock-output-names = "gpu_hyd_gclk_mux";
0862 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
0863 ti,bit-shift = <25>;
0864 reg = <0x1520>;
0865 };
0866
0867 hsi_fclk: hsi_fclk@1638 {
0868 #clock-cells = <0>;
0869 compatible = "ti,divider-clock";
0870 clock-output-names = "hsi_fclk";
0871 clocks = <&dpll_per_m2x2_ck>;
0872 ti,bit-shift = <24>;
0873 ti,max-div = <2>;
0874 reg = <0x1638>;
0875 };
0876 };
0877
0878 &cm_core_clockdomains {
0879 l3init_clkdm: l3init_clkdm {
0880 compatible = "ti,clockdomain";
0881 clock-output-names = "l3init_clkdm";
0882 clocks = <&dpll_usb_ck>;
0883 };
0884 };
0885
0886 &scrm_clocks {
0887 auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
0888 #clock-cells = <0>;
0889 compatible = "ti,composite-no-wait-gate-clock";
0890 clock-output-names = "auxclk0_src_gate_ck";
0891 clocks = <&dpll_core_m3x2_ck>;
0892 ti,bit-shift = <8>;
0893 reg = <0x0310>;
0894 };
0895
0896 auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
0897 #clock-cells = <0>;
0898 compatible = "ti,composite-mux-clock";
0899 clock-output-names = "auxclk0_src_mux_ck";
0900 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
0901 ti,bit-shift = <1>;
0902 reg = <0x0310>;
0903 };
0904
0905 auxclk0_src_ck: auxclk0_src_ck {
0906 #clock-cells = <0>;
0907 compatible = "ti,composite-clock";
0908 clock-output-names = "auxclk0_src_ck";
0909 clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
0910 };
0911
0912 auxclk0_ck: auxclk0_ck@310 {
0913 #clock-cells = <0>;
0914 compatible = "ti,divider-clock";
0915 clock-output-names = "auxclk0_ck";
0916 clocks = <&auxclk0_src_ck>;
0917 ti,bit-shift = <16>;
0918 ti,max-div = <16>;
0919 reg = <0x0310>;
0920 };
0921
0922 auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
0923 #clock-cells = <0>;
0924 compatible = "ti,composite-no-wait-gate-clock";
0925 clock-output-names = "auxclk1_src_gate_ck";
0926 clocks = <&dpll_core_m3x2_ck>;
0927 ti,bit-shift = <8>;
0928 reg = <0x0314>;
0929 };
0930
0931 auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
0932 #clock-cells = <0>;
0933 compatible = "ti,composite-mux-clock";
0934 clock-output-names = "auxclk1_src_mux_ck";
0935 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
0936 ti,bit-shift = <1>;
0937 reg = <0x0314>;
0938 };
0939
0940 auxclk1_src_ck: auxclk1_src_ck {
0941 #clock-cells = <0>;
0942 compatible = "ti,composite-clock";
0943 clock-output-names = "auxclk1_src_ck";
0944 clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
0945 };
0946
0947 auxclk1_ck: auxclk1_ck@314 {
0948 #clock-cells = <0>;
0949 compatible = "ti,divider-clock";
0950 clock-output-names = "auxclk1_ck";
0951 clocks = <&auxclk1_src_ck>;
0952 ti,bit-shift = <16>;
0953 ti,max-div = <16>;
0954 reg = <0x0314>;
0955 };
0956
0957 auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
0958 #clock-cells = <0>;
0959 compatible = "ti,composite-no-wait-gate-clock";
0960 clock-output-names = "auxclk2_src_gate_ck";
0961 clocks = <&dpll_core_m3x2_ck>;
0962 ti,bit-shift = <8>;
0963 reg = <0x0318>;
0964 };
0965
0966 auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
0967 #clock-cells = <0>;
0968 compatible = "ti,composite-mux-clock";
0969 clock-output-names = "auxclk2_src_mux_ck";
0970 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
0971 ti,bit-shift = <1>;
0972 reg = <0x0318>;
0973 };
0974
0975 auxclk2_src_ck: auxclk2_src_ck {
0976 #clock-cells = <0>;
0977 compatible = "ti,composite-clock";
0978 clock-output-names = "auxclk2_src_ck";
0979 clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
0980 };
0981
0982 auxclk2_ck: auxclk2_ck@318 {
0983 #clock-cells = <0>;
0984 compatible = "ti,divider-clock";
0985 clock-output-names = "auxclk2_ck";
0986 clocks = <&auxclk2_src_ck>;
0987 ti,bit-shift = <16>;
0988 ti,max-div = <16>;
0989 reg = <0x0318>;
0990 };
0991
0992 auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
0993 #clock-cells = <0>;
0994 compatible = "ti,composite-no-wait-gate-clock";
0995 clock-output-names = "auxclk3_src_gate_ck";
0996 clocks = <&dpll_core_m3x2_ck>;
0997 ti,bit-shift = <8>;
0998 reg = <0x031c>;
0999 };
1000
1001 auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
1002 #clock-cells = <0>;
1003 compatible = "ti,composite-mux-clock";
1004 clock-output-names = "auxclk3_src_mux_ck";
1005 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1006 ti,bit-shift = <1>;
1007 reg = <0x031c>;
1008 };
1009
1010 auxclk3_src_ck: auxclk3_src_ck {
1011 #clock-cells = <0>;
1012 compatible = "ti,composite-clock";
1013 clock-output-names = "auxclk3_src_ck";
1014 clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
1015 };
1016
1017 auxclk3_ck: auxclk3_ck@31c {
1018 #clock-cells = <0>;
1019 compatible = "ti,divider-clock";
1020 clock-output-names = "auxclk3_ck";
1021 clocks = <&auxclk3_src_ck>;
1022 ti,bit-shift = <16>;
1023 ti,max-div = <16>;
1024 reg = <0x031c>;
1025 };
1026
1027 auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
1028 #clock-cells = <0>;
1029 compatible = "ti,composite-no-wait-gate-clock";
1030 clock-output-names = "auxclk4_src_gate_ck";
1031 clocks = <&dpll_core_m3x2_ck>;
1032 ti,bit-shift = <8>;
1033 reg = <0x0320>;
1034 };
1035
1036 auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
1037 #clock-cells = <0>;
1038 compatible = "ti,composite-mux-clock";
1039 clock-output-names = "auxclk4_src_mux_ck";
1040 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1041 ti,bit-shift = <1>;
1042 reg = <0x0320>;
1043 };
1044
1045 auxclk4_src_ck: auxclk4_src_ck {
1046 #clock-cells = <0>;
1047 compatible = "ti,composite-clock";
1048 clock-output-names = "auxclk4_src_ck";
1049 clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
1050 };
1051
1052 auxclk4_ck: auxclk4_ck@320 {
1053 #clock-cells = <0>;
1054 compatible = "ti,divider-clock";
1055 clock-output-names = "auxclk4_ck";
1056 clocks = <&auxclk4_src_ck>;
1057 ti,bit-shift = <16>;
1058 ti,max-div = <16>;
1059 reg = <0x0320>;
1060 };
1061
1062 auxclkreq0_ck: auxclkreq0_ck@210 {
1063 #clock-cells = <0>;
1064 compatible = "ti,mux-clock";
1065 clock-output-names = "auxclkreq0_ck";
1066 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1067 ti,bit-shift = <2>;
1068 reg = <0x0210>;
1069 };
1070
1071 auxclkreq1_ck: auxclkreq1_ck@214 {
1072 #clock-cells = <0>;
1073 compatible = "ti,mux-clock";
1074 clock-output-names = "auxclkreq1_ck";
1075 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1076 ti,bit-shift = <2>;
1077 reg = <0x0214>;
1078 };
1079
1080 auxclkreq2_ck: auxclkreq2_ck@218 {
1081 #clock-cells = <0>;
1082 compatible = "ti,mux-clock";
1083 clock-output-names = "auxclkreq2_ck";
1084 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1085 ti,bit-shift = <2>;
1086 reg = <0x0218>;
1087 };
1088
1089 auxclkreq3_ck: auxclkreq3_ck@21c {
1090 #clock-cells = <0>;
1091 compatible = "ti,mux-clock";
1092 clock-output-names = "auxclkreq3_ck";
1093 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1094 ti,bit-shift = <2>;
1095 reg = <0x021c>;
1096 };
1097 };
1098
1099 &cm_core_aon {
1100 mpu_cm: mpu_cm@300 {
1101 compatible = "ti,omap4-cm";
1102 clock-output-names = "mpu_cm";
1103 reg = <0x300 0x100>;
1104 #address-cells = <1>;
1105 #size-cells = <1>;
1106 ranges = <0 0x300 0x100>;
1107
1108 mpu_clkctrl: clk@20 {
1109 compatible = "ti,clkctrl";
1110 clock-output-names = "mpu_clkctrl";
1111 reg = <0x20 0x4>;
1112 #clock-cells = <2>;
1113 };
1114 };
1115
1116 dsp_cm: dsp_cm@400 {
1117 compatible = "ti,omap4-cm";
1118 clock-output-names = "dsp_cm";
1119 reg = <0x400 0x100>;
1120 #address-cells = <1>;
1121 #size-cells = <1>;
1122 ranges = <0 0x400 0x100>;
1123
1124 dsp_clkctrl: clk@20 {
1125 compatible = "ti,clkctrl";
1126 clock-output-names = "dsp_clkctrl";
1127 reg = <0x20 0x4>;
1128 #clock-cells = <2>;
1129 };
1130 };
1131
1132 abe_cm: abe_cm@500 {
1133 compatible = "ti,omap4-cm";
1134 clock-output-names = "abe_cm";
1135 reg = <0x500 0x100>;
1136 #address-cells = <1>;
1137 #size-cells = <1>;
1138 ranges = <0 0x500 0x100>;
1139
1140 abe_clkctrl: clk@20 {
1141 compatible = "ti,clkctrl";
1142 clock-output-names = "abe_clkctrl";
1143 reg = <0x20 0x64>;
1144 #clock-cells = <2>;
1145 };
1146 };
1147
1148 };
1149
1150 &cm_core {
1151 l3main1_cm: l3main1_cm@700 {
1152 compatible = "ti,omap4-cm";
1153 clock-output-names = "l3main1_cm";
1154 reg = <0x700 0x100>;
1155 #address-cells = <1>;
1156 #size-cells = <1>;
1157 ranges = <0 0x700 0x100>;
1158
1159 l3main1_clkctrl: clk@20 {
1160 compatible = "ti,clkctrl";
1161 clock-output-names = "l3main1_clkctrl";
1162 reg = <0x20 0x4>;
1163 #clock-cells = <2>;
1164 };
1165 };
1166
1167 l3main2_cm: l3main2_cm@800 {
1168 compatible = "ti,omap4-cm";
1169 clock-output-names = "l3main2_cm";
1170 reg = <0x800 0x100>;
1171 #address-cells = <1>;
1172 #size-cells = <1>;
1173 ranges = <0 0x800 0x100>;
1174
1175 l3main2_clkctrl: clk@20 {
1176 compatible = "ti,clkctrl";
1177 clock-output-names = "l3main2_clkctrl";
1178 reg = <0x20 0x4>;
1179 #clock-cells = <2>;
1180 };
1181 };
1182
1183 ipu_cm: ipu_cm@900 {
1184 compatible = "ti,omap4-cm";
1185 clock-output-names = "ipu_cm";
1186 reg = <0x900 0x100>;
1187 #address-cells = <1>;
1188 #size-cells = <1>;
1189 ranges = <0 0x900 0x100>;
1190
1191 ipu_clkctrl: clk@20 {
1192 compatible = "ti,clkctrl";
1193 clock-output-names = "ipu_clkctrl";
1194 reg = <0x20 0x4>;
1195 #clock-cells = <2>;
1196 };
1197 };
1198
1199 dma_cm: dma_cm@a00 {
1200 compatible = "ti,omap4-cm";
1201 clock-output-names = "dma_cm";
1202 reg = <0xa00 0x100>;
1203 #address-cells = <1>;
1204 #size-cells = <1>;
1205 ranges = <0 0xa00 0x100>;
1206
1207 dma_clkctrl: clk@20 {
1208 compatible = "ti,clkctrl";
1209 clock-output-names = "dma_clkctrl";
1210 reg = <0x20 0x4>;
1211 #clock-cells = <2>;
1212 };
1213 };
1214
1215 emif_cm: emif_cm@b00 {
1216 compatible = "ti,omap4-cm";
1217 clock-output-names = "emif_cm";
1218 reg = <0xb00 0x100>;
1219 #address-cells = <1>;
1220 #size-cells = <1>;
1221 ranges = <0 0xb00 0x100>;
1222
1223 emif_clkctrl: clk@20 {
1224 compatible = "ti,clkctrl";
1225 clock-output-names = "emif_clkctrl";
1226 reg = <0x20 0x1c>;
1227 #clock-cells = <2>;
1228 };
1229 };
1230
1231 l4cfg_cm: l4cfg_cm@d00 {
1232 compatible = "ti,omap4-cm";
1233 clock-output-names = "l4cfg_cm";
1234 reg = <0xd00 0x100>;
1235 #address-cells = <1>;
1236 #size-cells = <1>;
1237 ranges = <0 0xd00 0x100>;
1238
1239 l4cfg_clkctrl: clk@20 {
1240 compatible = "ti,clkctrl";
1241 clock-output-names = "l4cfg_clkctrl";
1242 reg = <0x20 0x14>;
1243 #clock-cells = <2>;
1244 };
1245 };
1246
1247 l3instr_cm: l3instr_cm@e00 {
1248 compatible = "ti,omap4-cm";
1249 clock-output-names = "l3instr_cm";
1250 reg = <0xe00 0x100>;
1251 #address-cells = <1>;
1252 #size-cells = <1>;
1253 ranges = <0 0xe00 0x100>;
1254
1255 l3instr_clkctrl: clk@20 {
1256 compatible = "ti,clkctrl";
1257 clock-output-names = "l3instr_clkctrl";
1258 reg = <0x20 0xc>;
1259 #clock-cells = <2>;
1260 };
1261 };
1262
1263 l4per_cm: clock@1000 {
1264 compatible = "ti,omap4-cm";
1265 clock-output-names = "l4per_cm";
1266 reg = <0x1000 0x200>;
1267 #address-cells = <1>;
1268 #size-cells = <1>;
1269 ranges = <0 0x1000 0x200>;
1270
1271 l4per_clkctrl: clock@20 {
1272 compatible = "ti,clkctrl";
1273 clock-output-names = "l4per_clkctrl";
1274 reg = <0x20 0x15c>;
1275 #clock-cells = <2>;
1276 };
1277
1278 l4sec_clkctrl: clock@1a0 {
1279 compatible = "ti,clkctrl";
1280 clock-output-names = "l4sec_clkctrl";
1281 reg = <0x1a0 0x3c>;
1282 #clock-cells = <2>;
1283 };
1284 };
1285
1286 dss_cm: dss_cm@1400 {
1287 compatible = "ti,omap4-cm";
1288 clock-output-names = "dss_cm";
1289 reg = <0x1400 0x100>;
1290 #address-cells = <1>;
1291 #size-cells = <1>;
1292 ranges = <0 0x1400 0x100>;
1293
1294 dss_clkctrl: clk@20 {
1295 compatible = "ti,clkctrl";
1296 clock-output-names = "dss_clkctrl";
1297 reg = <0x20 0x4>;
1298 #clock-cells = <2>;
1299 };
1300 };
1301
1302 gpu_cm: gpu_cm@1500 {
1303 compatible = "ti,omap4-cm";
1304 clock-output-names = "gpu_cm";
1305 reg = <0x1500 0x100>;
1306 #address-cells = <1>;
1307 #size-cells = <1>;
1308 ranges = <0 0x1500 0x100>;
1309
1310 gpu_clkctrl: clk@20 {
1311 compatible = "ti,clkctrl";
1312 clock-output-names = "gpu_clkctrl";
1313 reg = <0x20 0x4>;
1314 #clock-cells = <2>;
1315 };
1316 };
1317
1318 l3init_cm: l3init_cm@1600 {
1319 compatible = "ti,omap4-cm";
1320 clock-output-names = "l3init_cm";
1321 reg = <0x1600 0x100>;
1322 #address-cells = <1>;
1323 #size-cells = <1>;
1324 ranges = <0 0x1600 0x100>;
1325
1326 l3init_clkctrl: clk@20 {
1327 compatible = "ti,clkctrl";
1328 clock-output-names = "l3init_clkctrl";
1329 reg = <0x20 0xd4>;
1330 #clock-cells = <2>;
1331 };
1332 };
1333 };
1334
1335 &prm {
1336 wkupaon_cm: wkupaon_cm@1900 {
1337 compatible = "ti,omap4-cm";
1338 clock-output-names = "wkupaon_cm";
1339 reg = <0x1900 0x100>;
1340 #address-cells = <1>;
1341 #size-cells = <1>;
1342 ranges = <0 0x1900 0x100>;
1343
1344 wkupaon_clkctrl: clk@20 {
1345 compatible = "ti,clkctrl";
1346 clock-output-names = "wkupaon_clkctrl";
1347 reg = <0x20 0x5c>;
1348 #clock-cells = <2>;
1349 };
1350 };
1351 };
1352
1353 &scm_wkup_pad_conf_clocks {
1354 fref_xtal_ck: fref_xtal_ck {
1355 #clock-cells = <0>;
1356 compatible = "ti,gate-clock";
1357 clock-output-names = "fref_xtal_ck";
1358 clocks = <&sys_clkin>;
1359 ti,bit-shift = <28>;
1360 reg = <0x14>;
1361 };
1362 };
