0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
0004 *
0005 * Based on "omap4.dtsi"
0006 */
0007
0008 #include <dt-bindings/bus/ti-sysc.h>
0009 #include <dt-bindings/gpio/gpio.h>
0010 #include <dt-bindings/interrupt-controller/arm-gic.h>
0011 #include <dt-bindings/pinctrl/omap.h>
0012 #include <dt-bindings/clock/omap5.h>
0013
0014 / {
0015 #address-cells = <2>;
0016 #size-cells = <2>;
0017
0018 compatible = "ti,omap5";
0019 interrupt-parent = <&wakeupgen>;
0020 chosen { };
0021
0022 aliases {
0023 i2c0 = &i2c1;
0024 i2c1 = &i2c2;
0025 i2c2 = &i2c3;
0026 i2c3 = &i2c4;
0027 i2c4 = &i2c5;
0028 mmc0 = &mmc1;
0029 mmc1 = &mmc2;
0030 mmc2 = &mmc3;
0031 mmc3 = &mmc4;
0032 mmc4 = &mmc5;
0033 serial0 = &uart1;
0034 serial1 = &uart2;
0035 serial2 = &uart3;
0036 serial3 = &uart4;
0037 serial4 = &uart5;
0038 serial5 = &uart6;
0039 rproc0 = &dsp;
0040 rproc1 = &ipu;
0041 };
0042
0043 cpus {
0044 #address-cells = <1>;
0045 #size-cells = <0>;
0046
0047 cpu0: cpu@0 {
0048 device_type = "cpu";
0049 compatible = "arm,cortex-a15";
0050 reg = <0x0>;
0051
0052 operating-points = <
0053 /* kHz uV */
0054 1000000 1060000
0055 1500000 1250000
0056 >;
0057
0058 clocks = <&dpll_mpu_ck>;
0059 clock-names = "cpu";
0060
0061 clock-latency = <300000>; /* From omap-cpufreq driver */
0062
0063 /* cooling options */
0064 #cooling-cells = <2>; /* min followed by max */
0065 };
0066 cpu@1 {
0067 device_type = "cpu";
0068 compatible = "arm,cortex-a15";
0069 reg = <0x1>;
0070
0071 operating-points = <
0072 /* kHz uV */
0073 1000000 1060000
0074 1500000 1250000
0075 >;
0076
0077 clocks = <&dpll_mpu_ck>;
0078 clock-names = "cpu";
0079
0080 clock-latency = <300000>; /* From omap-cpufreq driver */
0081
0082 /* cooling options */
0083 #cooling-cells = <2>; /* min followed by max */
0084 };
0085 };
0086
0087 thermal-zones {
0088 #include "omap4-cpu-thermal.dtsi"
0089 #include "omap5-gpu-thermal.dtsi"
0090 #include "omap5-core-thermal.dtsi"
0091 };
0092
0093 timer {
0094 compatible = "arm,armv7-timer";
0095 /* PPI secure/nonsecure IRQ */
0096 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
0097 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
0098 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
0099 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
0100 interrupt-parent = <&gic>;
0101 };
0102
0103 pmu {
0104 compatible = "arm,cortex-a15-pmu";
0105 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
0106 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
0107 };
0108
0109 /*
0110 * Needed early by omap4_sram_init() for barrier, do not move to l3
0111 * interconnect as simple-pm-bus probes at module_init() time.
0112 */
0113 ocmcram: sram@40300000 {
0114 compatible = "mmio-sram";
0115 reg = <0 0x40300000 0 0x20000>; /* 128k */
0116 };
0117
0118 gic: interrupt-controller@48211000 {
0119 compatible = "arm,cortex-a15-gic";
0120 interrupt-controller;
0121 #interrupt-cells = <3>;
0122 reg = <0 0x48211000 0 0x1000>,
0123 <0 0x48212000 0 0x2000>,
0124 <0 0x48214000 0 0x2000>,
0125 <0 0x48216000 0 0x2000>;
0126 interrupt-parent = <&gic>;
0127 };
0128
0129 wakeupgen: interrupt-controller@48281000 {
0130 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
0131 interrupt-controller;
0132 #interrupt-cells = <3>;
0133 reg = <0 0x48281000 0 0x1000>;
0134 interrupt-parent = <&gic>;
0135 };
0136
0137 /*
0138 * XXX: Use a flat representation of the OMAP3 interconnect.
0139 * The real OMAP interconnect network is quite complex.
0140 * Since it will not bring real advantage to represent that in DT for
0141 * the moment, just use a fake OCP bus entry to represent the whole bus
0142 * hierarchy.
0143 */
0144 ocp {
0145 compatible = "simple-pm-bus";
0146 power-domains = <&prm_core>;
0147 clocks = <&l3main1_clkctrl OMAP5_L3_MAIN_1_CLKCTRL 0>,
0148 <&l3main2_clkctrl OMAP5_L3_MAIN_2_CLKCTRL 0>,
0149 <&l3instr_clkctrl OMAP5_L3_MAIN_3_CLKCTRL 0>;
0150 #address-cells = <1>;
0151 #size-cells = <1>;
0152 ranges = <0 0 0 0xc0000000>;
0153 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
0154
0155 l3-noc@44000000 {
0156 compatible = "ti,omap5-l3-noc";
0157 reg = <0x44000000 0x2000>,
0158 <0x44800000 0x3000>,
0159 <0x45000000 0x4000>;
0160 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0161 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0162 };
0163
0164 l4_wkup: interconnect@4ae00000 {
0165 };
0166
0167 l4_cfg: interconnect@4a000000 {
0168 };
0169
0170 l4_per: interconnect@48000000 {
0171 };
0172
0173 target-module@48210000 {
0174 compatible = "ti,sysc-omap4-simple", "ti,sysc";
0175 power-domains = <&prm_mpu>;
0176 clocks = <&mpu_clkctrl OMAP5_MPU_CLKCTRL 0>;
0177 clock-names = "fck";
0178 #address-cells = <1>;
0179 #size-cells = <1>;
0180 ranges = <0 0x48210000 0x1f0000>;
0181
0182 mpu {
0183 compatible = "ti,omap4-mpu";
0184 sram = <&ocmcram>;
0185 };
0186 };
0187
0188 l4_abe: interconnect@40100000 {
0189 };
0190
0191 target-module@50000000 {
0192 compatible = "ti,sysc-omap2", "ti,sysc";
0193 reg = <0x50000000 4>,
0194 <0x50000010 4>,
0195 <0x50000014 4>;
0196 reg-names = "rev", "sysc", "syss";
0197 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0198 <SYSC_IDLE_NO>,
0199 <SYSC_IDLE_SMART>;
0200 ti,syss-mask = <1>;
0201 ti,no-idle-on-init;
0202 clocks = <&l3main2_clkctrl OMAP5_L3_MAIN_2_GPMC_CLKCTRL 0>;
0203 clock-names = "fck";
0204 #address-cells = <1>;
0205 #size-cells = <1>;
0206 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
0207 <0x00000000 0x00000000 0x40000000>; /* data */
0208
0209 gpmc: gpmc@50000000 {
0210 compatible = "ti,omap4430-gpmc";
0211 reg = <0x50000000 0x1000>;
0212 #address-cells = <2>;
0213 #size-cells = <1>;
0214 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0215 dmas = <&sdma 4>;
0216 dma-names = "rxtx";
0217 gpmc,num-cs = <8>;
0218 gpmc,num-waitpins = <4>;
0219 clock-names = "fck";
0220 interrupt-controller;
0221 #interrupt-cells = <2>;
0222 gpio-controller;
0223 #gpio-cells = <2>;
0224 };
0225 };
0226
0227 target-module@55082000 {
0228 compatible = "ti,sysc-omap2", "ti,sysc";
0229 reg = <0x55082000 0x4>,
0230 <0x55082010 0x4>,
0231 <0x55082014 0x4>;
0232 reg-names = "rev", "sysc", "syss";
0233 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0234 <SYSC_IDLE_NO>,
0235 <SYSC_IDLE_SMART>;
0236 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0237 SYSC_OMAP2_SOFTRESET |
0238 SYSC_OMAP2_AUTOIDLE)>;
0239 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
0240 clock-names = "fck";
0241 resets = <&prm_core 2>;
0242 reset-names = "rstctrl";
0243 ranges = <0x0 0x55082000 0x100>;
0244 #size-cells = <1>;
0245 #address-cells = <1>;
0246
0247 mmu_ipu: mmu@0 {
0248 compatible = "ti,omap4-iommu";
0249 reg = <0x0 0x100>;
0250 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0251 #iommu-cells = <0>;
0252 ti,iommu-bus-err-back;
0253 };
0254 };
0255
0256 dsp: dsp {
0257 compatible = "ti,omap5-dsp";
0258 ti,bootreg = <&scm_conf 0x304 0>;
0259 iommus = <&mmu_dsp>;
0260 resets = <&prm_dsp 0>;
0261 clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
0262 firmware-name = "omap5-dsp-fw.xe64T";
0263 mboxes = <&mailbox &mbox_dsp>;
0264 status = "disabled";
0265 };
0266
0267 ipu: ipu@55020000 {
0268 compatible = "ti,omap5-ipu";
0269 reg = <0x55020000 0x10000>;
0270 reg-names = "l2ram";
0271 iommus = <&mmu_ipu>;
0272 resets = <&prm_core 0>, <&prm_core 1>;
0273 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
0274 firmware-name = "omap5-ipu-fw.xem4";
0275 mboxes = <&mailbox &mbox_ipu>;
0276 status = "disabled";
0277 };
0278
0279 target-module@4e000000 {
0280 compatible = "ti,sysc-omap2", "ti,sysc";
0281 reg = <0x4e000000 0x4>,
0282 <0x4e000010 0x4>;
0283 reg-names = "rev", "sysc";
0284 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0285 <SYSC_IDLE_NO>,
0286 <SYSC_IDLE_SMART>;
0287 ranges = <0x0 0x4e000000 0x2000000>;
0288 #size-cells = <1>;
0289 #address-cells = <1>;
0290
0291 dmm@0 {
0292 compatible = "ti,omap5-dmm";
0293 reg = <0 0x800>;
0294 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
0295 };
0296 };
0297
0298 target-module@4c000000 {
0299 compatible = "ti,sysc-omap4-simple", "ti,sysc";
0300 reg = <0x4c000000 0x4>;
0301 reg-names = "rev";
0302 clocks = <&emif_clkctrl OMAP5_EMIF1_CLKCTRL 0>;
0303 clock-names = "fck";
0304 ti,no-idle;
0305 #address-cells = <1>;
0306 #size-cells = <1>;
0307 ranges = <0x0 0x4c000000 0x1000000>;
0308
0309 emif1: emif@0 {
0310 compatible = "ti,emif-4d5";
0311 reg = <0 0x400>;
0312 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0313 phy-type = <2>; /* DDR PHY type: Intelli PHY */
0314 hw-caps-read-idle-ctrl;
0315 hw-caps-ll-interface;
0316 hw-caps-temp-alert;
0317 };
0318 };
0319
0320 target-module@4d000000 {
0321 compatible = "ti,sysc-omap4-simple", "ti,sysc";
0322 reg = <0x4d000000 0x4>;
0323 reg-names = "rev";
0324 clocks = <&emif_clkctrl OMAP5_EMIF2_CLKCTRL 0>;
0325 clock-names = "fck";
0326 ti,no-idle;
0327 #address-cells = <1>;
0328 #size-cells = <1>;
0329 ranges = <0x0 0x4d000000 0x1000000>;
0330
0331 emif2: emif@0 {
0332 compatible = "ti,emif-4d5";
0333 reg = <0 0x400>;
0334 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
0335 phy-type = <2>; /* DDR PHY type: Intelli PHY */
0336 hw-caps-read-idle-ctrl;
0337 hw-caps-ll-interface;
0338 hw-caps-temp-alert;
0339 };
0340 };
0341
0342 aes1_target: target-module@4b501000 {
0343 compatible = "ti,sysc-omap2", "ti,sysc";
0344 reg = <0x4b501080 0x4>,
0345 <0x4b501084 0x4>,
0346 <0x4b501088 0x4>;
0347 reg-names = "rev", "sysc", "syss";
0348 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
0349 SYSC_OMAP2_AUTOIDLE)>;
0350 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0351 <SYSC_IDLE_NO>,
0352 <SYSC_IDLE_SMART>,
0353 <SYSC_IDLE_SMART_WKUP>;
0354 ti,syss-mask = <1>;
0355 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
0356 clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>;
0357 clock-names = "fck";
0358 #address-cells = <1>;
0359 #size-cells = <1>;
0360 ranges = <0x0 0x4b501000 0x1000>;
0361
0362 aes1: aes@0 {
0363 compatible = "ti,omap4-aes";
0364 reg = <0 0xa0>;
0365 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0366 dmas = <&sdma 111>, <&sdma 110>;
0367 dma-names = "tx", "rx";
0368 };
0369 };
0370
0371 aes2_target: target-module@4b701000 {
0372 compatible = "ti,sysc-omap2", "ti,sysc";
0373 reg = <0x4b701080 0x4>,
0374 <0x4b701084 0x4>,
0375 <0x4b701088 0x4>;
0376 reg-names = "rev", "sysc", "syss";
0377 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
0378 SYSC_OMAP2_AUTOIDLE)>;
0379 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0380 <SYSC_IDLE_NO>,
0381 <SYSC_IDLE_SMART>,
0382 <SYSC_IDLE_SMART_WKUP>;
0383 ti,syss-mask = <1>;
0384 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
0385 clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>;
0386 clock-names = "fck";
0387 #address-cells = <1>;
0388 #size-cells = <1>;
0389 ranges = <0x0 0x4b701000 0x1000>;
0390
0391 aes2: aes@0 {
0392 compatible = "ti,omap4-aes";
0393 reg = <0 0xa0>;
0394 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
0395 dmas = <&sdma 114>, <&sdma 113>;
0396 dma-names = "tx", "rx";
0397 };
0398 };
0399
0400 sham_target: target-module@4b100000 {
0401 compatible = "ti,sysc-omap3-sham", "ti,sysc";
0402 reg = <0x4b100100 0x4>,
0403 <0x4b100110 0x4>,
0404 <0x4b100114 0x4>;
0405 reg-names = "rev", "sysc", "syss";
0406 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
0407 SYSC_OMAP2_AUTOIDLE)>;
0408 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0409 <SYSC_IDLE_NO>,
0410 <SYSC_IDLE_SMART>;
0411 ti,syss-mask = <1>;
0412 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
0413 clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>;
0414 clock-names = "fck";
0415 #address-cells = <1>;
0416 #size-cells = <1>;
0417 ranges = <0x0 0x4b100000 0x1000>;
0418
0419 sham: sham@0 {
0420 compatible = "ti,omap4-sham";
0421 reg = <0 0x300>;
0422 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0423 dmas = <&sdma 119>;
0424 dma-names = "rx";
0425 };
0426 };
0427
0428 bandgap: bandgap@4a0021e0 {
0429 reg = <0x4a0021e0 0xc
0430 0x4a00232c 0xc
0431 0x4a002380 0x2c
0432 0x4a0023C0 0x3c>;
0433 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
0434 compatible = "ti,omap5430-bandgap";
0435
0436 #thermal-sensor-cells = <1>;
0437 };
0438
0439 target-module@56000000 {
0440 compatible = "ti,sysc-omap4", "ti,sysc";
0441 reg = <0x5600fe00 0x4>,
0442 <0x5600fe10 0x4>;
0443 reg-names = "rev", "sysc";
0444 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0445 <SYSC_IDLE_NO>,
0446 <SYSC_IDLE_SMART>;
0447 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0448 <SYSC_IDLE_NO>,
0449 <SYSC_IDLE_SMART>;
0450 clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
0451 clock-names = "fck";
0452 #address-cells = <1>;
0453 #size-cells = <1>;
0454 ranges = <0 0x56000000 0x2000000>;
0455
0456 /*
0457 * Closed source PowerVR driver, no child device
0458 * binding or driver in mainline
0459 */
0460 };
0461
0462 target-module@58000000 {
0463 compatible = "ti,sysc-omap2", "ti,sysc";
0464 reg = <0x58000000 4>,
0465 <0x58000014 4>;
0466 reg-names = "rev", "syss";
0467 ti,syss-mask = <1>;
0468 power-domains = <&prm_dss>;
0469 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
0470 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
0471 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
0472 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
0473 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
0474 #address-cells = <1>;
0475 #size-cells = <1>;
0476 ranges = <0 0x58000000 0x1000000>;
0477
0478 dss: dss@0 {
0479 compatible = "ti,omap5-dss";
0480 reg = <0 0x80>;
0481 status = "disabled";
0482 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
0483 clock-names = "fck";
0484 #address-cells = <1>;
0485 #size-cells = <1>;
0486 ranges = <0 0 0x1000000>;
0487
0488 target-module@1000 {
0489 compatible = "ti,sysc-omap2", "ti,sysc";
0490 reg = <0x1000 0x4>,
0491 <0x1010 0x4>,
0492 <0x1014 0x4>;
0493 reg-names = "rev", "sysc", "syss";
0494 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0495 <SYSC_IDLE_NO>,
0496 <SYSC_IDLE_SMART>;
0497 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0498 <SYSC_IDLE_NO>,
0499 <SYSC_IDLE_SMART>;
0500 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0501 SYSC_OMAP2_ENAWAKEUP |
0502 SYSC_OMAP2_SOFTRESET |
0503 SYSC_OMAP2_AUTOIDLE)>;
0504 ti,syss-mask = <1>;
0505 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
0506 clock-names = "fck";
0507 #address-cells = <1>;
0508 #size-cells = <1>;
0509 ranges = <0 0x1000 0x1000>;
0510
0511 dispc@0 {
0512 compatible = "ti,omap5-dispc";
0513 reg = <0 0x1000>;
0514 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0515 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
0516 clock-names = "fck";
0517 };
0518 };
0519
0520 target-module@2000 {
0521 compatible = "ti,sysc-omap2", "ti,sysc";
0522 reg = <0x2000 0x4>,
0523 <0x2010 0x4>,
0524 <0x2014 0x4>;
0525 reg-names = "rev", "sysc", "syss";
0526 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0527 <SYSC_IDLE_NO>,
0528 <SYSC_IDLE_SMART>;
0529 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
0530 SYSC_OMAP2_AUTOIDLE)>;
0531 ti,syss-mask = <1>;
0532 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
0533 clock-names = "fck";
0534 #address-cells = <1>;
0535 #size-cells = <1>;
0536 ranges = <0 0x2000 0x1000>;
0537
0538 rfbi: encoder@0 {
0539 compatible = "ti,omap5-rfbi";
0540 reg = <0 0x100>;
0541 status = "disabled";
0542 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
0543 clock-names = "fck", "ick";
0544 };
0545 };
0546
0547 target-module@4000 {
0548 compatible = "ti,sysc-omap2", "ti,sysc";
0549 reg = <0x4000 0x4>,
0550 <0x4010 0x4>,
0551 <0x4014 0x4>;
0552 reg-names = "rev", "sysc", "syss";
0553 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0554 <SYSC_IDLE_NO>,
0555 <SYSC_IDLE_SMART>;
0556 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0557 SYSC_OMAP2_ENAWAKEUP |
0558 SYSC_OMAP2_SOFTRESET |
0559 SYSC_OMAP2_AUTOIDLE)>;
0560 ti,syss-mask = <1>;
0561 #address-cells = <1>;
0562 #size-cells = <1>;
0563 ranges = <0 0x4000 0x1000>;
0564
0565 dsi1: encoder@0 {
0566 compatible = "ti,omap5-dsi";
0567 reg = <0 0x200>,
0568 <0x200 0x40>,
0569 <0x300 0x40>;
0570 reg-names = "proto", "phy", "pll";
0571 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0572 status = "disabled";
0573 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
0574 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
0575 clock-names = "fck", "sys_clk";
0576
0577 #address-cells = <1>;
0578 #size-cells = <0>;
0579 };
0580 };
0581
0582 target-module@9000 {
0583 compatible = "ti,sysc-omap2", "ti,sysc";
0584 reg = <0x9000 0x4>,
0585 <0x9010 0x4>,
0586 <0x9014 0x4>;
0587 reg-names = "rev", "sysc", "syss";
0588 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0589 <SYSC_IDLE_NO>,
0590 <SYSC_IDLE_SMART>;
0591 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0592 SYSC_OMAP2_ENAWAKEUP |
0593 SYSC_OMAP2_SOFTRESET |
0594 SYSC_OMAP2_AUTOIDLE)>;
0595 ti,syss-mask = <1>;
0596 #address-cells = <1>;
0597 #size-cells = <1>;
0598 ranges = <0 0x9000 0x1000>;
0599
0600 dsi2: encoder@0 {
0601 compatible = "ti,omap5-dsi";
0602 reg = <0 0x200>,
0603 <0x200 0x40>,
0604 <0x300 0x40>;
0605 reg-names = "proto", "phy", "pll";
0606 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0607 status = "disabled";
0608 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
0609 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
0610 clock-names = "fck", "sys_clk";
0611
0612 #address-cells = <1>;
0613 #size-cells = <0>;
0614 };
0615 };
0616
0617 target-module@40000 {
0618 compatible = "ti,sysc-omap4", "ti,sysc";
0619 reg = <0x40000 0x4>,
0620 <0x40010 0x4>;
0621 reg-names = "rev", "sysc";
0622 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0623 <SYSC_IDLE_NO>,
0624 <SYSC_IDLE_SMART>,
0625 <SYSC_IDLE_SMART_WKUP>;
0626 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
0627 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
0628 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
0629 clock-names = "fck", "dss_clk";
0630 #address-cells = <1>;
0631 #size-cells = <1>;
0632 ranges = <0 0x40000 0x40000>;
0633
0634 hdmi: encoder@0 {
0635 compatible = "ti,omap5-hdmi";
0636 reg = <0 0x200>,
0637 <0x200 0x80>,
0638 <0x300 0x80>,
0639 <0x20000 0x19000>;
0640 reg-names = "wp", "pll", "phy", "core";
0641 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
0642 status = "disabled";
0643 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
0644 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
0645 clock-names = "fck", "sys_clk";
0646 dmas = <&sdma 76>;
0647 dma-names = "audio_tx";
0648 };
0649 };
0650 };
0651 };
0652
0653 abb_mpu: regulator-abb-mpu {
0654 compatible = "ti,abb-v2";
0655 regulator-name = "abb_mpu";
0656 #address-cells = <0>;
0657 #size-cells = <0>;
0658 clocks = <&sys_clkin>;
0659 ti,settling-time = <50>;
0660 ti,clock-cycles = <16>;
0661
0662 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
0663 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
0664 reg-names = "base-address", "int-address",
0665 "efuse-address", "ldo-address";
0666 ti,tranxdone-status-mask = <0x80>;
0667 /* LDOVBBMPU_MUX_CTRL */
0668 ti,ldovbb-override-mask = <0x400>;
0669 /* LDOVBBMPU_VSET_OUT */
0670 ti,ldovbb-vset-mask = <0x1F>;
0671
0672 /*
0673 * NOTE: only FBB mode used but actual vset will
0674 * determine final biasing
0675 */
0676 ti,abb_info = <
0677 /*uV ABB efuse rbb_m fbb_m vset_m*/
0678 1060000 0 0x0 0 0x02000000 0x01F00000
0679 1250000 0 0x4 0 0x02000000 0x01F00000
0680 >;
0681 };
0682
0683 abb_mm: regulator-abb-mm {
0684 compatible = "ti,abb-v2";
0685 regulator-name = "abb_mm";
0686 #address-cells = <0>;
0687 #size-cells = <0>;
0688 clocks = <&sys_clkin>;
0689 ti,settling-time = <50>;
0690 ti,clock-cycles = <16>;
0691
0692 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
0693 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
0694 reg-names = "base-address", "int-address",
0695 "efuse-address", "ldo-address";
0696 ti,tranxdone-status-mask = <0x80000000>;
0697 /* LDOVBBMM_MUX_CTRL */
0698 ti,ldovbb-override-mask = <0x400>;
0699 /* LDOVBBMM_VSET_OUT */
0700 ti,ldovbb-vset-mask = <0x1F>;
0701
0702 /*
0703 * NOTE: only FBB mode used but actual vset will
0704 * determine final biasing
0705 */
0706 ti,abb_info = <
0707 /*uV ABB efuse rbb_m fbb_m vset_m*/
0708 1025000 0 0x0 0 0x02000000 0x01F00000
0709 1120000 0 0x4 0 0x02000000 0x01F00000
0710 >;
0711 };
0712 };
0713 };
0714
0715 &cpu_thermal {
0716 polling-delay = <500>; /* milliseconds */
0717 coefficients = <65 (-1791)>;
0718 };
0719
0720 #include "omap5-l4.dtsi"
0721 #include "omap54xx-clocks.dtsi"
0722
0723 &gpu_thermal {
0724 coefficients = <117 (-2992)>;
0725 };
0726
0727 &core_thermal {
0728 coefficients = <0 2000>;
0729 };
0730
0731 #include "omap5-l4-abe.dtsi"
0732 #include "omap54xx-clocks.dtsi"
0733
0734 &prm {
0735 prm_mpu: prm@300 {
0736 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
0737 reg = <0x300 0x100>;
0738 #power-domain-cells = <0>;
0739 };
0740
0741 prm_dsp: prm@400 {
0742 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
0743 reg = <0x400 0x100>;
0744 #reset-cells = <1>;
0745 #power-domain-cells = <0>;
0746 };
0747
0748 prm_abe: prm@500 {
0749 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
0750 reg = <0x500 0x100>;
0751 #power-domain-cells = <0>;
0752 };
0753
0754 prm_coreaon: prm@600 {
0755 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
0756 reg = <0x600 0x100>;
0757 #power-domain-cells = <0>;
0758 };
0759
0760 prm_core: prm@700 {
0761 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
0762 reg = <0x700 0x100>;
0763 #reset-cells = <1>;
0764 #power-domain-cells = <0>;
0765 };
0766
0767 prm_iva: prm@1200 {
0768 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
0769 reg = <0x1200 0x100>;
0770 #reset-cells = <1>;
0771 #power-domain-cells = <0>;
0772 };
0773
0774 prm_cam: prm@1300 {
0775 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
0776 reg = <0x1300 0x100>;
0777 #power-domain-cells = <0>;
0778 };
0779
0780 prm_dss: prm@1400 {
0781 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
0782 reg = <0x1400 0x100>;
0783 #power-domain-cells = <0>;
0784 };
0785
0786 prm_gpu: prm@1500 {
0787 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
0788 reg = <0x1500 0x100>;
0789 #power-domain-cells = <0>;
0790 };
0791
0792 prm_l3init: prm@1600 {
0793 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
0794 reg = <0x1600 0x100>;
0795 #power-domain-cells = <0>;
0796 };
0797
0798 prm_custefuse: prm@1700 {
0799 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
0800 reg = <0x1700 0x100>;
0801 #power-domain-cells = <0>;
0802 };
0803
0804 prm_wkupaon: prm@1800 {
0805 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
0806 reg = <0x1800 0x100>;
0807 #power-domain-cells = <0>;
0808 };
0809
0810 prm_emu: prm@1a00 {
0811 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
0812 reg = <0x1a00 0x100>;
0813 #power-domain-cells = <0>;
0814 };
0815
0816 prm_device: prm@1c00 {
0817 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
0818 reg = <0x1c00 0x100>;
0819 #reset-cells = <1>;
0820 };
0821 };
0822
0823 /* Preferred always-on timer for clockevent */
0824 &timer1_target {
0825 ti,no-reset-on-init;
0826 ti,no-idle;
0827 timer@0 {
0828 assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
0829 assigned-clock-parents = <&sys_32k_ck>;
0830 };
0831 };
