0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for OMAP4 clock data
0004 *
0005 * Copyright (C) 2013 Texas Instruments, Inc.
0006 */
0007 &cm1_clocks {
0008 extalt_clkin_ck: extalt_clkin_ck {
0009 #clock-cells = <0>;
0010 compatible = "fixed-clock";
0011 clock-output-names = "extalt_clkin_ck";
0012 clock-frequency = <59000000>;
0013 };
0014
0015 pad_clks_src_ck: pad_clks_src_ck {
0016 #clock-cells = <0>;
0017 compatible = "fixed-clock";
0018 clock-output-names = "pad_clks_src_ck";
0019 clock-frequency = <12000000>;
0020 };
0021
0022 pad_clks_ck: pad_clks_ck@108 {
0023 #clock-cells = <0>;
0024 compatible = "ti,gate-clock";
0025 clock-output-names = "pad_clks_ck";
0026 clocks = <&pad_clks_src_ck>;
0027 ti,bit-shift = <8>;
0028 reg = <0x0108>;
0029 };
0030
0031 pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
0032 #clock-cells = <0>;
0033 compatible = "fixed-clock";
0034 clock-output-names = "pad_slimbus_core_clks_ck";
0035 clock-frequency = <12000000>;
0036 };
0037
0038 secure_32k_clk_src_ck: secure_32k_clk_src_ck {
0039 #clock-cells = <0>;
0040 compatible = "fixed-clock";
0041 clock-output-names = "secure_32k_clk_src_ck";
0042 clock-frequency = <32768>;
0043 };
0044
0045 slimbus_src_clk: slimbus_src_clk {
0046 #clock-cells = <0>;
0047 compatible = "fixed-clock";
0048 clock-output-names = "slimbus_src_clk";
0049 clock-frequency = <12000000>;
0050 };
0051
0052 slimbus_clk: slimbus_clk@108 {
0053 #clock-cells = <0>;
0054 compatible = "ti,gate-clock";
0055 clock-output-names = "slimbus_clk";
0056 clocks = <&slimbus_src_clk>;
0057 ti,bit-shift = <10>;
0058 reg = <0x0108>;
0059 };
0060
0061 sys_32k_ck: sys_32k_ck {
0062 #clock-cells = <0>;
0063 compatible = "fixed-clock";
0064 clock-output-names = "sys_32k_ck";
0065 clock-frequency = <32768>;
0066 };
0067
0068 virt_12000000_ck: virt_12000000_ck {
0069 #clock-cells = <0>;
0070 compatible = "fixed-clock";
0071 clock-output-names = "virt_12000000_ck";
0072 clock-frequency = <12000000>;
0073 };
0074
0075 virt_13000000_ck: virt_13000000_ck {
0076 #clock-cells = <0>;
0077 compatible = "fixed-clock";
0078 clock-output-names = "virt_13000000_ck";
0079 clock-frequency = <13000000>;
0080 };
0081
0082 virt_16800000_ck: virt_16800000_ck {
0083 #clock-cells = <0>;
0084 compatible = "fixed-clock";
0085 clock-output-names = "virt_16800000_ck";
0086 clock-frequency = <16800000>;
0087 };
0088
0089 virt_19200000_ck: virt_19200000_ck {
0090 #clock-cells = <0>;
0091 compatible = "fixed-clock";
0092 clock-output-names = "virt_19200000_ck";
0093 clock-frequency = <19200000>;
0094 };
0095
0096 virt_26000000_ck: virt_26000000_ck {
0097 #clock-cells = <0>;
0098 compatible = "fixed-clock";
0099 clock-output-names = "virt_26000000_ck";
0100 clock-frequency = <26000000>;
0101 };
0102
0103 virt_27000000_ck: virt_27000000_ck {
0104 #clock-cells = <0>;
0105 compatible = "fixed-clock";
0106 clock-output-names = "virt_27000000_ck";
0107 clock-frequency = <27000000>;
0108 };
0109
0110 virt_38400000_ck: virt_38400000_ck {
0111 #clock-cells = <0>;
0112 compatible = "fixed-clock";
0113 clock-output-names = "virt_38400000_ck";
0114 clock-frequency = <38400000>;
0115 };
0116
0117 tie_low_clock_ck: tie_low_clock_ck {
0118 #clock-cells = <0>;
0119 compatible = "fixed-clock";
0120 clock-output-names = "tie_low_clock_ck";
0121 clock-frequency = <0>;
0122 };
0123
0124 utmi_phy_clkout_ck: utmi_phy_clkout_ck {
0125 #clock-cells = <0>;
0126 compatible = "fixed-clock";
0127 clock-output-names = "utmi_phy_clkout_ck";
0128 clock-frequency = <60000000>;
0129 };
0130
0131 xclk60mhsp1_ck: xclk60mhsp1_ck {
0132 #clock-cells = <0>;
0133 compatible = "fixed-clock";
0134 clock-output-names = "xclk60mhsp1_ck";
0135 clock-frequency = <60000000>;
0136 };
0137
0138 xclk60mhsp2_ck: xclk60mhsp2_ck {
0139 #clock-cells = <0>;
0140 compatible = "fixed-clock";
0141 clock-output-names = "xclk60mhsp2_ck";
0142 clock-frequency = <60000000>;
0143 };
0144
0145 xclk60motg_ck: xclk60motg_ck {
0146 #clock-cells = <0>;
0147 compatible = "fixed-clock";
0148 clock-output-names = "xclk60motg_ck";
0149 clock-frequency = <60000000>;
0150 };
0151
0152 dpll_abe_ck: dpll_abe_ck@1e0 {
0153 #clock-cells = <0>;
0154 compatible = "ti,omap4-dpll-m4xen-clock";
0155 clock-output-names = "dpll_abe_ck";
0156 clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
0157 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
0158 };
0159
0160 dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 {
0161 #clock-cells = <0>;
0162 compatible = "ti,omap4-dpll-x2-clock";
0163 clock-output-names = "dpll_abe_x2_ck";
0164 clocks = <&dpll_abe_ck>;
0165 reg = <0x01f0>;
0166 };
0167
0168 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
0169 #clock-cells = <0>;
0170 compatible = "ti,divider-clock";
0171 clock-output-names = "dpll_abe_m2x2_ck";
0172 clocks = <&dpll_abe_x2_ck>;
0173 ti,max-div = <31>;
0174 ti,autoidle-shift = <8>;
0175 reg = <0x01f0>;
0176 ti,index-starts-at-one;
0177 ti,invert-autoidle-bit;
0178 };
0179
0180 abe_24m_fclk: abe_24m_fclk {
0181 #clock-cells = <0>;
0182 compatible = "fixed-factor-clock";
0183 clock-output-names = "abe_24m_fclk";
0184 clocks = <&dpll_abe_m2x2_ck>;
0185 clock-mult = <1>;
0186 clock-div = <8>;
0187 };
0188
0189 abe_clk: abe_clk@108 {
0190 #clock-cells = <0>;
0191 compatible = "ti,divider-clock";
0192 clock-output-names = "abe_clk";
0193 clocks = <&dpll_abe_m2x2_ck>;
0194 ti,max-div = <4>;
0195 reg = <0x0108>;
0196 ti,index-power-of-two;
0197 };
0198
0199
0200 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
0201 #clock-cells = <0>;
0202 compatible = "ti,divider-clock";
0203 clock-output-names = "dpll_abe_m3x2_ck";
0204 clocks = <&dpll_abe_x2_ck>;
0205 ti,max-div = <31>;
0206 ti,autoidle-shift = <8>;
0207 reg = <0x01f4>;
0208 ti,index-starts-at-one;
0209 ti,invert-autoidle-bit;
0210 };
0211
0212 core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c {
0213 #clock-cells = <0>;
0214 compatible = "ti,mux-clock";
0215 clock-output-names = "core_hsd_byp_clk_mux_ck";
0216 clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
0217 ti,bit-shift = <23>;
0218 reg = <0x012c>;
0219 };
0220
0221 dpll_core_ck: dpll_core_ck@120 {
0222 #clock-cells = <0>;
0223 compatible = "ti,omap4-dpll-core-clock";
0224 clock-output-names = "dpll_core_ck";
0225 clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
0226 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
0227 };
0228
0229 dpll_core_x2_ck: dpll_core_x2_ck {
0230 #clock-cells = <0>;
0231 compatible = "ti,omap4-dpll-x2-clock";
0232 clock-output-names = "dpll_core_x2_ck";
0233 clocks = <&dpll_core_ck>;
0234 };
0235
0236 dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 {
0237 #clock-cells = <0>;
0238 compatible = "ti,divider-clock";
0239 clock-output-names = "dpll_core_m6x2_ck";
0240 clocks = <&dpll_core_x2_ck>;
0241 ti,max-div = <31>;
0242 ti,autoidle-shift = <8>;
0243 reg = <0x0140>;
0244 ti,index-starts-at-one;
0245 ti,invert-autoidle-bit;
0246 };
0247
0248 dpll_core_m2_ck: dpll_core_m2_ck@130 {
0249 #clock-cells = <0>;
0250 compatible = "ti,divider-clock";
0251 clock-output-names = "dpll_core_m2_ck";
0252 clocks = <&dpll_core_ck>;
0253 ti,max-div = <31>;
0254 ti,autoidle-shift = <8>;
0255 reg = <0x0130>;
0256 ti,index-starts-at-one;
0257 ti,invert-autoidle-bit;
0258 };
0259
0260 ddrphy_ck: ddrphy_ck {
0261 #clock-cells = <0>;
0262 compatible = "fixed-factor-clock";
0263 clock-output-names = "ddrphy_ck";
0264 clocks = <&dpll_core_m2_ck>;
0265 clock-mult = <1>;
0266 clock-div = <2>;
0267 };
0268
0269 dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c {
0270 #clock-cells = <0>;
0271 compatible = "ti,divider-clock";
0272 clock-output-names = "dpll_core_m5x2_ck";
0273 clocks = <&dpll_core_x2_ck>;
0274 ti,max-div = <31>;
0275 ti,autoidle-shift = <8>;
0276 reg = <0x013c>;
0277 ti,index-starts-at-one;
0278 ti,invert-autoidle-bit;
0279 };
0280
0281 div_core_ck: div_core_ck@100 {
0282 #clock-cells = <0>;
0283 compatible = "ti,divider-clock";
0284 clock-output-names = "div_core_ck";
0285 clocks = <&dpll_core_m5x2_ck>;
0286 reg = <0x0100>;
0287 ti,max-div = <2>;
0288 };
0289
0290 div_iva_hs_clk: div_iva_hs_clk@1dc {
0291 #clock-cells = <0>;
0292 compatible = "ti,divider-clock";
0293 clock-output-names = "div_iva_hs_clk";
0294 clocks = <&dpll_core_m5x2_ck>;
0295 ti,max-div = <4>;
0296 reg = <0x01dc>;
0297 ti,index-power-of-two;
0298 };
0299
0300 div_mpu_hs_clk: div_mpu_hs_clk@19c {
0301 #clock-cells = <0>;
0302 compatible = "ti,divider-clock";
0303 clock-output-names = "div_mpu_hs_clk";
0304 clocks = <&dpll_core_m5x2_ck>;
0305 ti,max-div = <4>;
0306 reg = <0x019c>;
0307 ti,index-power-of-two;
0308 };
0309
0310 dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 {
0311 #clock-cells = <0>;
0312 compatible = "ti,divider-clock";
0313 clock-output-names = "dpll_core_m4x2_ck";
0314 clocks = <&dpll_core_x2_ck>;
0315 ti,max-div = <31>;
0316 ti,autoidle-shift = <8>;
0317 reg = <0x0138>;
0318 ti,index-starts-at-one;
0319 ti,invert-autoidle-bit;
0320 };
0321
0322 dll_clk_div_ck: dll_clk_div_ck {
0323 #clock-cells = <0>;
0324 compatible = "fixed-factor-clock";
0325 clock-output-names = "dll_clk_div_ck";
0326 clocks = <&dpll_core_m4x2_ck>;
0327 clock-mult = <1>;
0328 clock-div = <2>;
0329 };
0330
0331 dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
0332 #clock-cells = <0>;
0333 compatible = "ti,divider-clock";
0334 clock-output-names = "dpll_abe_m2_ck";
0335 clocks = <&dpll_abe_ck>;
0336 ti,max-div = <31>;
0337 reg = <0x01f0>;
0338 ti,index-starts-at-one;
0339 };
0340
0341 dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 {
0342 #clock-cells = <0>;
0343 compatible = "ti,composite-no-wait-gate-clock";
0344 clock-output-names = "dpll_core_m3x2_gate_ck";
0345 clocks = <&dpll_core_x2_ck>;
0346 ti,bit-shift = <8>;
0347 reg = <0x0134>;
0348 };
0349
0350 dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 {
0351 #clock-cells = <0>;
0352 compatible = "ti,composite-divider-clock";
0353 clock-output-names = "dpll_core_m3x2_div_ck";
0354 clocks = <&dpll_core_x2_ck>;
0355 ti,max-div = <31>;
0356 reg = <0x0134>;
0357 ti,index-starts-at-one;
0358 };
0359
0360 dpll_core_m3x2_ck: dpll_core_m3x2_ck {
0361 #clock-cells = <0>;
0362 compatible = "ti,composite-clock";
0363 clock-output-names = "dpll_core_m3x2_ck";
0364 clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>;
0365 };
0366
0367 dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 {
0368 #clock-cells = <0>;
0369 compatible = "ti,divider-clock";
0370 clock-output-names = "dpll_core_m7x2_ck";
0371 clocks = <&dpll_core_x2_ck>;
0372 ti,max-div = <31>;
0373 ti,autoidle-shift = <8>;
0374 reg = <0x0144>;
0375 ti,index-starts-at-one;
0376 ti,invert-autoidle-bit;
0377 };
0378
0379 iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac {
0380 #clock-cells = <0>;
0381 compatible = "ti,mux-clock";
0382 clock-output-names = "iva_hsd_byp_clk_mux_ck";
0383 clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
0384 ti,bit-shift = <23>;
0385 reg = <0x01ac>;
0386 };
0387
0388 dpll_iva_ck: dpll_iva_ck@1a0 {
0389 #clock-cells = <0>;
0390 compatible = "ti,omap4-dpll-clock";
0391 clock-output-names = "dpll_iva_ck";
0392 clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
0393 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
0394 assigned-clocks = <&dpll_iva_ck>;
0395 assigned-clock-rates = <931200000>;
0396 };
0397
0398 dpll_iva_x2_ck: dpll_iva_x2_ck {
0399 #clock-cells = <0>;
0400 compatible = "ti,omap4-dpll-x2-clock";
0401 clock-output-names = "dpll_iva_x2_ck";
0402 clocks = <&dpll_iva_ck>;
0403 };
0404
0405 dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 {
0406 #clock-cells = <0>;
0407 compatible = "ti,divider-clock";
0408 clock-output-names = "dpll_iva_m4x2_ck";
0409 clocks = <&dpll_iva_x2_ck>;
0410 ti,max-div = <31>;
0411 ti,autoidle-shift = <8>;
0412 reg = <0x01b8>;
0413 ti,index-starts-at-one;
0414 ti,invert-autoidle-bit;
0415 assigned-clocks = <&dpll_iva_m4x2_ck>;
0416 assigned-clock-rates = <465600000>;
0417 };
0418
0419 dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
0420 #clock-cells = <0>;
0421 compatible = "ti,divider-clock";
0422 clock-output-names = "dpll_iva_m5x2_ck";
0423 clocks = <&dpll_iva_x2_ck>;
0424 ti,max-div = <31>;
0425 ti,autoidle-shift = <8>;
0426 reg = <0x01bc>;
0427 ti,index-starts-at-one;
0428 ti,invert-autoidle-bit;
0429 assigned-clocks = <&dpll_iva_m5x2_ck>;
0430 assigned-clock-rates = <266100000>;
0431 };
0432
0433 dpll_mpu_ck: dpll_mpu_ck@160 {
0434 #clock-cells = <0>;
0435 compatible = "ti,omap4-dpll-clock";
0436 clock-output-names = "dpll_mpu_ck";
0437 clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
0438 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
0439 };
0440
0441 dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
0442 #clock-cells = <0>;
0443 compatible = "ti,divider-clock";
0444 clock-output-names = "dpll_mpu_m2_ck";
0445 clocks = <&dpll_mpu_ck>;
0446 ti,max-div = <31>;
0447 ti,autoidle-shift = <8>;
0448 reg = <0x0170>;
0449 ti,index-starts-at-one;
0450 ti,invert-autoidle-bit;
0451 };
0452
0453 per_hs_clk_div_ck: per_hs_clk_div_ck {
0454 #clock-cells = <0>;
0455 compatible = "fixed-factor-clock";
0456 clock-output-names = "per_hs_clk_div_ck";
0457 clocks = <&dpll_abe_m3x2_ck>;
0458 clock-mult = <1>;
0459 clock-div = <2>;
0460 };
0461
0462 usb_hs_clk_div_ck: usb_hs_clk_div_ck {
0463 #clock-cells = <0>;
0464 compatible = "fixed-factor-clock";
0465 clock-output-names = "usb_hs_clk_div_ck";
0466 clocks = <&dpll_abe_m3x2_ck>;
0467 clock-mult = <1>;
0468 clock-div = <3>;
0469 };
0470
0471 l3_div_ck: l3_div_ck@100 {
0472 #clock-cells = <0>;
0473 compatible = "ti,divider-clock";
0474 clock-output-names = "l3_div_ck";
0475 clocks = <&div_core_ck>;
0476 ti,bit-shift = <4>;
0477 ti,max-div = <2>;
0478 reg = <0x0100>;
0479 };
0480
0481 l4_div_ck: l4_div_ck@100 {
0482 #clock-cells = <0>;
0483 compatible = "ti,divider-clock";
0484 clock-output-names = "l4_div_ck";
0485 clocks = <&l3_div_ck>;
0486 ti,bit-shift = <8>;
0487 ti,max-div = <2>;
0488 reg = <0x0100>;
0489 };
0490
0491 lp_clk_div_ck: lp_clk_div_ck {
0492 #clock-cells = <0>;
0493 compatible = "fixed-factor-clock";
0494 clock-output-names = "lp_clk_div_ck";
0495 clocks = <&dpll_abe_m2x2_ck>;
0496 clock-mult = <1>;
0497 clock-div = <16>;
0498 };
0499
0500 mpu_periphclk: mpu_periphclk {
0501 #clock-cells = <0>;
0502 compatible = "fixed-factor-clock";
0503 clock-output-names = "mpu_periphclk";
0504 clocks = <&dpll_mpu_ck>;
0505 clock-mult = <1>;
0506 clock-div = <2>;
0507 };
0508
0509 ocp_abe_iclk: ocp_abe_iclk@528 {
0510 #clock-cells = <0>;
0511 compatible = "ti,divider-clock";
0512 clock-output-names = "ocp_abe_iclk";
0513 clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>;
0514 ti,bit-shift = <24>;
0515 reg = <0x0528>;
0516 ti,dividers = <2>, <1>;
0517 };
0518
0519 per_abe_24m_fclk: per_abe_24m_fclk {
0520 #clock-cells = <0>;
0521 compatible = "fixed-factor-clock";
0522 clock-output-names = "per_abe_24m_fclk";
0523 clocks = <&dpll_abe_m2_ck>;
0524 clock-mult = <1>;
0525 clock-div = <4>;
0526 };
0527
0528 dummy_ck: dummy_ck {
0529 #clock-cells = <0>;
0530 compatible = "fixed-clock";
0531 clock-output-names = "dummy_ck";
0532 clock-frequency = <0>;
0533 };
0534 };
0535
0536 &prm_clocks {
0537 sys_clkin_ck: sys_clkin_ck@110 {
0538 #clock-cells = <0>;
0539 compatible = "ti,mux-clock";
0540 clock-output-names = "sys_clkin_ck";
0541 clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
0542 reg = <0x0110>;
0543 ti,index-starts-at-one;
0544 };
0545
0546 abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 {
0547 #clock-cells = <0>;
0548 compatible = "ti,mux-clock";
0549 clock-output-names = "abe_dpll_bypass_clk_mux_ck";
0550 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
0551 ti,bit-shift = <24>;
0552 reg = <0x0108>;
0553 };
0554
0555 abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c {
0556 #clock-cells = <0>;
0557 compatible = "ti,mux-clock";
0558 clock-output-names = "abe_dpll_refclk_mux_ck";
0559 clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
0560 reg = <0x010c>;
0561 };
0562
0563 dbgclk_mux_ck: dbgclk_mux_ck {
0564 #clock-cells = <0>;
0565 compatible = "fixed-factor-clock";
0566 clock-output-names = "dbgclk_mux_ck";
0567 clocks = <&sys_clkin_ck>;
0568 clock-mult = <1>;
0569 clock-div = <1>;
0570 };
0571
0572 l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 {
0573 #clock-cells = <0>;
0574 compatible = "ti,mux-clock";
0575 clock-output-names = "l4_wkup_clk_mux_ck";
0576 clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
0577 reg = <0x0108>;
0578 };
0579
0580 syc_clk_div_ck: syc_clk_div_ck@100 {
0581 #clock-cells = <0>;
0582 compatible = "ti,divider-clock";
0583 clock-output-names = "syc_clk_div_ck";
0584 clocks = <&sys_clkin_ck>;
0585 reg = <0x0100>;
0586 ti,max-div = <2>;
0587 };
0588
0589 usim_ck: usim_ck@1858 {
0590 #clock-cells = <0>;
0591 compatible = "ti,divider-clock";
0592 clock-output-names = "usim_ck";
0593 clocks = <&dpll_per_m4x2_ck>;
0594 ti,bit-shift = <24>;
0595 reg = <0x1858>;
0596 ti,dividers = <14>, <18>;
0597 };
0598
0599 usim_fclk: usim_fclk@1858 {
0600 #clock-cells = <0>;
0601 compatible = "ti,gate-clock";
0602 clock-output-names = "usim_fclk";
0603 clocks = <&usim_ck>;
0604 ti,bit-shift = <8>;
0605 reg = <0x1858>;
0606 };
0607
0608 trace_clk_div_ck: trace_clk_div_ck {
0609 #clock-cells = <0>;
0610 compatible = "ti,clkdm-gate-clock";
0611 clock-output-names = "trace_clk_div_ck";
0612 clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>;
0613 };
0614 };
0615
0616 &prm_clockdomains {
0617 emu_sys_clkdm: emu_sys_clkdm {
0618 compatible = "ti,clockdomain";
0619 clock-output-names = "emu_sys_clkdm";
0620 clocks = <&trace_clk_div_ck>;
0621 };
0622 };
0623
0624 &cm2_clocks {
0625 per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c {
0626 #clock-cells = <0>;
0627 compatible = "ti,mux-clock";
0628 clock-output-names = "per_hsd_byp_clk_mux_ck";
0629 clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
0630 ti,bit-shift = <23>;
0631 reg = <0x014c>;
0632 };
0633
0634 dpll_per_ck: dpll_per_ck@140 {
0635 #clock-cells = <0>;
0636 compatible = "ti,omap4-dpll-clock";
0637 clock-output-names = "dpll_per_ck";
0638 clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
0639 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
0640 };
0641
0642 dpll_per_m2_ck: dpll_per_m2_ck@150 {
0643 #clock-cells = <0>;
0644 compatible = "ti,divider-clock";
0645 clock-output-names = "dpll_per_m2_ck";
0646 clocks = <&dpll_per_ck>;
0647 ti,max-div = <31>;
0648 reg = <0x0150>;
0649 ti,index-starts-at-one;
0650 };
0651
0652 dpll_per_x2_ck: dpll_per_x2_ck@150 {
0653 #clock-cells = <0>;
0654 compatible = "ti,omap4-dpll-x2-clock";
0655 clock-output-names = "dpll_per_x2_ck";
0656 clocks = <&dpll_per_ck>;
0657 reg = <0x0150>;
0658 };
0659
0660 dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
0661 #clock-cells = <0>;
0662 compatible = "ti,divider-clock";
0663 clock-output-names = "dpll_per_m2x2_ck";
0664 clocks = <&dpll_per_x2_ck>;
0665 ti,max-div = <31>;
0666 ti,autoidle-shift = <8>;
0667 reg = <0x0150>;
0668 ti,index-starts-at-one;
0669 ti,invert-autoidle-bit;
0670 };
0671
0672 dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 {
0673 #clock-cells = <0>;
0674 compatible = "ti,composite-no-wait-gate-clock";
0675 clock-output-names = "dpll_per_m3x2_gate_ck";
0676 clocks = <&dpll_per_x2_ck>;
0677 ti,bit-shift = <8>;
0678 reg = <0x0154>;
0679 };
0680
0681 dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 {
0682 #clock-cells = <0>;
0683 compatible = "ti,composite-divider-clock";
0684 clock-output-names = "dpll_per_m3x2_div_ck";
0685 clocks = <&dpll_per_x2_ck>;
0686 ti,max-div = <31>;
0687 reg = <0x0154>;
0688 ti,index-starts-at-one;
0689 };
0690
0691 dpll_per_m3x2_ck: dpll_per_m3x2_ck {
0692 #clock-cells = <0>;
0693 compatible = "ti,composite-clock";
0694 clock-output-names = "dpll_per_m3x2_ck";
0695 clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>;
0696 };
0697
0698 dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 {
0699 #clock-cells = <0>;
0700 compatible = "ti,divider-clock";
0701 clock-output-names = "dpll_per_m4x2_ck";
0702 clocks = <&dpll_per_x2_ck>;
0703 ti,max-div = <31>;
0704 ti,autoidle-shift = <8>;
0705 reg = <0x0158>;
0706 ti,index-starts-at-one;
0707 ti,invert-autoidle-bit;
0708 };
0709
0710 dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c {
0711 #clock-cells = <0>;
0712 compatible = "ti,divider-clock";
0713 clock-output-names = "dpll_per_m5x2_ck";
0714 clocks = <&dpll_per_x2_ck>;
0715 ti,max-div = <31>;
0716 ti,autoidle-shift = <8>;
0717 reg = <0x015c>;
0718 ti,index-starts-at-one;
0719 ti,invert-autoidle-bit;
0720 };
0721
0722 dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 {
0723 #clock-cells = <0>;
0724 compatible = "ti,divider-clock";
0725 clock-output-names = "dpll_per_m6x2_ck";
0726 clocks = <&dpll_per_x2_ck>;
0727 ti,max-div = <31>;
0728 ti,autoidle-shift = <8>;
0729 reg = <0x0160>;
0730 ti,index-starts-at-one;
0731 ti,invert-autoidle-bit;
0732 };
0733
0734 dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 {
0735 #clock-cells = <0>;
0736 compatible = "ti,divider-clock";
0737 clock-output-names = "dpll_per_m7x2_ck";
0738 clocks = <&dpll_per_x2_ck>;
0739 ti,max-div = <31>;
0740 ti,autoidle-shift = <8>;
0741 reg = <0x0164>;
0742 ti,index-starts-at-one;
0743 ti,invert-autoidle-bit;
0744 };
0745
0746 dpll_usb_ck: dpll_usb_ck@180 {
0747 #clock-cells = <0>;
0748 compatible = "ti,omap4-dpll-j-type-clock";
0749 clock-output-names = "dpll_usb_ck";
0750 clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
0751 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
0752 };
0753
0754 dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 {
0755 #clock-cells = <0>;
0756 compatible = "ti,fixed-factor-clock";
0757 clock-output-names = "dpll_usb_clkdcoldo_ck";
0758 clocks = <&dpll_usb_ck>;
0759 ti,clock-div = <1>;
0760 ti,autoidle-shift = <8>;
0761 reg = <0x01b4>;
0762 ti,clock-mult = <1>;
0763 ti,invert-autoidle-bit;
0764 };
0765
0766 dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
0767 #clock-cells = <0>;
0768 compatible = "ti,divider-clock";
0769 clock-output-names = "dpll_usb_m2_ck";
0770 clocks = <&dpll_usb_ck>;
0771 ti,max-div = <127>;
0772 ti,autoidle-shift = <8>;
0773 reg = <0x0190>;
0774 ti,index-starts-at-one;
0775 ti,invert-autoidle-bit;
0776 };
0777
0778 ducati_clk_mux_ck: ducati_clk_mux_ck@100 {
0779 #clock-cells = <0>;
0780 compatible = "ti,mux-clock";
0781 clock-output-names = "ducati_clk_mux_ck";
0782 clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
0783 reg = <0x0100>;
0784 };
0785
0786 func_12m_fclk: func_12m_fclk {
0787 #clock-cells = <0>;
0788 compatible = "fixed-factor-clock";
0789 clock-output-names = "func_12m_fclk";
0790 clocks = <&dpll_per_m2x2_ck>;
0791 clock-mult = <1>;
0792 clock-div = <16>;
0793 };
0794
0795 func_24m_clk: func_24m_clk {
0796 #clock-cells = <0>;
0797 compatible = "fixed-factor-clock";
0798 clock-output-names = "func_24m_clk";
0799 clocks = <&dpll_per_m2_ck>;
0800 clock-mult = <1>;
0801 clock-div = <4>;
0802 };
0803
0804 func_24mc_fclk: func_24mc_fclk {
0805 #clock-cells = <0>;
0806 compatible = "fixed-factor-clock";
0807 clock-output-names = "func_24mc_fclk";
0808 clocks = <&dpll_per_m2x2_ck>;
0809 clock-mult = <1>;
0810 clock-div = <8>;
0811 };
0812
0813 func_48m_fclk: func_48m_fclk@108 {
0814 #clock-cells = <0>;
0815 compatible = "ti,divider-clock";
0816 clock-output-names = "func_48m_fclk";
0817 clocks = <&dpll_per_m2x2_ck>;
0818 reg = <0x0108>;
0819 ti,dividers = <4>, <8>;
0820 };
0821
0822 func_48mc_fclk: func_48mc_fclk {
0823 #clock-cells = <0>;
0824 compatible = "fixed-factor-clock";
0825 clock-output-names = "func_48mc_fclk";
0826 clocks = <&dpll_per_m2x2_ck>;
0827 clock-mult = <1>;
0828 clock-div = <4>;
0829 };
0830
0831 func_64m_fclk: func_64m_fclk@108 {
0832 #clock-cells = <0>;
0833 compatible = "ti,divider-clock";
0834 clock-output-names = "func_64m_fclk";
0835 clocks = <&dpll_per_m4x2_ck>;
0836 reg = <0x0108>;
0837 ti,dividers = <2>, <4>;
0838 };
0839
0840 func_96m_fclk: func_96m_fclk@108 {
0841 #clock-cells = <0>;
0842 compatible = "ti,divider-clock";
0843 clock-output-names = "func_96m_fclk";
0844 clocks = <&dpll_per_m2x2_ck>;
0845 reg = <0x0108>;
0846 ti,dividers = <2>, <4>;
0847 };
0848
0849 init_60m_fclk: init_60m_fclk@104 {
0850 #clock-cells = <0>;
0851 compatible = "ti,divider-clock";
0852 clock-output-names = "init_60m_fclk";
0853 clocks = <&dpll_usb_m2_ck>;
0854 reg = <0x0104>;
0855 ti,dividers = <1>, <8>;
0856 };
0857
0858 per_abe_nc_fclk: per_abe_nc_fclk@108 {
0859 #clock-cells = <0>;
0860 compatible = "ti,divider-clock";
0861 clock-output-names = "per_abe_nc_fclk";
0862 clocks = <&dpll_abe_m2_ck>;
0863 reg = <0x0108>;
0864 ti,max-div = <2>;
0865 };
0866
0867 usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
0868 #clock-cells = <0>;
0869 compatible = "ti,gate-clock";
0870 clock-output-names = "usb_phy_cm_clk32k";
0871 clocks = <&sys_32k_ck>;
0872 ti,bit-shift = <8>;
0873 reg = <0x0640>;
0874 };
0875 };
0876
0877 &cm2_clockdomains {
0878 l3_init_clkdm: l3_init_clkdm {
0879 compatible = "ti,clockdomain";
0880 clock-output-names = "l3_init_clkdm";
0881 clocks = <&dpll_usb_ck>;
0882 };
0883 };
0884
0885 &scrm_clocks {
0886 auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
0887 #clock-cells = <0>;
0888 compatible = "ti,composite-no-wait-gate-clock";
0889 clock-output-names = "auxclk0_src_gate_ck";
0890 clocks = <&dpll_core_m3x2_ck>;
0891 ti,bit-shift = <8>;
0892 reg = <0x0310>;
0893 };
0894
0895 auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
0896 #clock-cells = <0>;
0897 compatible = "ti,composite-mux-clock";
0898 clock-output-names = "auxclk0_src_mux_ck";
0899 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
0900 ti,bit-shift = <1>;
0901 reg = <0x0310>;
0902 };
0903
0904 auxclk0_src_ck: auxclk0_src_ck {
0905 #clock-cells = <0>;
0906 compatible = "ti,composite-clock";
0907 clock-output-names = "auxclk0_src_ck";
0908 clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
0909 };
0910
0911 auxclk0_ck: auxclk0_ck@310 {
0912 #clock-cells = <0>;
0913 compatible = "ti,divider-clock";
0914 clock-output-names = "auxclk0_ck";
0915 clocks = <&auxclk0_src_ck>;
0916 ti,bit-shift = <16>;
0917 ti,max-div = <16>;
0918 reg = <0x0310>;
0919 };
0920
0921 auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
0922 #clock-cells = <0>;
0923 compatible = "ti,composite-no-wait-gate-clock";
0924 clock-output-names = "auxclk1_src_gate_ck";
0925 clocks = <&dpll_core_m3x2_ck>;
0926 ti,bit-shift = <8>;
0927 reg = <0x0314>;
0928 };
0929
0930 auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
0931 #clock-cells = <0>;
0932 compatible = "ti,composite-mux-clock";
0933 clock-output-names = "auxclk1_src_mux_ck";
0934 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
0935 ti,bit-shift = <1>;
0936 reg = <0x0314>;
0937 };
0938
0939 auxclk1_src_ck: auxclk1_src_ck {
0940 #clock-cells = <0>;
0941 compatible = "ti,composite-clock";
0942 clock-output-names = "auxclk1_src_ck";
0943 clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
0944 };
0945
0946 auxclk1_ck: auxclk1_ck@314 {
0947 #clock-cells = <0>;
0948 compatible = "ti,divider-clock";
0949 clock-output-names = "auxclk1_ck";
0950 clocks = <&auxclk1_src_ck>;
0951 ti,bit-shift = <16>;
0952 ti,max-div = <16>;
0953 reg = <0x0314>;
0954 };
0955
0956 auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
0957 #clock-cells = <0>;
0958 compatible = "ti,composite-no-wait-gate-clock";
0959 clock-output-names = "auxclk2_src_gate_ck";
0960 clocks = <&dpll_core_m3x2_ck>;
0961 ti,bit-shift = <8>;
0962 reg = <0x0318>;
0963 };
0964
0965 auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
0966 #clock-cells = <0>;
0967 compatible = "ti,composite-mux-clock";
0968 clock-output-names = "auxclk2_src_mux_ck";
0969 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
0970 ti,bit-shift = <1>;
0971 reg = <0x0318>;
0972 };
0973
0974 auxclk2_src_ck: auxclk2_src_ck {
0975 #clock-cells = <0>;
0976 compatible = "ti,composite-clock";
0977 clock-output-names = "auxclk2_src_ck";
0978 clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
0979 };
0980
0981 auxclk2_ck: auxclk2_ck@318 {
0982 #clock-cells = <0>;
0983 compatible = "ti,divider-clock";
0984 clock-output-names = "auxclk2_ck";
0985 clocks = <&auxclk2_src_ck>;
0986 ti,bit-shift = <16>;
0987 ti,max-div = <16>;
0988 reg = <0x0318>;
0989 };
0990
0991 auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
0992 #clock-cells = <0>;
0993 compatible = "ti,composite-no-wait-gate-clock";
0994 clock-output-names = "auxclk3_src_gate_ck";
0995 clocks = <&dpll_core_m3x2_ck>;
0996 ti,bit-shift = <8>;
0997 reg = <0x031c>;
0998 };
0999
1000 auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
1001 #clock-cells = <0>;
1002 compatible = "ti,composite-mux-clock";
1003 clock-output-names = "auxclk3_src_mux_ck";
1004 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1005 ti,bit-shift = <1>;
1006 reg = <0x031c>;
1007 };
1008
1009 auxclk3_src_ck: auxclk3_src_ck {
1010 #clock-cells = <0>;
1011 compatible = "ti,composite-clock";
1012 clock-output-names = "auxclk3_src_ck";
1013 clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
1014 };
1015
1016 auxclk3_ck: auxclk3_ck@31c {
1017 #clock-cells = <0>;
1018 compatible = "ti,divider-clock";
1019 clock-output-names = "auxclk3_ck";
1020 clocks = <&auxclk3_src_ck>;
1021 ti,bit-shift = <16>;
1022 ti,max-div = <16>;
1023 reg = <0x031c>;
1024 };
1025
1026 auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
1027 #clock-cells = <0>;
1028 compatible = "ti,composite-no-wait-gate-clock";
1029 clock-output-names = "auxclk4_src_gate_ck";
1030 clocks = <&dpll_core_m3x2_ck>;
1031 ti,bit-shift = <8>;
1032 reg = <0x0320>;
1033 };
1034
1035 auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
1036 #clock-cells = <0>;
1037 compatible = "ti,composite-mux-clock";
1038 clock-output-names = "auxclk4_src_mux_ck";
1039 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1040 ti,bit-shift = <1>;
1041 reg = <0x0320>;
1042 };
1043
1044 auxclk4_src_ck: auxclk4_src_ck {
1045 #clock-cells = <0>;
1046 compatible = "ti,composite-clock";
1047 clock-output-names = "auxclk4_src_ck";
1048 clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
1049 };
1050
1051 auxclk4_ck: auxclk4_ck@320 {
1052 #clock-cells = <0>;
1053 compatible = "ti,divider-clock";
1054 clock-output-names = "auxclk4_ck";
1055 clocks = <&auxclk4_src_ck>;
1056 ti,bit-shift = <16>;
1057 ti,max-div = <16>;
1058 reg = <0x0320>;
1059 };
1060
1061 auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 {
1062 #clock-cells = <0>;
1063 compatible = "ti,composite-no-wait-gate-clock";
1064 clock-output-names = "auxclk5_src_gate_ck";
1065 clocks = <&dpll_core_m3x2_ck>;
1066 ti,bit-shift = <8>;
1067 reg = <0x0324>;
1068 };
1069
1070 auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 {
1071 #clock-cells = <0>;
1072 compatible = "ti,composite-mux-clock";
1073 clock-output-names = "auxclk5_src_mux_ck";
1074 clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1075 ti,bit-shift = <1>;
1076 reg = <0x0324>;
1077 };
1078
1079 auxclk5_src_ck: auxclk5_src_ck {
1080 #clock-cells = <0>;
1081 compatible = "ti,composite-clock";
1082 clock-output-names = "auxclk5_src_ck";
1083 clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>;
1084 };
1085
1086 auxclk5_ck: auxclk5_ck@324 {
1087 #clock-cells = <0>;
1088 compatible = "ti,divider-clock";
1089 clock-output-names = "auxclk5_ck";
1090 clocks = <&auxclk5_src_ck>;
1091 ti,bit-shift = <16>;
1092 ti,max-div = <16>;
1093 reg = <0x0324>;
1094 };
1095
1096 auxclkreq0_ck: auxclkreq0_ck@210 {
1097 #clock-cells = <0>;
1098 compatible = "ti,mux-clock";
1099 clock-output-names = "auxclkreq0_ck";
1100 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1101 ti,bit-shift = <2>;
1102 reg = <0x0210>;
1103 };
1104
1105 auxclkreq1_ck: auxclkreq1_ck@214 {
1106 #clock-cells = <0>;
1107 compatible = "ti,mux-clock";
1108 clock-output-names = "auxclkreq1_ck";
1109 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1110 ti,bit-shift = <2>;
1111 reg = <0x0214>;
1112 };
1113
1114 auxclkreq2_ck: auxclkreq2_ck@218 {
1115 #clock-cells = <0>;
1116 compatible = "ti,mux-clock";
1117 clock-output-names = "auxclkreq2_ck";
1118 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1119 ti,bit-shift = <2>;
1120 reg = <0x0218>;
1121 };
1122
1123 auxclkreq3_ck: auxclkreq3_ck@21c {
1124 #clock-cells = <0>;
1125 compatible = "ti,mux-clock";
1126 clock-output-names = "auxclkreq3_ck";
1127 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1128 ti,bit-shift = <2>;
1129 reg = <0x021c>;
1130 };
1131
1132 auxclkreq4_ck: auxclkreq4_ck@220 {
1133 #clock-cells = <0>;
1134 compatible = "ti,mux-clock";
1135 clock-output-names = "auxclkreq4_ck";
1136 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1137 ti,bit-shift = <2>;
1138 reg = <0x0220>;
1139 };
1140
1141 auxclkreq5_ck: auxclkreq5_ck@224 {
1142 #clock-cells = <0>;
1143 compatible = "ti,mux-clock";
1144 clock-output-names = "auxclkreq5_ck";
1145 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
1146 ti,bit-shift = <2>;
1147 reg = <0x0224>;
1148 };
1149 };
1150
1151 &cm1 {
1152 mpuss_cm: mpuss_cm@300 {
1153 compatible = "ti,omap4-cm";
1154 clock-output-names = "mpuss_cm";
1155 reg = <0x300 0x100>;
1156 #address-cells = <1>;
1157 #size-cells = <1>;
1158 ranges = <0 0x300 0x100>;
1159
1160 mpuss_clkctrl: clk@20 {
1161 compatible = "ti,clkctrl";
1162 clock-output-names = "mpuss_clkctrl";
1163 reg = <0x20 0x4>;
1164 #clock-cells = <2>;
1165 };
1166 };
1167
1168 tesla_cm: tesla_cm@400 {
1169 compatible = "ti,omap4-cm";
1170 clock-output-names = "tesla_cm";
1171 reg = <0x400 0x100>;
1172 #address-cells = <1>;
1173 #size-cells = <1>;
1174 ranges = <0 0x400 0x100>;
1175
1176 tesla_clkctrl: clk@20 {
1177 compatible = "ti,clkctrl";
1178 clock-output-names = "tesla_clkctrl";
1179 reg = <0x20 0x4>;
1180 #clock-cells = <2>;
1181 };
1182 };
1183
1184 abe_cm: abe_cm@500 {
1185 compatible = "ti,omap4-cm";
1186 clock-output-names = "abe_cm";
1187 reg = <0x500 0x100>;
1188 #address-cells = <1>;
1189 #size-cells = <1>;
1190 ranges = <0 0x500 0x100>;
1191
1192 abe_clkctrl: clk@20 {
1193 compatible = "ti,clkctrl";
1194 clock-output-names = "abe_clkctrl";
1195 reg = <0x20 0x6c>;
1196 #clock-cells = <2>;
1197 };
1198 };
1199
1200 };
1201
1202 &cm2 {
1203 l4_ao_cm: l4_ao_cm@600 {
1204 compatible = "ti,omap4-cm";
1205 clock-output-names = "l4_ao_cm";
1206 reg = <0x600 0x100>;
1207 #address-cells = <1>;
1208 #size-cells = <1>;
1209 ranges = <0 0x600 0x100>;
1210
1211 l4_ao_clkctrl: clk@20 {
1212 compatible = "ti,clkctrl";
1213 clock-output-names = "l4_ao_clkctrl";
1214 reg = <0x20 0x1c>;
1215 #clock-cells = <2>;
1216 };
1217 };
1218
1219 l3_1_cm: l3_1_cm@700 {
1220 compatible = "ti,omap4-cm";
1221 clock-output-names = "l3_1_cm";
1222 reg = <0x700 0x100>;
1223 #address-cells = <1>;
1224 #size-cells = <1>;
1225 ranges = <0 0x700 0x100>;
1226
1227 l3_1_clkctrl: clk@20 {
1228 compatible = "ti,clkctrl";
1229 clock-output-names = "l3_1_clkctrl";
1230 reg = <0x20 0x4>;
1231 #clock-cells = <2>;
1232 };
1233 };
1234
1235 l3_2_cm: l3_2_cm@800 {
1236 compatible = "ti,omap4-cm";
1237 clock-output-names = "l3_2_cm";
1238 reg = <0x800 0x100>;
1239 #address-cells = <1>;
1240 #size-cells = <1>;
1241 ranges = <0 0x800 0x100>;
1242
1243 l3_2_clkctrl: clk@20 {
1244 compatible = "ti,clkctrl";
1245 clock-output-names = "l3_2_clkctrl";
1246 reg = <0x20 0x14>;
1247 #clock-cells = <2>;
1248 };
1249 };
1250
1251 ducati_cm: ducati_cm@900 {
1252 compatible = "ti,omap4-cm";
1253 clock-output-names = "ducati_cm";
1254 reg = <0x900 0x100>;
1255 #address-cells = <1>;
1256 #size-cells = <1>;
1257 ranges = <0 0x900 0x100>;
1258
1259 ducati_clkctrl: clk@20 {
1260 compatible = "ti,clkctrl";
1261 clock-output-names = "ducati_clkctrl";
1262 reg = <0x20 0x4>;
1263 #clock-cells = <2>;
1264 };
1265 };
1266
1267 l3_dma_cm: l3_dma_cm@a00 {
1268 compatible = "ti,omap4-cm";
1269 clock-output-names = "l3_dma_cm";
1270 reg = <0xa00 0x100>;
1271 #address-cells = <1>;
1272 #size-cells = <1>;
1273 ranges = <0 0xa00 0x100>;
1274
1275 l3_dma_clkctrl: clk@20 {
1276 compatible = "ti,clkctrl";
1277 clock-output-names = "l3_dma_clkctrl";
1278 reg = <0x20 0x4>;
1279 #clock-cells = <2>;
1280 };
1281 };
1282
1283 l3_emif_cm: l3_emif_cm@b00 {
1284 compatible = "ti,omap4-cm";
1285 clock-output-names = "l3_emif_cm";
1286 reg = <0xb00 0x100>;
1287 #address-cells = <1>;
1288 #size-cells = <1>;
1289 ranges = <0 0xb00 0x100>;
1290
1291 l3_emif_clkctrl: clk@20 {
1292 compatible = "ti,clkctrl";
1293 clock-output-names = "l3_emif_clkctrl";
1294 reg = <0x20 0x1c>;
1295 #clock-cells = <2>;
1296 };
1297 };
1298
1299 d2d_cm: d2d_cm@c00 {
1300 compatible = "ti,omap4-cm";
1301 clock-output-names = "d2d_cm";
1302 reg = <0xc00 0x100>;
1303 #address-cells = <1>;
1304 #size-cells = <1>;
1305 ranges = <0 0xc00 0x100>;
1306
1307 d2d_clkctrl: clk@20 {
1308 compatible = "ti,clkctrl";
1309 clock-output-names = "d2d_clkctrl";
1310 reg = <0x20 0x4>;
1311 #clock-cells = <2>;
1312 };
1313 };
1314
1315 l4_cfg_cm: l4_cfg_cm@d00 {
1316 compatible = "ti,omap4-cm";
1317 clock-output-names = "l4_cfg_cm";
1318 reg = <0xd00 0x100>;
1319 #address-cells = <1>;
1320 #size-cells = <1>;
1321 ranges = <0 0xd00 0x100>;
1322
1323 l4_cfg_clkctrl: clk@20 {
1324 compatible = "ti,clkctrl";
1325 clock-output-names = "l4_cfg_clkctrl";
1326 reg = <0x20 0x14>;
1327 #clock-cells = <2>;
1328 };
1329 };
1330
1331 l3_instr_cm: l3_instr_cm@e00 {
1332 compatible = "ti,omap4-cm";
1333 clock-output-names = "l3_instr_cm";
1334 reg = <0xe00 0x100>;
1335 #address-cells = <1>;
1336 #size-cells = <1>;
1337 ranges = <0 0xe00 0x100>;
1338
1339 l3_instr_clkctrl: clk@20 {
1340 compatible = "ti,clkctrl";
1341 clock-output-names = "l3_instr_clkctrl";
1342 reg = <0x20 0x24>;
1343 #clock-cells = <2>;
1344 };
1345 };
1346
1347 ivahd_cm: ivahd_cm@f00 {
1348 compatible = "ti,omap4-cm";
1349 clock-output-names = "ivahd_cm";
1350 reg = <0xf00 0x100>;
1351 #address-cells = <1>;
1352 #size-cells = <1>;
1353 ranges = <0 0xf00 0x100>;
1354
1355 ivahd_clkctrl: clk@20 {
1356 compatible = "ti,clkctrl";
1357 clock-output-names = "ivahd_clkctrl";
1358 reg = <0x20 0xc>;
1359 #clock-cells = <2>;
1360 };
1361 };
1362
1363 iss_cm: iss_cm@1000 {
1364 compatible = "ti,omap4-cm";
1365 clock-output-names = "iss_cm";
1366 reg = <0x1000 0x100>;
1367 #address-cells = <1>;
1368 #size-cells = <1>;
1369 ranges = <0 0x1000 0x100>;
1370
1371 iss_clkctrl: clk@20 {
1372 compatible = "ti,clkctrl";
1373 clock-output-names = "iss_clkctrl";
1374 reg = <0x20 0xc>;
1375 #clock-cells = <2>;
1376 };
1377 };
1378
1379 l3_dss_cm: l3_dss_cm@1100 {
1380 compatible = "ti,omap4-cm";
1381 clock-output-names = "l3_dss_cm";
1382 reg = <0x1100 0x100>;
1383 #address-cells = <1>;
1384 #size-cells = <1>;
1385 ranges = <0 0x1100 0x100>;
1386
1387 l3_dss_clkctrl: clk@20 {
1388 compatible = "ti,clkctrl";
1389 clock-output-names = "l3_dss_clkctrl";
1390 reg = <0x20 0x4>;
1391 #clock-cells = <2>;
1392 };
1393 };
1394
1395 l3_gfx_cm: l3_gfx_cm@1200 {
1396 compatible = "ti,omap4-cm";
1397 clock-output-names = "l3_gfx_cm";
1398 reg = <0x1200 0x100>;
1399 #address-cells = <1>;
1400 #size-cells = <1>;
1401 ranges = <0 0x1200 0x100>;
1402
1403 l3_gfx_clkctrl: clk@20 {
1404 compatible = "ti,clkctrl";
1405 clock-output-names = "l3_gfx_clkctrl";
1406 reg = <0x20 0x4>;
1407 #clock-cells = <2>;
1408 };
1409 };
1410
1411 l3_init_cm: l3_init_cm@1300 {
1412 compatible = "ti,omap4-cm";
1413 clock-output-names = "l3_init_cm";
1414 reg = <0x1300 0x100>;
1415 #address-cells = <1>;
1416 #size-cells = <1>;
1417 ranges = <0 0x1300 0x100>;
1418
1419 l3_init_clkctrl: clk@20 {
1420 compatible = "ti,clkctrl";
1421 clock-output-names = "l3_init_clkctrl";
1422 reg = <0x20 0xc4>;
1423 #clock-cells = <2>;
1424 };
1425 };
1426
1427 l4_per_cm: clock@1400 {
1428 compatible = "ti,omap4-cm";
1429 clock-output-names = "l4_per_cm";
1430 reg = <0x1400 0x200>;
1431 #address-cells = <1>;
1432 #size-cells = <1>;
1433 ranges = <0 0x1400 0x200>;
1434
1435 l4_per_clkctrl: clock@20 {
1436 compatible = "ti,clkctrl";
1437 clock-output-names = "l4_per_clkctrl";
1438 reg = <0x20 0x144>;
1439 #clock-cells = <2>;
1440 };
1441
1442 l4_secure_clkctrl: clock@1a0 {
1443 compatible = "ti,clkctrl";
1444 clock-output-names = "l4_secure_clkctrl";
1445 reg = <0x1a0 0x3c>;
1446 #clock-cells = <2>;
1447 };
1448 };
1449 };
1450
1451 &prm {
1452 l4_wkup_cm: l4_wkup_cm@1800 {
1453 compatible = "ti,omap4-cm";
1454 clock-output-names = "l4_wkup_cm";
1455 reg = <0x1800 0x100>;
1456 #address-cells = <1>;
1457 #size-cells = <1>;
1458 ranges = <0 0x1800 0x100>;
1459
1460 l4_wkup_clkctrl: clk@20 {
1461 compatible = "ti,clkctrl";
1462 clock-output-names = "l4_wkup_clkctrl";
1463 reg = <0x20 0x5c>;
1464 #clock-cells = <2>;
1465 };
1466 };
1467
1468 emu_sys_cm: emu_sys_cm@1a00 {
1469 compatible = "ti,omap4-cm";
1470 clock-output-names = "emu_sys_cm";
1471 reg = <0x1a00 0x100>;
1472 #address-cells = <1>;
1473 #size-cells = <1>;
1474 ranges = <0 0x1a00 0x100>;
1475
1476 emu_sys_clkctrl: clk@20 {
1477 compatible = "ti,clkctrl";
1478 clock-output-names = "emu_sys_clkctrl";
1479 reg = <0x20 0x4>;
1480 #clock-cells = <2>;
1481 };
1482 };
1483 };
