0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for OMAP4460 SoC
0004 *
0005 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007 #include "omap4.dtsi"
0008
0009 / {
0010 cpus {
0011 /* OMAP446x 'standard device' variants OPP50 to OPPTurbo */
0012 cpu0: cpu@0 {
0013 operating-points = <
0014 /* kHz uV */
0015 350000 1025000
0016 700000 1200000
0017 920000 1313000
0018 >;
0019 clock-latency = <300000>; /* From legacy driver */
0020
0021 /* cooling options */
0022 #cooling-cells = <2>; /* min followed by max */
0023 };
0024 };
0025
0026 thermal-zones {
0027 #include "omap4-cpu-thermal.dtsi"
0028 };
0029
0030 ocp {
0031 bandgap: bandgap@4a002260 {
0032 reg = <0x4a002260 0x4
0033 0x4a00232C 0x4
0034 0x4a002378 0x18>;
0035 compatible = "ti,omap4460-bandgap";
0036 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
0037 gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* tshut */
0038
0039 #thermal-sensor-cells = <0>;
0040 };
0041
0042 abb_mpu: regulator-abb-mpu {
0043 status = "okay";
0044
0045 reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
0046 <0x4A002268 0x4>;
0047 reg-names = "base-address", "int-address",
0048 "efuse-address";
0049
0050 ti,abb_info = <
0051 /*uV ABB efuse rbb_m fbb_m vset_m*/
0052 1025000 0 0 0 0 0
0053 1200000 0 0 0 0 0
0054 1313000 0 0 0x100000 0x40000 0
0055 1375000 1 0 0 0 0
0056 1389000 1 0 0 0 0
0057 >;
0058 };
0059
0060 abb_iva: regulator-abb-iva {
0061 status = "okay";
0062
0063 reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>,
0064 <0x4A002268 0x4>;
0065 reg-names = "base-address", "int-address",
0066 "efuse-address";
0067
0068 ti,abb_info = <
0069 /*uV ABB efuse rbb_m fbb_m vset_m*/
0070 950000 0 0 0 0 0
0071 1140000 0 0 0 0 0
0072 1291000 0 0 0x200000 0 0
0073 1375000 1 0 0 0 0
0074 1376000 1 0 0 0 0
0075 >;
0076 };
0077 };
0078
0079 };
0080
0081 &cpu_thermal {
0082 coefficients = <348 (-9301)>;
0083 };
0084
0085 /* Only some L4 CFG interconnect ranges are different on 4460 */
0086 &l4_cfg_segment_300000 {
0087 ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
0088 <0x00040000 0x00340000 0x001000>, /* ap 68 */
0089 <0x00020000 0x00320000 0x004000>, /* ap 71 */
0090 <0x00024000 0x00324000 0x002000>, /* ap 72 */
0091 <0x00026000 0x00326000 0x001000>, /* ap 73 */
0092 <0x00027000 0x00327000 0x001000>, /* ap 74 */
0093 <0x00028000 0x00328000 0x001000>, /* ap 75 */
0094 <0x00029000 0x00329000 0x001000>, /* ap 76 */
0095 <0x00030000 0x00330000 0x010000>, /* ap 77 */
0096 <0x0002a000 0x0032a000 0x002000>, /* ap 90 */
0097 <0x0002c000 0x0032c000 0x004000>, /* ap 91 */
0098 <0x00010000 0x00310000 0x008000>, /* ap 92 */
0099 <0x00018000 0x00318000 0x004000>, /* ap 93 */
0100 <0x0001c000 0x0031c000 0x002000>, /* ap 94 */
0101 <0x0001e000 0x0031e000 0x002000>; /* ap 95 */
0102 };
0103
0104 &l4_cfg_target_0 {
0105 ranges = <0x00000000 0x00000000 0x00010000>,
0106 <0x00010000 0x00010000 0x00008000>,
0107 <0x00018000 0x00018000 0x00004000>,
0108 <0x0001c000 0x0001c000 0x00002000>,
0109 <0x0001e000 0x0001e000 0x00002000>,
0110 <0x00020000 0x00020000 0x00004000>,
0111 <0x00024000 0x00024000 0x00002000>,
0112 <0x00026000 0x00026000 0x00001000>,
0113 <0x00027000 0x00027000 0x00001000>,
0114 <0x00028000 0x00028000 0x00001000>,
0115 <0x00029000 0x00029000 0x00001000>,
0116 <0x0002a000 0x0002a000 0x00002000>,
0117 <0x0002c000 0x0002c000 0x00004000>,
0118 <0x00030000 0x00030000 0x00010000>;
0119 };
0120
0121 &pmu {
0122 compatible = "arm,cortex-a9-pmu";
0123 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
0124 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0125 };
0126
0127 /include/ "omap446x-clocks.dtsi"
