0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
0004 */
0005
0006 #include <dt-bindings/bus/ti-sysc.h>
0007 #include <dt-bindings/clock/omap4.h>
0008 #include <dt-bindings/gpio/gpio.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/pinctrl/omap.h>
0011 #include <dt-bindings/clock/omap4.h>
0012
0013 / {
0014 compatible = "ti,omap4430", "ti,omap4";
0015 interrupt-parent = <&wakeupgen>;
0016 #address-cells = <1>;
0017 #size-cells = <1>;
0018 chosen { };
0019
0020 aliases {
0021 i2c0 = &i2c1;
0022 i2c1 = &i2c2;
0023 i2c2 = &i2c3;
0024 i2c3 = &i2c4;
0025 mmc0 = &mmc1;
0026 mmc1 = &mmc2;
0027 mmc2 = &mmc3;
0028 mmc3 = &mmc4;
0029 mmc4 = &mmc5;
0030 serial0 = &uart1;
0031 serial1 = &uart2;
0032 serial2 = &uart3;
0033 serial3 = &uart4;
0034 rproc0 = &dsp;
0035 rproc1 = &ipu;
0036 };
0037
0038 cpus {
0039 #address-cells = <1>;
0040 #size-cells = <0>;
0041
0042 cpu@0 {
0043 compatible = "arm,cortex-a9";
0044 device_type = "cpu";
0045 next-level-cache = <&L2>;
0046 reg = <0x0>;
0047
0048 clocks = <&dpll_mpu_ck>;
0049 clock-names = "cpu";
0050
0051 clock-latency = <300000>; /* From omap-cpufreq driver */
0052 };
0053 cpu@1 {
0054 compatible = "arm,cortex-a9";
0055 device_type = "cpu";
0056 next-level-cache = <&L2>;
0057 reg = <0x1>;
0058 };
0059 };
0060
0061 /*
0062 * Needed early by omap4_sram_init() for barrier, do not move to l3
0063 * interconnect as simple-pm-bus probes at module_init() time.
0064 */
0065 ocmcram: sram@40304000 {
0066 compatible = "mmio-sram";
0067 reg = <0x40304000 0xa000>; /* 40k */
0068 };
0069
0070 gic: interrupt-controller@48241000 {
0071 compatible = "arm,cortex-a9-gic";
0072 interrupt-controller;
0073 #interrupt-cells = <3>;
0074 reg = <0x48241000 0x1000>,
0075 <0x48240100 0x0100>;
0076 interrupt-parent = <&gic>;
0077 };
0078
0079 L2: cache-controller@48242000 {
0080 compatible = "arm,pl310-cache";
0081 reg = <0x48242000 0x1000>;
0082 cache-unified;
0083 cache-level = <2>;
0084 };
0085
0086 local-timer@48240600 {
0087 compatible = "arm,cortex-a9-twd-timer";
0088 clocks = <&mpu_periphclk>;
0089 reg = <0x48240600 0x20>;
0090 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
0091 interrupt-parent = <&gic>;
0092 };
0093
0094 wakeupgen: interrupt-controller@48281000 {
0095 compatible = "ti,omap4-wugen-mpu";
0096 interrupt-controller;
0097 #interrupt-cells = <3>;
0098 reg = <0x48281000 0x1000>;
0099 interrupt-parent = <&gic>;
0100 };
0101
0102 /*
0103 * XXX: Use a flat representation of the OMAP4 interconnect.
0104 * The real OMAP interconnect network is quite complex.
0105 * Since it will not bring real advantage to represent that in DT for
0106 * the moment, just use a fake OCP bus entry to represent the whole bus
0107 * hierarchy.
0108 */
0109 ocp {
0110 compatible = "simple-pm-bus";
0111 power-domains = <&prm_l4per>;
0112 clocks = <&l3_1_clkctrl OMAP4_L3_MAIN_1_CLKCTRL 0>,
0113 <&l3_2_clkctrl OMAP4_L3_MAIN_2_CLKCTRL 0>,
0114 <&l3_instr_clkctrl OMAP4_L3_MAIN_3_CLKCTRL 0>;
0115 #address-cells = <1>;
0116 #size-cells = <1>;
0117 ranges;
0118
0119 l3-noc@44000000 {
0120 compatible = "ti,omap4-l3-noc";
0121 reg = <0x44000000 0x1000>,
0122 <0x44800000 0x2000>,
0123 <0x45000000 0x1000>;
0124 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0125 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0126 };
0127
0128 l4_wkup: interconnect@4a300000 {
0129 };
0130
0131 l4_cfg: interconnect@4a000000 {
0132 };
0133
0134 l4_per: interconnect@48000000 {
0135 };
0136
0137 target-module@48210000 {
0138 compatible = "ti,sysc-omap4-simple", "ti,sysc";
0139 power-domains = <&prm_mpu>;
0140 clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
0141 clock-names = "fck";
0142 #address-cells = <1>;
0143 #size-cells = <1>;
0144 ranges = <0 0x48210000 0x1f0000>;
0145
0146 mpu {
0147 compatible = "ti,omap4-mpu";
0148 sram = <&ocmcram>;
0149 };
0150 };
0151
0152 l4_abe: interconnect@40100000 {
0153 };
0154
0155 target-module@50000000 {
0156 compatible = "ti,sysc-omap2", "ti,sysc";
0157 reg = <0x50000000 4>,
0158 <0x50000010 4>,
0159 <0x50000014 4>;
0160 reg-names = "rev", "sysc", "syss";
0161 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0162 <SYSC_IDLE_NO>,
0163 <SYSC_IDLE_SMART>;
0164 ti,syss-mask = <1>;
0165 ti,no-idle-on-init;
0166 clocks = <&l3_2_clkctrl OMAP4_GPMC_CLKCTRL 0>;
0167 clock-names = "fck";
0168 #address-cells = <1>;
0169 #size-cells = <1>;
0170 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
0171 <0x00000000 0x00000000 0x40000000>; /* data */
0172
0173 gpmc: gpmc@50000000 {
0174 compatible = "ti,omap4430-gpmc";
0175 reg = <0x50000000 0x1000>;
0176 #address-cells = <2>;
0177 #size-cells = <1>;
0178 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0179 dmas = <&sdma 4>;
0180 dma-names = "rxtx";
0181 gpmc,num-cs = <8>;
0182 gpmc,num-waitpins = <4>;
0183 clocks = <&l3_div_ck>;
0184 clock-names = "fck";
0185 interrupt-controller;
0186 #interrupt-cells = <2>;
0187 gpio-controller;
0188 #gpio-cells = <2>;
0189 };
0190 };
0191
0192 target-module@52000000 {
0193 compatible = "ti,sysc-omap4", "ti,sysc";
0194 reg = <0x52000000 0x4>,
0195 <0x52000010 0x4>;
0196 reg-names = "rev", "sysc";
0197 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
0198 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0199 <SYSC_IDLE_NO>,
0200 <SYSC_IDLE_SMART>,
0201 <SYSC_IDLE_SMART_WKUP>;
0202 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0203 <SYSC_IDLE_NO>,
0204 <SYSC_IDLE_SMART>,
0205 <SYSC_IDLE_SMART_WKUP>;
0206 ti,sysc-delay-us = <2>;
0207 power-domains = <&prm_cam>;
0208 clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
0209 clock-names = "fck";
0210 #address-cells = <1>;
0211 #size-cells = <1>;
0212 ranges = <0 0x52000000 0x1000000>;
0213
0214 /* No child device binding, driver in staging */
0215 };
0216
0217 /*
0218 * Note that 4430 needs cross trigger interface (CTI) supported
0219 * before we can configure the interrupts. This means sampling
0220 * events are not supported for pmu. Note that 4460 does not use
0221 * CTI, see also 4460.dtsi.
0222 */
0223 target-module@54000000 {
0224 compatible = "ti,sysc-omap4-simple", "ti,sysc";
0225 power-domains = <&prm_emu>;
0226 clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 0>;
0227 clock-names = "fck";
0228 #address-cells = <1>;
0229 #size-cells = <1>;
0230 ranges = <0x0 0x54000000 0x1000000>;
0231
0232 pmu: pmu {
0233 compatible = "arm,cortex-a9-pmu";
0234 };
0235 };
0236
0237 target-module@55082000 {
0238 compatible = "ti,sysc-omap2", "ti,sysc";
0239 reg = <0x55082000 0x4>,
0240 <0x55082010 0x4>,
0241 <0x55082014 0x4>;
0242 reg-names = "rev", "sysc", "syss";
0243 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0244 <SYSC_IDLE_NO>,
0245 <SYSC_IDLE_SMART>;
0246 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0247 SYSC_OMAP2_SOFTRESET |
0248 SYSC_OMAP2_AUTOIDLE)>;
0249 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
0250 clock-names = "fck";
0251 resets = <&prm_core 2>;
0252 reset-names = "rstctrl";
0253 ranges = <0x0 0x55082000 0x100>;
0254 #size-cells = <1>;
0255 #address-cells = <1>;
0256
0257 mmu_ipu: mmu@0 {
0258 compatible = "ti,omap4-iommu";
0259 reg = <0x0 0x100>;
0260 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0261 #iommu-cells = <0>;
0262 ti,iommu-bus-err-back;
0263 };
0264 };
0265
0266 target-module@4012c000 {
0267 compatible = "ti,sysc-omap4", "ti,sysc";
0268 reg = <0x4012c000 0x4>,
0269 <0x4012c010 0x4>;
0270 reg-names = "rev", "sysc";
0271 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
0272 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0273 <SYSC_IDLE_NO>,
0274 <SYSC_IDLE_SMART>,
0275 <SYSC_IDLE_SMART_WKUP>;
0276 clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
0277 clock-names = "fck";
0278 #address-cells = <1>;
0279 #size-cells = <1>;
0280 ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
0281 <0x4902c000 0x4902c000 0x1000>; /* L3 */
0282
0283 /* No child device binding or driver in mainline */
0284 };
0285
0286 target-module@4e000000 {
0287 compatible = "ti,sysc-omap2", "ti,sysc";
0288 reg = <0x4e000000 0x4>,
0289 <0x4e000010 0x4>;
0290 reg-names = "rev", "sysc";
0291 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0292 <SYSC_IDLE_NO>,
0293 <SYSC_IDLE_SMART>;
0294 ranges = <0x0 0x4e000000 0x2000000>;
0295 #size-cells = <1>;
0296 #address-cells = <1>;
0297
0298 dmm@0 {
0299 compatible = "ti,omap4-dmm";
0300 reg = <0 0x800>;
0301 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
0302 };
0303 };
0304
0305 target-module@4c000000 {
0306 compatible = "ti,sysc-omap4-simple", "ti,sysc";
0307 reg = <0x4c000000 0x4>;
0308 reg-names = "rev";
0309 clocks = <&l3_emif_clkctrl OMAP4_EMIF1_CLKCTRL 0>;
0310 clock-names = "fck";
0311 ti,no-idle;
0312 #address-cells = <1>;
0313 #size-cells = <1>;
0314 ranges = <0x0 0x4c000000 0x1000000>;
0315
0316 emif1: emif@0 {
0317 compatible = "ti,emif-4d";
0318 reg = <0 0x100>;
0319 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0320 phy-type = <1>;
0321 hw-caps-read-idle-ctrl;
0322 hw-caps-ll-interface;
0323 hw-caps-temp-alert;
0324 };
0325 };
0326
0327 target-module@4d000000 {
0328 compatible = "ti,sysc-omap4-simple", "ti,sysc";
0329 reg = <0x4d000000 0x4>;
0330 reg-names = "rev";
0331 clocks = <&l3_emif_clkctrl OMAP4_EMIF2_CLKCTRL 0>;
0332 clock-names = "fck";
0333 ti,no-idle;
0334 #address-cells = <1>;
0335 #size-cells = <1>;
0336 ranges = <0x0 0x4d000000 0x1000000>;
0337
0338 emif2: emif@0 {
0339 compatible = "ti,emif-4d";
0340 reg = <0 0x100>;
0341 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
0342 phy-type = <1>;
0343 hw-caps-read-idle-ctrl;
0344 hw-caps-ll-interface;
0345 hw-caps-temp-alert;
0346 };
0347 };
0348
0349 dsp: dsp {
0350 compatible = "ti,omap4-dsp";
0351 ti,bootreg = <&scm_conf 0x304 0>;
0352 iommus = <&mmu_dsp>;
0353 resets = <&prm_tesla 0>;
0354 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
0355 firmware-name = "omap4-dsp-fw.xe64T";
0356 mboxes = <&mailbox &mbox_dsp>;
0357 status = "disabled";
0358 };
0359
0360 ipu: ipu@55020000 {
0361 compatible = "ti,omap4-ipu";
0362 reg = <0x55020000 0x10000>;
0363 reg-names = "l2ram";
0364 iommus = <&mmu_ipu>;
0365 resets = <&prm_core 0>, <&prm_core 1>;
0366 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
0367 firmware-name = "omap4-ipu-fw.xem3";
0368 mboxes = <&mailbox &mbox_ipu>;
0369 status = "disabled";
0370 };
0371
0372 aes1_target: target-module@4b501000 {
0373 compatible = "ti,sysc-omap2", "ti,sysc";
0374 reg = <0x4b501080 0x4>,
0375 <0x4b501084 0x4>,
0376 <0x4b501088 0x4>;
0377 reg-names = "rev", "sysc", "syss";
0378 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
0379 SYSC_OMAP2_AUTOIDLE)>;
0380 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0381 <SYSC_IDLE_NO>,
0382 <SYSC_IDLE_SMART>,
0383 <SYSC_IDLE_SMART_WKUP>;
0384 ti,syss-mask = <1>;
0385 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
0386 clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
0387 clock-names = "fck";
0388 #address-cells = <1>;
0389 #size-cells = <1>;
0390 ranges = <0x0 0x4b501000 0x1000>;
0391
0392 aes1: aes@0 {
0393 compatible = "ti,omap4-aes";
0394 reg = <0 0xa0>;
0395 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0396 dmas = <&sdma 111>, <&sdma 110>;
0397 dma-names = "tx", "rx";
0398 };
0399 };
0400
0401 aes2_target: target-module@4b701000 {
0402 compatible = "ti,sysc-omap2", "ti,sysc";
0403 reg = <0x4b701080 0x4>,
0404 <0x4b701084 0x4>,
0405 <0x4b701088 0x4>;
0406 reg-names = "rev", "sysc", "syss";
0407 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
0408 SYSC_OMAP2_AUTOIDLE)>;
0409 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0410 <SYSC_IDLE_NO>,
0411 <SYSC_IDLE_SMART>,
0412 <SYSC_IDLE_SMART_WKUP>;
0413 ti,syss-mask = <1>;
0414 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
0415 clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
0416 clock-names = "fck";
0417 #address-cells = <1>;
0418 #size-cells = <1>;
0419 ranges = <0x0 0x4b701000 0x1000>;
0420
0421 aes2: aes@0 {
0422 compatible = "ti,omap4-aes";
0423 reg = <0 0xa0>;
0424 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
0425 dmas = <&sdma 114>, <&sdma 113>;
0426 dma-names = "tx", "rx";
0427 };
0428 };
0429
0430 sham_target: target-module@4b100000 {
0431 compatible = "ti,sysc-omap3-sham", "ti,sysc";
0432 reg = <0x4b100100 0x4>,
0433 <0x4b100110 0x4>,
0434 <0x4b100114 0x4>;
0435 reg-names = "rev", "sysc", "syss";
0436 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
0437 SYSC_OMAP2_AUTOIDLE)>;
0438 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0439 <SYSC_IDLE_NO>,
0440 <SYSC_IDLE_SMART>;
0441 ti,syss-mask = <1>;
0442 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
0443 clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
0444 clock-names = "fck";
0445 #address-cells = <1>;
0446 #size-cells = <1>;
0447 ranges = <0x0 0x4b100000 0x1000>;
0448
0449 sham: sham@0 {
0450 compatible = "ti,omap4-sham";
0451 reg = <0 0x300>;
0452 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0453 dmas = <&sdma 119>;
0454 dma-names = "rx";
0455 };
0456 };
0457
0458 abb_mpu: regulator-abb-mpu {
0459 compatible = "ti,abb-v2";
0460 regulator-name = "abb_mpu";
0461 #address-cells = <0>;
0462 #size-cells = <0>;
0463 ti,tranxdone-status-mask = <0x80>;
0464 clocks = <&sys_clkin_ck>;
0465 ti,settling-time = <50>;
0466 ti,clock-cycles = <16>;
0467
0468 status = "disabled";
0469 };
0470
0471 abb_iva: regulator-abb-iva {
0472 compatible = "ti,abb-v2";
0473 regulator-name = "abb_iva";
0474 #address-cells = <0>;
0475 #size-cells = <0>;
0476 ti,tranxdone-status-mask = <0x80000000>;
0477 clocks = <&sys_clkin_ck>;
0478 ti,settling-time = <50>;
0479 ti,clock-cycles = <16>;
0480
0481 status = "disabled";
0482 };
0483
0484 sgx_module: target-module@56000000 {
0485 compatible = "ti,sysc-omap4", "ti,sysc";
0486 reg = <0x5600fe00 0x4>,
0487 <0x5600fe10 0x4>;
0488 reg-names = "rev", "sysc";
0489 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0490 <SYSC_IDLE_NO>,
0491 <SYSC_IDLE_SMART>,
0492 <SYSC_IDLE_SMART_WKUP>;
0493 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0494 <SYSC_IDLE_NO>,
0495 <SYSC_IDLE_SMART>,
0496 <SYSC_IDLE_SMART_WKUP>;
0497 power-domains = <&prm_gfx>;
0498 clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
0499 clock-names = "fck";
0500 #address-cells = <1>;
0501 #size-cells = <1>;
0502 ranges = <0 0x56000000 0x2000000>;
0503
0504 /*
0505 * Closed source PowerVR driver, no child device
0506 * binding or driver in mainline
0507 */
0508 };
0509
0510 /*
0511 * DSS is only using l3 mapping without l4 as noted in the TRM
0512 * "10.1.3 DSS Register Manual" for omap4460.
0513 */
0514 target-module@58000000 {
0515 compatible = "ti,sysc-omap2", "ti,sysc";
0516 reg = <0x58000000 4>,
0517 <0x58000014 4>;
0518 reg-names = "rev", "syss";
0519 ti,syss-mask = <1>;
0520 power-domains = <&prm_dss>;
0521 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
0522 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
0523 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
0524 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
0525 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
0526 #address-cells = <1>;
0527 #size-cells = <1>;
0528 ranges = <0 0x58000000 0x1000000>;
0529
0530 dss: dss@0 {
0531 compatible = "ti,omap4-dss";
0532 reg = <0 0x80>;
0533 status = "disabled";
0534 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
0535 clock-names = "fck";
0536 #address-cells = <1>;
0537 #size-cells = <1>;
0538 ranges = <0 0 0x1000000>;
0539
0540 target-module@1000 {
0541 compatible = "ti,sysc-omap2", "ti,sysc";
0542 reg = <0x1000 0x4>,
0543 <0x1010 0x4>,
0544 <0x1014 0x4>;
0545 reg-names = "rev", "sysc", "syss";
0546 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0547 <SYSC_IDLE_NO>,
0548 <SYSC_IDLE_SMART>;
0549 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0550 <SYSC_IDLE_NO>,
0551 <SYSC_IDLE_SMART>;
0552 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0553 SYSC_OMAP2_ENAWAKEUP |
0554 SYSC_OMAP2_SOFTRESET |
0555 SYSC_OMAP2_AUTOIDLE)>;
0556 ti,syss-mask = <1>;
0557 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
0558 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
0559 clock-names = "fck", "sys_clk";
0560 #address-cells = <1>;
0561 #size-cells = <1>;
0562 ranges = <0 0x1000 0x1000>;
0563
0564 dispc@0 {
0565 compatible = "ti,omap4-dispc";
0566 reg = <0 0x1000>;
0567 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0568 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
0569 clock-names = "fck";
0570 };
0571 };
0572
0573 target-module@2000 {
0574 compatible = "ti,sysc-omap2", "ti,sysc";
0575 reg = <0x2000 0x4>,
0576 <0x2010 0x4>,
0577 <0x2014 0x4>;
0578 reg-names = "rev", "sysc", "syss";
0579 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0580 <SYSC_IDLE_NO>,
0581 <SYSC_IDLE_SMART>;
0582 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
0583 SYSC_OMAP2_AUTOIDLE)>;
0584 ti,syss-mask = <1>;
0585 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
0586 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
0587 clock-names = "fck", "sys_clk";
0588 #address-cells = <1>;
0589 #size-cells = <1>;
0590 ranges = <0 0x2000 0x1000>;
0591
0592 rfbi: encoder@0 {
0593 reg = <0 0x1000>;
0594 status = "disabled";
0595 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
0596 clock-names = "fck", "ick";
0597 };
0598 };
0599
0600 target-module@3000 {
0601 compatible = "ti,sysc-omap2", "ti,sysc";
0602 reg = <0x3000 0x4>;
0603 reg-names = "rev";
0604 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
0605 clock-names = "sys_clk";
0606 #address-cells = <1>;
0607 #size-cells = <1>;
0608 ranges = <0 0x3000 0x1000>;
0609
0610 venc: encoder@0 {
0611 compatible = "ti,omap4-venc";
0612 reg = <0 0x1000>;
0613 status = "disabled";
0614 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
0615 clock-names = "fck";
0616 };
0617 };
0618
0619 target-module@4000 {
0620 compatible = "ti,sysc-omap2", "ti,sysc";
0621 reg = <0x4000 0x4>,
0622 <0x4010 0x4>,
0623 <0x4014 0x4>;
0624 reg-names = "rev", "sysc", "syss";
0625 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0626 <SYSC_IDLE_NO>,
0627 <SYSC_IDLE_SMART>;
0628 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0629 SYSC_OMAP2_ENAWAKEUP |
0630 SYSC_OMAP2_SOFTRESET |
0631 SYSC_OMAP2_AUTOIDLE)>;
0632 ti,syss-mask = <1>;
0633 #address-cells = <1>;
0634 #size-cells = <1>;
0635 ranges = <0 0x4000 0x1000>;
0636
0637 dsi1: encoder@0 {
0638 compatible = "ti,omap4-dsi";
0639 reg = <0 0x200>,
0640 <0x200 0x40>,
0641 <0x300 0x20>;
0642 reg-names = "proto", "phy", "pll";
0643 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0644 status = "disabled";
0645 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
0646 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
0647 clock-names = "fck", "sys_clk";
0648
0649 #address-cells = <1>;
0650 #size-cells = <0>;
0651 };
0652 };
0653
0654 target-module@5000 {
0655 compatible = "ti,sysc-omap2", "ti,sysc";
0656 reg = <0x5000 0x4>,
0657 <0x5010 0x4>,
0658 <0x5014 0x4>;
0659 reg-names = "rev", "sysc", "syss";
0660 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0661 <SYSC_IDLE_NO>,
0662 <SYSC_IDLE_SMART>;
0663 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
0664 SYSC_OMAP2_ENAWAKEUP |
0665 SYSC_OMAP2_SOFTRESET |
0666 SYSC_OMAP2_AUTOIDLE)>;
0667 ti,syss-mask = <1>;
0668 #address-cells = <1>;
0669 #size-cells = <1>;
0670 ranges = <0 0x5000 0x1000>;
0671
0672 dsi2: encoder@0 {
0673 compatible = "ti,omap4-dsi";
0674 reg = <0 0x200>,
0675 <0x200 0x40>,
0676 <0x300 0x20>;
0677 reg-names = "proto", "phy", "pll";
0678 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0679 status = "disabled";
0680 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
0681 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
0682 clock-names = "fck", "sys_clk";
0683
0684 #address-cells = <1>;
0685 #size-cells = <0>;
0686 };
0687 };
0688
0689 target-module@6000 {
0690 compatible = "ti,sysc-omap4", "ti,sysc";
0691 reg = <0x6000 0x4>,
0692 <0x6010 0x4>;
0693 reg-names = "rev", "sysc";
0694 /*
0695 * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
0696 * but HDMI audio will fail with them.
0697 */
0698 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0699 <SYSC_IDLE_NO>;
0700 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
0701 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
0702 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
0703 clock-names = "fck", "dss_clk";
0704 #address-cells = <1>;
0705 #size-cells = <1>;
0706 ranges = <0 0x6000 0x2000>;
0707
0708 hdmi: encoder@0 {
0709 compatible = "ti,omap4-hdmi";
0710 reg = <0 0x200>,
0711 <0x200 0x100>,
0712 <0x300 0x100>,
0713 <0x400 0x1000>;
0714 reg-names = "wp", "pll", "phy", "core";
0715 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
0716 status = "disabled";
0717 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
0718 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
0719 clock-names = "fck", "sys_clk";
0720 dmas = <&sdma 76>;
0721 dma-names = "audio_tx";
0722 };
0723 };
0724 };
0725 };
0726
0727 iva_hd_target: target-module@5a000000 {
0728 compatible = "ti,sysc-omap4", "ti,sysc";
0729 reg = <0x5a05a400 0x4>,
0730 <0x5a05a410 0x4>;
0731 reg-names = "rev", "sysc";
0732 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0733 <SYSC_IDLE_NO>,
0734 <SYSC_IDLE_SMART>;
0735 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0736 <SYSC_IDLE_NO>,
0737 <SYSC_IDLE_SMART>;
0738 power-domains = <&prm_ivahd>;
0739 resets = <&prm_ivahd 2>;
0740 reset-names = "rstctrl";
0741 clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>;
0742 clock-names = "fck";
0743 #address-cells = <1>;
0744 #size-cells = <1>;
0745 ranges = <0x5a000000 0x5a000000 0x1000000>,
0746 <0x5b000000 0x5b000000 0x1000000>;
0747
0748 iva {
0749 compatible = "ti,ivahd";
0750 };
0751 };
0752 };
0753 };
0754
0755 #include "omap4-l4.dtsi"
0756 #include "omap4-l4-abe.dtsi"
0757 #include "omap44xx-clocks.dtsi"
0758
0759 &prm {
0760 prm_mpu: prm@300 {
0761 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
0762 reg = <0x300 0x100>;
0763 #power-domain-cells = <0>;
0764 };
0765
0766 prm_tesla: prm@400 {
0767 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
0768 reg = <0x400 0x100>;
0769 #reset-cells = <1>;
0770 #power-domain-cells = <0>;
0771 };
0772
0773 prm_abe: prm@500 {
0774 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
0775 reg = <0x500 0x100>;
0776 #power-domain-cells = <0>;
0777 };
0778
0779 prm_always_on_core: prm@600 {
0780 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
0781 reg = <0x600 0x100>;
0782 #power-domain-cells = <0>;
0783 };
0784
0785 prm_core: prm@700 {
0786 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
0787 reg = <0x700 0x100>;
0788 #reset-cells = <1>;
0789 #power-domain-cells = <0>;
0790 };
0791
0792 prm_ivahd: prm@f00 {
0793 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
0794 reg = <0xf00 0x100>;
0795 #reset-cells = <1>;
0796 #power-domain-cells = <0>;
0797 };
0798
0799 prm_cam: prm@1000 {
0800 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
0801 reg = <0x1000 0x100>;
0802 #power-domain-cells = <0>;
0803 };
0804
0805 prm_dss: prm@1100 {
0806 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
0807 reg = <0x1100 0x100>;
0808 #power-domain-cells = <0>;
0809 };
0810
0811 prm_gfx: prm@1200 {
0812 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
0813 reg = <0x1200 0x100>;
0814 #power-domain-cells = <0>;
0815 };
0816
0817 prm_l3init: prm@1300 {
0818 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
0819 reg = <0x1300 0x100>;
0820 #power-domain-cells = <0>;
0821 };
0822
0823 prm_l4per: prm@1400 {
0824 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
0825 reg = <0x1400 0x100>;
0826 #power-domain-cells = <0>;
0827 };
0828
0829 prm_cefuse: prm@1600 {
0830 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
0831 reg = <0x1600 0x100>;
0832 #power-domain-cells = <0>;
0833 };
0834
0835 prm_wkup: prm@1700 {
0836 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
0837 reg = <0x1700 0x100>;
0838 #power-domain-cells = <0>;
0839 };
0840
0841 prm_emu: prm@1900 {
0842 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
0843 reg = <0x1900 0x100>;
0844 #power-domain-cells = <0>;
0845 };
0846
0847 prm_dss: prm@1100 {
0848 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
0849 reg = <0x1100 0x40>;
0850 #power-domain-cells = <0>;
0851 };
0852
0853 prm_device: prm@1b00 {
0854 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
0855 reg = <0x1b00 0x40>;
0856 #reset-cells = <1>;
0857 };
0858 };
0859
0860 /* Preferred always-on timer for clockevent */
0861 &timer1_target {
0862 ti,no-reset-on-init;
0863 ti,no-idle;
0864 timer@0 {
0865 assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
0866 assigned-clock-parents = <&sys_32k_ck>;
0867 };
0868 };
