0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for OMAP3 clock data
0004 *
0005 * Copyright (C) 2013 Texas Instruments, Inc.
0006 */
0007 &prm_clocks {
0008 virt_16_8m_ck: virt_16_8m_ck {
0009 #clock-cells = <0>;
0010 compatible = "fixed-clock";
0011 clock-frequency = <16800000>;
0012 };
0013
0014 osc_sys_ck: osc_sys_ck@d40 {
0015 #clock-cells = <0>;
0016 compatible = "ti,mux-clock";
0017 clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
0018 reg = <0x0d40>;
0019 };
0020
0021 sys_ck: sys_ck@1270 {
0022 #clock-cells = <0>;
0023 compatible = "ti,divider-clock";
0024 clocks = <&osc_sys_ck>;
0025 ti,bit-shift = <6>;
0026 ti,max-div = <3>;
0027 reg = <0x1270>;
0028 ti,index-starts-at-one;
0029 };
0030
0031 sys_clkout1: sys_clkout1@d70 {
0032 #clock-cells = <0>;
0033 compatible = "ti,gate-clock";
0034 clocks = <&osc_sys_ck>;
0035 reg = <0x0d70>;
0036 ti,bit-shift = <7>;
0037 };
0038
0039 dpll3_x2_ck: dpll3_x2_ck {
0040 #clock-cells = <0>;
0041 compatible = "fixed-factor-clock";
0042 clocks = <&dpll3_ck>;
0043 clock-mult = <2>;
0044 clock-div = <1>;
0045 };
0046
0047 dpll3_m2x2_ck: dpll3_m2x2_ck {
0048 #clock-cells = <0>;
0049 compatible = "fixed-factor-clock";
0050 clocks = <&dpll3_m2_ck>;
0051 clock-mult = <2>;
0052 clock-div = <1>;
0053 };
0054
0055 dpll4_x2_ck: dpll4_x2_ck {
0056 #clock-cells = <0>;
0057 compatible = "fixed-factor-clock";
0058 clocks = <&dpll4_ck>;
0059 clock-mult = <2>;
0060 clock-div = <1>;
0061 };
0062
0063 corex2_fck: corex2_fck {
0064 #clock-cells = <0>;
0065 compatible = "fixed-factor-clock";
0066 clocks = <&dpll3_m2x2_ck>;
0067 clock-mult = <1>;
0068 clock-div = <1>;
0069 };
0070
0071 wkup_l4_ick: wkup_l4_ick {
0072 #clock-cells = <0>;
0073 compatible = "fixed-factor-clock";
0074 clocks = <&sys_ck>;
0075 clock-mult = <1>;
0076 clock-div = <1>;
0077 };
0078 };
0079
0080 &scm_clocks {
0081 /* CONTROL_DEVCONF1 */
0082 clock@68 {
0083 compatible = "ti,clksel";
0084 reg = <0x68>;
0085 #clock-cells = <2>;
0086 #address-cells = <0>;
0087
0088 mcbsp5_mux_fck: clock-mcbsp5-mux-fck {
0089 #clock-cells = <0>;
0090 compatible = "ti,composite-mux-clock";
0091 clock-output-names = "mcbsp5_mux_fck";
0092 clocks = <&core_96m_fck>, <&mcbsp_clks>;
0093 ti,bit-shift = <4>;
0094 };
0095
0096 mcbsp3_mux_fck: clock-mcbsp3-mux-fck {
0097 #clock-cells = <0>;
0098 compatible = "ti,composite-mux-clock";
0099 clock-output-names = "mcbsp3_mux_fck";
0100 clocks = <&per_96m_fck>, <&mcbsp_clks>;
0101 };
0102
0103 mcbsp4_mux_fck: clock-mcbsp4-mux-fck {
0104 #clock-cells = <0>;
0105 compatible = "ti,composite-mux-clock";
0106 clock-output-names = "mcbsp4_mux_fck";
0107 clocks = <&per_96m_fck>, <&mcbsp_clks>;
0108 ti,bit-shift = <2>;
0109 };
0110 };
0111
0112 mcbsp5_fck: mcbsp5_fck {
0113 #clock-cells = <0>;
0114 compatible = "ti,composite-clock";
0115 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
0116 };
0117
0118 /* CONTROL_DEVCONF0 */
0119 clock@4 {
0120 compatible = "ti,clksel";
0121 reg = <0x4>;
0122 #clock-cells = <2>;
0123 #address-cells = <0>;
0124
0125 mcbsp1_mux_fck: clock-mcbsp1-mux-fck {
0126 #clock-cells = <0>;
0127 compatible = "ti,composite-mux-clock";
0128 clock-output-names = "mcbsp1_mux_fck";
0129 clocks = <&core_96m_fck>, <&mcbsp_clks>;
0130 ti,bit-shift = <2>;
0131 };
0132
0133 mcbsp2_mux_fck: clock-mcbsp2-mux-fck {
0134 #clock-cells = <0>;
0135 compatible = "ti,composite-mux-clock";
0136 clock-output-names = "mcbsp2_mux_fck";
0137 clocks = <&per_96m_fck>, <&mcbsp_clks>;
0138 ti,bit-shift = <6>;
0139 };
0140 };
0141
0142 mcbsp1_fck: mcbsp1_fck {
0143 #clock-cells = <0>;
0144 compatible = "ti,composite-clock";
0145 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
0146 };
0147
0148 mcbsp2_fck: mcbsp2_fck {
0149 #clock-cells = <0>;
0150 compatible = "ti,composite-clock";
0151 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
0152 };
0153
0154 mcbsp3_fck: mcbsp3_fck {
0155 #clock-cells = <0>;
0156 compatible = "ti,composite-clock";
0157 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
0158 };
0159
0160 mcbsp4_fck: mcbsp4_fck {
0161 #clock-cells = <0>;
0162 compatible = "ti,composite-clock";
0163 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
0164 };
0165 };
0166 &cm_clocks {
0167 dummy_apb_pclk: dummy_apb_pclk {
0168 #clock-cells = <0>;
0169 compatible = "fixed-clock";
0170 clock-frequency = <0x0>;
0171 };
0172
0173 omap_32k_fck: omap_32k_fck {
0174 #clock-cells = <0>;
0175 compatible = "fixed-clock";
0176 clock-frequency = <32768>;
0177 };
0178
0179 virt_12m_ck: virt_12m_ck {
0180 #clock-cells = <0>;
0181 compatible = "fixed-clock";
0182 clock-frequency = <12000000>;
0183 };
0184
0185 virt_13m_ck: virt_13m_ck {
0186 #clock-cells = <0>;
0187 compatible = "fixed-clock";
0188 clock-frequency = <13000000>;
0189 };
0190
0191 virt_19200000_ck: virt_19200000_ck {
0192 #clock-cells = <0>;
0193 compatible = "fixed-clock";
0194 clock-frequency = <19200000>;
0195 };
0196
0197 virt_26000000_ck: virt_26000000_ck {
0198 #clock-cells = <0>;
0199 compatible = "fixed-clock";
0200 clock-frequency = <26000000>;
0201 };
0202
0203 virt_38_4m_ck: virt_38_4m_ck {
0204 #clock-cells = <0>;
0205 compatible = "fixed-clock";
0206 clock-frequency = <38400000>;
0207 };
0208
0209 dpll4_ck: dpll4_ck@d00 {
0210 #clock-cells = <0>;
0211 compatible = "ti,omap3-dpll-per-clock";
0212 clocks = <&sys_ck>, <&sys_ck>;
0213 reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
0214 };
0215
0216 dpll4_m2_ck: dpll4_m2_ck@d48 {
0217 #clock-cells = <0>;
0218 compatible = "ti,divider-clock";
0219 clocks = <&dpll4_ck>;
0220 ti,max-div = <63>;
0221 reg = <0x0d48>;
0222 ti,index-starts-at-one;
0223 };
0224
0225 dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
0226 #clock-cells = <0>;
0227 compatible = "fixed-factor-clock";
0228 clocks = <&dpll4_m2_ck>;
0229 clock-mult = <2>;
0230 clock-div = <1>;
0231 };
0232
0233 dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
0234 #clock-cells = <0>;
0235 compatible = "ti,gate-clock";
0236 clocks = <&dpll4_m2x2_mul_ck>;
0237 ti,bit-shift = <0x1b>;
0238 reg = <0x0d00>;
0239 ti,set-bit-to-disable;
0240 };
0241
0242 omap_96m_alwon_fck: omap_96m_alwon_fck {
0243 #clock-cells = <0>;
0244 compatible = "fixed-factor-clock";
0245 clocks = <&dpll4_m2x2_ck>;
0246 clock-mult = <1>;
0247 clock-div = <1>;
0248 };
0249
0250 dpll3_ck: dpll3_ck@d00 {
0251 #clock-cells = <0>;
0252 compatible = "ti,omap3-dpll-core-clock";
0253 clocks = <&sys_ck>, <&sys_ck>;
0254 reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
0255 };
0256
0257 /* CM_CLKSEL1_EMU */
0258 clock@1140 {
0259 compatible = "ti,clksel";
0260 reg = <0x1140>;
0261 #clock-cells = <2>;
0262 #address-cells = <0>;
0263
0264 dpll3_m3_ck: clock-dpll3-m3 {
0265 #clock-cells = <0>;
0266 compatible = "ti,divider-clock";
0267 clock-output-names = "dpll3_m3_ck";
0268 clocks = <&dpll3_ck>;
0269 ti,bit-shift = <16>;
0270 ti,max-div = <31>;
0271 ti,index-starts-at-one;
0272 };
0273
0274 dpll4_m6_ck: clock-dpll4-m6 {
0275 #clock-cells = <0>;
0276 compatible = "ti,divider-clock";
0277 clock-output-names = "dpll4_m6_ck";
0278 clocks = <&dpll4_ck>;
0279 ti,bit-shift = <24>;
0280 ti,max-div = <63>;
0281 ti,index-starts-at-one;
0282 };
0283
0284 emu_src_mux_ck: clock-emu-src-mux {
0285 #clock-cells = <0>;
0286 compatible = "ti,mux-clock";
0287 clock-output-names = "emu_src_mux_ck";
0288 clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
0289 };
0290
0291 pclk_fck: clock-pclk-fck {
0292 #clock-cells = <0>;
0293 compatible = "ti,divider-clock";
0294 clock-output-names = "pclk_fck";
0295 clocks = <&emu_src_ck>;
0296 ti,bit-shift = <8>;
0297 ti,max-div = <7>;
0298 ti,index-starts-at-one;
0299 };
0300
0301 pclkx2_fck: clock-pclkx2-fck {
0302 #clock-cells = <0>;
0303 compatible = "ti,divider-clock";
0304 clock-output-names = "pclkx2_fck";
0305 clocks = <&emu_src_ck>;
0306 ti,bit-shift = <6>;
0307 ti,max-div = <3>;
0308 ti,index-starts-at-one;
0309 };
0310
0311 atclk_fck: clock-atclk-fck {
0312 #clock-cells = <0>;
0313 compatible = "ti,divider-clock";
0314 clock-output-names = "atclk_fck";
0315 clocks = <&emu_src_ck>;
0316 ti,bit-shift = <4>;
0317 ti,max-div = <3>;
0318 ti,index-starts-at-one;
0319 };
0320
0321 traceclk_src_fck: clock-traceclk-src-fck {
0322 #clock-cells = <0>;
0323 compatible = "ti,mux-clock";
0324 clock-output-names = "traceclk_src_fck";
0325 clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
0326 ti,bit-shift = <2>;
0327 };
0328
0329 traceclk_fck: clock-traceclk-fck {
0330 #clock-cells = <0>;
0331 compatible = "ti,divider-clock";
0332 clock-output-names = "traceclk_fck";
0333 clocks = <&traceclk_src_fck>;
0334 ti,bit-shift = <11>;
0335 ti,max-div = <7>;
0336 ti,index-starts-at-one;
0337 };
0338 };
0339
0340 dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
0341 #clock-cells = <0>;
0342 compatible = "fixed-factor-clock";
0343 clocks = <&dpll3_m3_ck>;
0344 clock-mult = <2>;
0345 clock-div = <1>;
0346 };
0347
0348 dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
0349 #clock-cells = <0>;
0350 compatible = "ti,gate-clock";
0351 clocks = <&dpll3_m3x2_mul_ck>;
0352 ti,bit-shift = <0xc>;
0353 reg = <0x0d00>;
0354 ti,set-bit-to-disable;
0355 };
0356
0357 emu_core_alwon_ck: emu_core_alwon_ck {
0358 #clock-cells = <0>;
0359 compatible = "fixed-factor-clock";
0360 clocks = <&dpll3_m3x2_ck>;
0361 clock-mult = <1>;
0362 clock-div = <1>;
0363 };
0364
0365 sys_altclk: sys_altclk {
0366 #clock-cells = <0>;
0367 compatible = "fixed-clock";
0368 clock-frequency = <0x0>;
0369 };
0370
0371 mcbsp_clks: mcbsp_clks {
0372 #clock-cells = <0>;
0373 compatible = "fixed-clock";
0374 clock-frequency = <0x0>;
0375 };
0376
0377 core_ck: core_ck {
0378 #clock-cells = <0>;
0379 compatible = "fixed-factor-clock";
0380 clocks = <&dpll3_m2_ck>;
0381 clock-mult = <1>;
0382 clock-div = <1>;
0383 };
0384
0385 dpll1_fck: dpll1_fck@940 {
0386 #clock-cells = <0>;
0387 compatible = "ti,divider-clock";
0388 clocks = <&core_ck>;
0389 ti,bit-shift = <19>;
0390 ti,max-div = <7>;
0391 reg = <0x0940>;
0392 ti,index-starts-at-one;
0393 };
0394
0395 dpll1_ck: dpll1_ck@904 {
0396 #clock-cells = <0>;
0397 compatible = "ti,omap3-dpll-clock";
0398 clocks = <&sys_ck>, <&dpll1_fck>;
0399 reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>;
0400 };
0401
0402 dpll1_x2_ck: dpll1_x2_ck {
0403 #clock-cells = <0>;
0404 compatible = "fixed-factor-clock";
0405 clocks = <&dpll1_ck>;
0406 clock-mult = <2>;
0407 clock-div = <1>;
0408 };
0409
0410 dpll1_x2m2_ck: dpll1_x2m2_ck@944 {
0411 #clock-cells = <0>;
0412 compatible = "ti,divider-clock";
0413 clocks = <&dpll1_x2_ck>;
0414 ti,max-div = <31>;
0415 reg = <0x0944>;
0416 ti,index-starts-at-one;
0417 };
0418
0419 cm_96m_fck: cm_96m_fck {
0420 #clock-cells = <0>;
0421 compatible = "fixed-factor-clock";
0422 clocks = <&omap_96m_alwon_fck>;
0423 clock-mult = <1>;
0424 clock-div = <1>;
0425 };
0426
0427 /* CM_CLKSEL1_PLL */
0428 clock@d40 {
0429 compatible = "ti,clksel";
0430 reg = <0xd40>;
0431 #clock-cells = <2>;
0432 #address-cells = <0>;
0433
0434 dpll3_m2_ck: clock-dpll3-m2 {
0435 #clock-cells = <0>;
0436 compatible = "ti,divider-clock";
0437 clock-output-names = "dpll3_m2_ck";
0438 clocks = <&dpll3_ck>;
0439 ti,bit-shift = <27>;
0440 ti,max-div = <31>;
0441 ti,index-starts-at-one;
0442 };
0443
0444 omap_96m_fck: clock-omap-96m-fck {
0445 #clock-cells = <0>;
0446 compatible = "ti,mux-clock";
0447 clock-output-names = "omap_96m_fck";
0448 clocks = <&cm_96m_fck>, <&sys_ck>;
0449 ti,bit-shift = <6>;
0450 };
0451
0452 omap_54m_fck: clock-omap-54m-fck {
0453 #clock-cells = <0>;
0454 compatible = "ti,mux-clock";
0455 clock-output-names = "omap_54m_fck";
0456 clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
0457 ti,bit-shift = <5>;
0458 };
0459
0460 omap_48m_fck: clock-omap-48m-fck {
0461 #clock-cells = <0>;
0462 compatible = "ti,mux-clock";
0463 clock-output-names = "omap_48m_fck";
0464 clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
0465 ti,bit-shift = <3>;
0466 };
0467 };
0468
0469 /* CM_CLKSEL_DSS */
0470 clock@e40 {
0471 compatible = "ti,clksel";
0472 reg = <0xe40>;
0473 #clock-cells = <2>;
0474 #address-cells = <0>;
0475
0476 dpll4_m3_ck: clock-dpll4-m3 {
0477 #clock-cells = <0>;
0478 compatible = "ti,divider-clock";
0479 clock-output-names = "dpll4_m3_ck";
0480 clocks = <&dpll4_ck>;
0481 ti,bit-shift = <8>;
0482 ti,max-div = <32>;
0483 ti,index-starts-at-one;
0484 };
0485
0486 dpll4_m4_ck: clock-dpll4-m4 {
0487 #clock-cells = <0>;
0488 compatible = "ti,divider-clock";
0489 clock-output-names = "dpll4_m4_ck";
0490 clocks = <&dpll4_ck>;
0491 ti,max-div = <16>;
0492 ti,index-starts-at-one;
0493 };
0494 };
0495
0496 dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
0497 #clock-cells = <0>;
0498 compatible = "fixed-factor-clock";
0499 clocks = <&dpll4_m3_ck>;
0500 clock-mult = <2>;
0501 clock-div = <1>;
0502 };
0503
0504 dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
0505 #clock-cells = <0>;
0506 compatible = "ti,gate-clock";
0507 clocks = <&dpll4_m3x2_mul_ck>;
0508 ti,bit-shift = <0x1c>;
0509 reg = <0x0d00>;
0510 ti,set-bit-to-disable;
0511 };
0512
0513 cm_96m_d2_fck: cm_96m_d2_fck {
0514 #clock-cells = <0>;
0515 compatible = "fixed-factor-clock";
0516 clocks = <&cm_96m_fck>;
0517 clock-mult = <1>;
0518 clock-div = <2>;
0519 };
0520
0521 omap_12m_fck: omap_12m_fck {
0522 #clock-cells = <0>;
0523 compatible = "fixed-factor-clock";
0524 clocks = <&omap_48m_fck>;
0525 clock-mult = <1>;
0526 clock-div = <4>;
0527 };
0528
0529 dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
0530 #clock-cells = <0>;
0531 compatible = "ti,fixed-factor-clock";
0532 clocks = <&dpll4_m4_ck>;
0533 ti,clock-mult = <2>;
0534 ti,clock-div = <1>;
0535 ti,set-rate-parent;
0536 };
0537
0538 dpll4_m4x2_ck: dpll4_m4x2_ck@d00 {
0539 #clock-cells = <0>;
0540 compatible = "ti,gate-clock";
0541 clocks = <&dpll4_m4x2_mul_ck>;
0542 ti,bit-shift = <0x1d>;
0543 reg = <0x0d00>;
0544 ti,set-bit-to-disable;
0545 ti,set-rate-parent;
0546 };
0547
0548 dpll4_m5_ck: dpll4_m5_ck@f40 {
0549 #clock-cells = <0>;
0550 compatible = "ti,divider-clock";
0551 clocks = <&dpll4_ck>;
0552 ti,max-div = <63>;
0553 reg = <0x0f40>;
0554 ti,index-starts-at-one;
0555 };
0556
0557 dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
0558 #clock-cells = <0>;
0559 compatible = "ti,fixed-factor-clock";
0560 clocks = <&dpll4_m5_ck>;
0561 ti,clock-mult = <2>;
0562 ti,clock-div = <1>;
0563 ti,set-rate-parent;
0564 };
0565
0566 dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
0567 #clock-cells = <0>;
0568 compatible = "ti,gate-clock";
0569 clocks = <&dpll4_m5x2_mul_ck>;
0570 ti,bit-shift = <0x1e>;
0571 reg = <0x0d00>;
0572 ti,set-bit-to-disable;
0573 ti,set-rate-parent;
0574 };
0575
0576 dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
0577 #clock-cells = <0>;
0578 compatible = "fixed-factor-clock";
0579 clocks = <&dpll4_m6_ck>;
0580 clock-mult = <2>;
0581 clock-div = <1>;
0582 };
0583
0584 dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
0585 #clock-cells = <0>;
0586 compatible = "ti,gate-clock";
0587 clocks = <&dpll4_m6x2_mul_ck>;
0588 ti,bit-shift = <0x1f>;
0589 reg = <0x0d00>;
0590 ti,set-bit-to-disable;
0591 };
0592
0593 emu_per_alwon_ck: emu_per_alwon_ck {
0594 #clock-cells = <0>;
0595 compatible = "fixed-factor-clock";
0596 clocks = <&dpll4_m6x2_ck>;
0597 clock-mult = <1>;
0598 clock-div = <1>;
0599 };
0600
0601 /* CM_CLKOUT_CTRL */
0602 clock@d70 {
0603 compatible = "ti,clksel";
0604 reg = <0xd70>;
0605 #clock-cells = <2>;
0606 #address-cells = <0>;
0607
0608 clkout2_src_gate_ck: clock-clkout2-src-gate {
0609 #clock-cells = <0>;
0610 compatible = "ti,composite-no-wait-gate-clock";
0611 clock-output-names = "clkout2_src_gate_ck";
0612 clocks = <&core_ck>;
0613 ti,bit-shift = <7>;
0614 };
0615
0616 clkout2_src_mux_ck: clock-clkout2-src-mux {
0617 #clock-cells = <0>;
0618 compatible = "ti,composite-mux-clock";
0619 clock-output-names = "clkout2_src_mux_ck";
0620 clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
0621 };
0622
0623 sys_clkout2: clock-sys-clkout2 {
0624 #clock-cells = <0>;
0625 compatible = "ti,divider-clock";
0626 clock-output-names = "sys_clkout2";
0627 clocks = <&clkout2_src_ck>;
0628 ti,bit-shift = <3>;
0629 ti,max-div = <64>;
0630 ti,index-power-of-two;
0631 };
0632 };
0633
0634 clkout2_src_ck: clkout2_src_ck {
0635 #clock-cells = <0>;
0636 compatible = "ti,composite-clock";
0637 clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
0638 };
0639
0640 mpu_ck: mpu_ck {
0641 #clock-cells = <0>;
0642 compatible = "fixed-factor-clock";
0643 clocks = <&dpll1_x2m2_ck>;
0644 clock-mult = <1>;
0645 clock-div = <1>;
0646 };
0647
0648 arm_fck: arm_fck@924 {
0649 #clock-cells = <0>;
0650 compatible = "ti,divider-clock";
0651 clocks = <&mpu_ck>;
0652 reg = <0x0924>;
0653 ti,max-div = <2>;
0654 };
0655
0656 emu_mpu_alwon_ck: emu_mpu_alwon_ck {
0657 #clock-cells = <0>;
0658 compatible = "fixed-factor-clock";
0659 clocks = <&mpu_ck>;
0660 clock-mult = <1>;
0661 clock-div = <1>;
0662 };
0663
0664 /* CM_CLKSEL_CORE */
0665 clock@a40 {
0666 compatible = "ti,clksel";
0667 reg = <0xa40>;
0668 #clock-cells = <2>;
0669 #address-cells = <0>;
0670
0671 l3_ick: clock-l3-ick {
0672 #clock-cells = <0>;
0673 compatible = "ti,divider-clock";
0674 clock-output-names = "l3_ick";
0675 clocks = <&core_ck>;
0676 ti,max-div = <3>;
0677 ti,index-starts-at-one;
0678 };
0679
0680 l4_ick: clock-l4-ick {
0681 #clock-cells = <0>;
0682 compatible = "ti,divider-clock";
0683 clock-output-names = "l4_ick";
0684 clocks = <&l3_ick>;
0685 ti,bit-shift = <2>;
0686 ti,max-div = <3>;
0687 ti,index-starts-at-one;
0688 };
0689
0690 gpt10_mux_fck: clock-gpt10-mux-fck {
0691 #clock-cells = <0>;
0692 compatible = "ti,composite-mux-clock";
0693 clock-output-names = "gpt10_mux_fck";
0694 clocks = <&omap_32k_fck>, <&sys_ck>;
0695 ti,bit-shift = <6>;
0696 };
0697
0698 gpt11_mux_fck: clock-gpt11-mux-fck {
0699 #clock-cells = <0>;
0700 compatible = "ti,composite-mux-clock";
0701 clock-output-names = "gpt11_mux_fck";
0702 clocks = <&omap_32k_fck>, <&sys_ck>;
0703 ti,bit-shift = <7>;
0704 };
0705 };
0706
0707 /* CM_CLKSEL_WKUP */
0708 clock@c40 {
0709 compatible = "ti,clksel";
0710 reg = <0xc40>;
0711 #clock-cells = <2>;
0712 #address-cells = <0>;
0713
0714 rm_ick: clock-rm-ick {
0715 #clock-cells = <0>;
0716 compatible = "ti,divider-clock";
0717 clock-output-names = "rm_ick";
0718 clocks = <&l4_ick>;
0719 ti,bit-shift = <1>;
0720 ti,max-div = <3>;
0721 ti,index-starts-at-one;
0722 };
0723
0724 gpt1_mux_fck: clock-gpt1-mux-fck {
0725 #clock-cells = <0>;
0726 compatible = "ti,composite-mux-clock";
0727 clock-output-names = "gpt1_mux_fck";
0728 clocks = <&omap_32k_fck>, <&sys_ck>;
0729 };
0730 };
0731
0732 /* CM_FCLKEN1_CORE */
0733 clock@a00 {
0734 compatible = "ti,clksel";
0735 reg = <0xa00>;
0736 #clock-cells = <2>;
0737 #address-cells = <0>;
0738
0739 gpt10_gate_fck: clock-gpt10-gate-fck {
0740 #clock-cells = <0>;
0741 compatible = "ti,composite-gate-clock";
0742 clock-output-names = "gpt10_gate_fck";
0743 clocks = <&sys_ck>;
0744 ti,bit-shift = <11>;
0745 };
0746
0747 gpt11_gate_fck: clock-gpt11-gate-fck {
0748 #clock-cells = <0>;
0749 compatible = "ti,composite-gate-clock";
0750 clock-output-names = "gpt11_gate_fck";
0751 clocks = <&sys_ck>;
0752 ti,bit-shift = <12>;
0753 };
0754
0755 mmchs2_fck: clock-mmchs2-fck {
0756 #clock-cells = <0>;
0757 compatible = "ti,wait-gate-clock";
0758 clock-output-names = "mmchs2_fck";
0759 clocks = <&core_96m_fck>;
0760 ti,bit-shift = <25>;
0761 };
0762
0763 mmchs1_fck: clock-mmchs1-fck {
0764 #clock-cells = <0>;
0765 compatible = "ti,wait-gate-clock";
0766 clock-output-names = "mmchs1_fck";
0767 clocks = <&core_96m_fck>;
0768 ti,bit-shift = <24>;
0769 };
0770
0771 i2c3_fck: clock-i2c3-fck {
0772 #clock-cells = <0>;
0773 compatible = "ti,wait-gate-clock";
0774 clock-output-names = "i2c3_fck";
0775 clocks = <&core_96m_fck>;
0776 ti,bit-shift = <17>;
0777 };
0778
0779 i2c2_fck: clock-i2c2-fck {
0780 #clock-cells = <0>;
0781 compatible = "ti,wait-gate-clock";
0782 clock-output-names = "i2c2_fck";
0783 clocks = <&core_96m_fck>;
0784 ti,bit-shift = <16>;
0785 };
0786
0787 i2c1_fck: clock-i2c1-fck {
0788 #clock-cells = <0>;
0789 compatible = "ti,wait-gate-clock";
0790 clock-output-names = "i2c1_fck";
0791 clocks = <&core_96m_fck>;
0792 ti,bit-shift = <15>;
0793 };
0794
0795 mcbsp5_gate_fck: clock-mcbsp5-gate-fck {
0796 #clock-cells = <0>;
0797 compatible = "ti,composite-gate-clock";
0798 clock-output-names = "mcbsp5_gate_fck";
0799 clocks = <&mcbsp_clks>;
0800 ti,bit-shift = <10>;
0801 };
0802
0803 mcbsp1_gate_fck: clock-mcbsp1-gate-fck {
0804 #clock-cells = <0>;
0805 compatible = "ti,composite-gate-clock";
0806 clock-output-names = "mcbsp1_gate_fck";
0807 clocks = <&mcbsp_clks>;
0808 ti,bit-shift = <9>;
0809 };
0810
0811 mcspi4_fck: clock-mcspi4-fck {
0812 #clock-cells = <0>;
0813 compatible = "ti,wait-gate-clock";
0814 clock-output-names = "mcspi4_fck";
0815 clocks = <&core_48m_fck>;
0816 ti,bit-shift = <21>;
0817 };
0818
0819 mcspi3_fck: clock-mcspi3-fck {
0820 #clock-cells = <0>;
0821 compatible = "ti,wait-gate-clock";
0822 clock-output-names = "mcspi3_fck";
0823 clocks = <&core_48m_fck>;
0824 ti,bit-shift = <20>;
0825 };
0826
0827 mcspi2_fck: clock-mcspi2-fck {
0828 #clock-cells = <0>;
0829 compatible = "ti,wait-gate-clock";
0830 clock-output-names = "mcspi2_fck";
0831 clocks = <&core_48m_fck>;
0832 ti,bit-shift = <19>;
0833 };
0834
0835 mcspi1_fck: clock-mcspi1-fck {
0836 #clock-cells = <0>;
0837 compatible = "ti,wait-gate-clock";
0838 clock-output-names = "mcspi1_fck";
0839 clocks = <&core_48m_fck>;
0840 ti,bit-shift = <18>;
0841 };
0842
0843 uart2_fck: clock-uart2-fck {
0844 #clock-cells = <0>;
0845 compatible = "ti,wait-gate-clock";
0846 clock-output-names = "uart2_fck";
0847 clocks = <&core_48m_fck>;
0848 ti,bit-shift = <14>;
0849 };
0850
0851 uart1_fck: clock-uart1-fck {
0852 #clock-cells = <0>;
0853 compatible = "ti,wait-gate-clock";
0854 clock-output-names = "uart1_fck";
0855 clocks = <&core_48m_fck>;
0856 ti,bit-shift = <13>;
0857 };
0858
0859 hdq_fck: clock-hdq-fck {
0860 #clock-cells = <0>;
0861 compatible = "ti,wait-gate-clock";
0862 clock-output-names = "hdq_fck";
0863 clocks = <&core_12m_fck>;
0864 ti,bit-shift = <22>;
0865 };
0866 };
0867
0868 gpt10_fck: gpt10_fck {
0869 #clock-cells = <0>;
0870 compatible = "ti,composite-clock";
0871 clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
0872 };
0873
0874 gpt11_fck: gpt11_fck {
0875 #clock-cells = <0>;
0876 compatible = "ti,composite-clock";
0877 clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
0878 };
0879
0880 core_96m_fck: core_96m_fck {
0881 #clock-cells = <0>;
0882 compatible = "fixed-factor-clock";
0883 clocks = <&omap_96m_fck>;
0884 clock-mult = <1>;
0885 clock-div = <1>;
0886 };
0887
0888 core_48m_fck: core_48m_fck {
0889 #clock-cells = <0>;
0890 compatible = "fixed-factor-clock";
0891 clocks = <&omap_48m_fck>;
0892 clock-mult = <1>;
0893 clock-div = <1>;
0894 };
0895
0896 core_12m_fck: core_12m_fck {
0897 #clock-cells = <0>;
0898 compatible = "fixed-factor-clock";
0899 clocks = <&omap_12m_fck>;
0900 clock-mult = <1>;
0901 clock-div = <1>;
0902 };
0903
0904 core_l3_ick: core_l3_ick {
0905 #clock-cells = <0>;
0906 compatible = "fixed-factor-clock";
0907 clocks = <&l3_ick>;
0908 clock-mult = <1>;
0909 clock-div = <1>;
0910 };
0911
0912 /* CM_ICLKEN1_CORE */
0913 clock@a10 {
0914 compatible = "ti,clksel";
0915 reg = <0xa10>;
0916 #clock-cells = <2>;
0917 #address-cells = <0>;
0918
0919 sdrc_ick: clock-sdrc-ick {
0920 #clock-cells = <0>;
0921 compatible = "ti,wait-gate-clock";
0922 clock-output-names = "sdrc_ick";
0923 clocks = <&core_l3_ick>;
0924 ti,bit-shift = <1>;
0925 };
0926
0927 mmchs2_ick: clock-mmchs2-ick {
0928 #clock-cells = <0>;
0929 compatible = "ti,omap3-interface-clock";
0930 clock-output-names = "mmchs2_ick";
0931 clocks = <&core_l4_ick>;
0932 ti,bit-shift = <25>;
0933 };
0934
0935 mmchs1_ick: clock-mmchs1-ick {
0936 #clock-cells = <0>;
0937 compatible = "ti,omap3-interface-clock";
0938 clock-output-names = "mmchs1_ick";
0939 clocks = <&core_l4_ick>;
0940 ti,bit-shift = <24>;
0941 };
0942
0943 hdq_ick: clock-hdq-ick {
0944 #clock-cells = <0>;
0945 compatible = "ti,omap3-interface-clock";
0946 clock-output-names = "hdq_ick";
0947 clocks = <&core_l4_ick>;
0948 ti,bit-shift = <22>;
0949 };
0950
0951 mcspi4_ick: clock-mcspi4-ick {
0952 #clock-cells = <0>;
0953 compatible = "ti,omap3-interface-clock";
0954 clock-output-names = "mcspi4_ick";
0955 clocks = <&core_l4_ick>;
0956 ti,bit-shift = <21>;
0957 };
0958
0959 mcspi3_ick: clock-mcspi3-ick {
0960 #clock-cells = <0>;
0961 compatible = "ti,omap3-interface-clock";
0962 clock-output-names = "mcspi3_ick";
0963 clocks = <&core_l4_ick>;
0964 ti,bit-shift = <20>;
0965 };
0966
0967 mcspi2_ick: clock-mcspi2-ick {
0968 #clock-cells = <0>;
0969 compatible = "ti,omap3-interface-clock";
0970 clock-output-names = "mcspi2_ick";
0971 clocks = <&core_l4_ick>;
0972 ti,bit-shift = <19>;
0973 };
0974
0975 mcspi1_ick: clock-mcspi1-ick {
0976 #clock-cells = <0>;
0977 compatible = "ti,omap3-interface-clock";
0978 clock-output-names = "mcspi1_ick";
0979 clocks = <&core_l4_ick>;
0980 ti,bit-shift = <18>;
0981 };
0982
0983 i2c3_ick: clock-i2c3-ick {
0984 #clock-cells = <0>;
0985 compatible = "ti,omap3-interface-clock";
0986 clock-output-names = "i2c3_ick";
0987 clocks = <&core_l4_ick>;
0988 ti,bit-shift = <17>;
0989 };
0990
0991 i2c2_ick: clock-i2c2-ick {
0992 #clock-cells = <0>;
0993 compatible = "ti,omap3-interface-clock";
0994 clock-output-names = "i2c2_ick";
0995 clocks = <&core_l4_ick>;
0996 ti,bit-shift = <16>;
0997 };
0998
0999 i2c1_ick: clock-i2c1-ick {
1000 #clock-cells = <0>;
1001 compatible = "ti,omap3-interface-clock";
1002 clock-output-names = "i2c1_ick";
1003 clocks = <&core_l4_ick>;
1004 ti,bit-shift = <15>;
1005 };
1006
1007 uart2_ick: clock-uart2-ick {
1008 #clock-cells = <0>;
1009 compatible = "ti,omap3-interface-clock";
1010 clock-output-names = "uart2_ick";
1011 clocks = <&core_l4_ick>;
1012 ti,bit-shift = <14>;
1013 };
1014
1015 uart1_ick: clock-uart1-ick {
1016 #clock-cells = <0>;
1017 compatible = "ti,omap3-interface-clock";
1018 clock-output-names = "uart1_ick";
1019 clocks = <&core_l4_ick>;
1020 ti,bit-shift = <13>;
1021 };
1022
1023 gpt11_ick: clock-gpt11-ick {
1024 #clock-cells = <0>;
1025 compatible = "ti,omap3-interface-clock";
1026 clock-output-names = "gpt11_ick";
1027 clocks = <&core_l4_ick>;
1028 ti,bit-shift = <12>;
1029 };
1030
1031 gpt10_ick: clock-gpt10-ick {
1032 #clock-cells = <0>;
1033 compatible = "ti,omap3-interface-clock";
1034 clock-output-names = "gpt10_ick";
1035 clocks = <&core_l4_ick>;
1036 ti,bit-shift = <11>;
1037 };
1038
1039 mcbsp5_ick: clock-mcbsp5-ick {
1040 #clock-cells = <0>;
1041 compatible = "ti,omap3-interface-clock";
1042 clock-output-names = "mcbsp5_ick";
1043 clocks = <&core_l4_ick>;
1044 ti,bit-shift = <10>;
1045 };
1046
1047 mcbsp1_ick: clock-mcbsp1-ick {
1048 #clock-cells = <0>;
1049 compatible = "ti,omap3-interface-clock";
1050 clock-output-names = "mcbsp1_ick";
1051 clocks = <&core_l4_ick>;
1052 ti,bit-shift = <9>;
1053 };
1054
1055 omapctrl_ick: clock-omapctrl-ick {
1056 #clock-cells = <0>;
1057 compatible = "ti,omap3-interface-clock";
1058 clock-output-names = "omapctrl_ick";
1059 clocks = <&core_l4_ick>;
1060 ti,bit-shift = <6>;
1061 };
1062
1063 aes2_ick: clock-aes2-ick {
1064 #clock-cells = <0>;
1065 compatible = "ti,omap3-interface-clock";
1066 clock-output-names = "aes2_ick";
1067 clocks = <&core_l4_ick>;
1068 ti,bit-shift = <28>;
1069 };
1070
1071 sha12_ick: clock-sha12-ick {
1072 #clock-cells = <0>;
1073 compatible = "ti,omap3-interface-clock";
1074 clock-output-names = "sha12_ick";
1075 clocks = <&core_l4_ick>;
1076 ti,bit-shift = <27>;
1077 };
1078 };
1079
1080 gpmc_fck: gpmc_fck {
1081 #clock-cells = <0>;
1082 compatible = "fixed-factor-clock";
1083 clocks = <&core_l3_ick>;
1084 clock-mult = <1>;
1085 clock-div = <1>;
1086 };
1087
1088 core_l4_ick: core_l4_ick {
1089 #clock-cells = <0>;
1090 compatible = "fixed-factor-clock";
1091 clocks = <&l4_ick>;
1092 clock-mult = <1>;
1093 clock-div = <1>;
1094 };
1095
1096 /* CM_FCLKEN_DSS */
1097 clock@e00 {
1098 compatible = "ti,clksel";
1099 reg = <0xe00>;
1100 #clock-cells = <2>;
1101 #address-cells = <0>;
1102
1103 dss_tv_fck: clock-dss-tv-fck {
1104 #clock-cells = <0>;
1105 compatible = "ti,gate-clock";
1106 clock-output-names = "dss_tv_fck";
1107 clocks = <&omap_54m_fck>;
1108 ti,bit-shift = <2>;
1109 };
1110
1111 dss_96m_fck: clock-dss-96m-fck {
1112 #clock-cells = <0>;
1113 compatible = "ti,gate-clock";
1114 clock-output-names = "dss_96m_fck";
1115 clocks = <&omap_96m_fck>;
1116 ti,bit-shift = <2>;
1117 };
1118
1119 dss2_alwon_fck: clock-dss2-alwon-fck {
1120 #clock-cells = <0>;
1121 compatible = "ti,gate-clock";
1122 clock-output-names = "dss2_alwon_fck";
1123 clocks = <&sys_ck>;
1124 ti,bit-shift = <1>;
1125 };
1126 };
1127
1128 dummy_ck: dummy_ck {
1129 #clock-cells = <0>;
1130 compatible = "fixed-clock";
1131 clock-frequency = <0>;
1132 };
1133
1134 /* CM_FCLKEN_WKUP */
1135 clock@c00 {
1136 compatible = "ti,clksel";
1137 reg = <0xc00>;
1138 #clock-cells = <2>;
1139 #address-cells = <0>;
1140
1141 gpt1_gate_fck: clock-gpt1-gate-fck {
1142 #clock-cells = <0>;
1143 compatible = "ti,composite-gate-clock";
1144 clock-output-names = "gpt1_gate_fck";
1145 clocks = <&sys_ck>;
1146 ti,bit-shift = <0>;
1147 };
1148
1149 gpio1_dbck: clock-gpio1-dbck {
1150 #clock-cells = <0>;
1151 compatible = "ti,gate-clock";
1152 clock-output-names = "gpio1_dbck";
1153 clocks = <&wkup_32k_fck>;
1154 ti,bit-shift = <3>;
1155 };
1156
1157 wdt2_fck: clock-wdt2-fck {
1158 #clock-cells = <0>;
1159 compatible = "ti,wait-gate-clock";
1160 clock-output-names = "wdt2_fck";
1161 clocks = <&wkup_32k_fck>;
1162 ti,bit-shift = <5>;
1163 };
1164 };
1165
1166 gpt1_fck: gpt1_fck {
1167 #clock-cells = <0>;
1168 compatible = "ti,composite-clock";
1169 clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
1170 };
1171
1172 wkup_32k_fck: wkup_32k_fck {
1173 #clock-cells = <0>;
1174 compatible = "fixed-factor-clock";
1175 clocks = <&omap_32k_fck>;
1176 clock-mult = <1>;
1177 clock-div = <1>;
1178 };
1179
1180 /* CM_ICLKEN_WKUP */
1181 clock@c10 {
1182 compatible = "ti,clksel";
1183 reg = <0xc10>;
1184 #clock-cells = <2>;
1185 #address-cells = <0>;
1186
1187 wdt2_ick: clock-wdt2-ick {
1188 #clock-cells = <0>;
1189 compatible = "ti,omap3-interface-clock";
1190 clock-output-names = "wdt2_ick";
1191 clocks = <&wkup_l4_ick>;
1192 ti,bit-shift = <5>;
1193 };
1194
1195 wdt1_ick: clock-wdt1-ick {
1196 #clock-cells = <0>;
1197 compatible = "ti,omap3-interface-clock";
1198 clock-output-names = "wdt1_ick";
1199 clocks = <&wkup_l4_ick>;
1200 ti,bit-shift = <4>;
1201 };
1202
1203 gpio1_ick: clock-gpio1-ick {
1204 #clock-cells = <0>;
1205 compatible = "ti,omap3-interface-clock";
1206 clock-output-names = "gpio1_ick";
1207 clocks = <&wkup_l4_ick>;
1208 ti,bit-shift = <3>;
1209 };
1210
1211 omap_32ksync_ick: clock-omap-32ksync-ick {
1212 #clock-cells = <0>;
1213 compatible = "ti,omap3-interface-clock";
1214 clock-output-names = "omap_32ksync_ick";
1215 clocks = <&wkup_l4_ick>;
1216 ti,bit-shift = <2>;
1217 };
1218
1219 gpt12_ick: clock-gpt12-ick {
1220 #clock-cells = <0>;
1221 compatible = "ti,omap3-interface-clock";
1222 clock-output-names = "gpt12_ick";
1223 clocks = <&wkup_l4_ick>;
1224 ti,bit-shift = <1>;
1225 };
1226
1227 gpt1_ick: clock-gpt1-ick {
1228 #clock-cells = <0>;
1229 compatible = "ti,omap3-interface-clock";
1230 clock-output-names = "gpt1_ick";
1231 clocks = <&wkup_l4_ick>;
1232 ti,bit-shift = <0>;
1233 };
1234 };
1235
1236 per_96m_fck: per_96m_fck {
1237 #clock-cells = <0>;
1238 compatible = "fixed-factor-clock";
1239 clocks = <&omap_96m_alwon_fck>;
1240 clock-mult = <1>;
1241 clock-div = <1>;
1242 };
1243
1244 per_48m_fck: per_48m_fck {
1245 #clock-cells = <0>;
1246 compatible = "fixed-factor-clock";
1247 clocks = <&omap_48m_fck>;
1248 clock-mult = <1>;
1249 clock-div = <1>;
1250 };
1251
1252 /* CM_FCLKEN_PER */
1253 clock@1000 {
1254 compatible = "ti,clksel";
1255 reg = <0x1000>;
1256 #clock-cells = <2>;
1257 #address-cells = <0>;
1258
1259 uart3_fck: clock-uart3-fck {
1260 #clock-cells = <0>;
1261 compatible = "ti,wait-gate-clock";
1262 clock-output-names = "uart3_fck";
1263 clocks = <&per_48m_fck>;
1264 ti,bit-shift = <11>;
1265 };
1266
1267 gpt2_gate_fck: clock-gpt2-gate-fck {
1268 #clock-cells = <0>;
1269 compatible = "ti,composite-gate-clock";
1270 clock-output-names = "gpt2_gate_fck";
1271 clocks = <&sys_ck>;
1272 ti,bit-shift = <3>;
1273 };
1274
1275 gpt3_gate_fck: clock-gpt3-gate-fck {
1276 #clock-cells = <0>;
1277 compatible = "ti,composite-gate-clock";
1278 clock-output-names = "gpt3_gate_fck";
1279 clocks = <&sys_ck>;
1280 ti,bit-shift = <4>;
1281 };
1282
1283 gpt4_gate_fck: clock-gpt4-gate-fck {
1284 #clock-cells = <0>;
1285 compatible = "ti,composite-gate-clock";
1286 clock-output-names = "gpt4_gate_fck";
1287 clocks = <&sys_ck>;
1288 ti,bit-shift = <5>;
1289 };
1290
1291 gpt5_gate_fck: clock-gpt5-gate-fck {
1292 #clock-cells = <0>;
1293 compatible = "ti,composite-gate-clock";
1294 clock-output-names = "gpt5_gate_fck";
1295 clocks = <&sys_ck>;
1296 ti,bit-shift = <6>;
1297 };
1298
1299 gpt6_gate_fck: clock-gpt6-gate-fck {
1300 #clock-cells = <0>;
1301 compatible = "ti,composite-gate-clock";
1302 clock-output-names = "gpt6_gate_fck";
1303 clocks = <&sys_ck>;
1304 ti,bit-shift = <7>;
1305 };
1306
1307 gpt7_gate_fck: clock-gpt7-gate-fck {
1308 #clock-cells = <0>;
1309 compatible = "ti,composite-gate-clock";
1310 clock-output-names = "gpt7_gate_fck";
1311 clocks = <&sys_ck>;
1312 ti,bit-shift = <8>;
1313 };
1314
1315 gpt8_gate_fck: clock-gpt8-gate-fck {
1316 #clock-cells = <0>;
1317 compatible = "ti,composite-gate-clock";
1318 clock-output-names = "gpt8_gate_fck";
1319 clocks = <&sys_ck>;
1320 ti,bit-shift = <9>;
1321 };
1322
1323 gpt9_gate_fck: clock-gpt9-gate-fck {
1324 #clock-cells = <0>;
1325 compatible = "ti,composite-gate-clock";
1326 clock-output-names = "gpt9_gate_fck";
1327 clocks = <&sys_ck>;
1328 ti,bit-shift = <10>;
1329 };
1330
1331 gpio6_dbck: clock-gpio6-dbck {
1332 #clock-cells = <0>;
1333 compatible = "ti,gate-clock";
1334 clock-output-names = "gpio6_dbck";
1335 clocks = <&per_32k_alwon_fck>;
1336 ti,bit-shift = <17>;
1337 };
1338
1339 gpio5_dbck: clock-gpio5-dbck {
1340 #clock-cells = <0>;
1341 compatible = "ti,gate-clock";
1342 clock-output-names = "gpio5_dbck";
1343 clocks = <&per_32k_alwon_fck>;
1344 ti,bit-shift = <16>;
1345 };
1346
1347 gpio4_dbck: clock-gpio4-dbck {
1348 #clock-cells = <0>;
1349 compatible = "ti,gate-clock";
1350 clock-output-names = "gpio4_dbck";
1351 clocks = <&per_32k_alwon_fck>;
1352 ti,bit-shift = <15>;
1353 };
1354
1355 gpio3_dbck: clock-gpio3-dbck {
1356 #clock-cells = <0>;
1357 compatible = "ti,gate-clock";
1358 clock-output-names = "gpio3_dbck";
1359 clocks = <&per_32k_alwon_fck>;
1360 ti,bit-shift = <14>;
1361 };
1362
1363 gpio2_dbck: clock-gpio2-dbck {
1364 #clock-cells = <0>;
1365 compatible = "ti,gate-clock";
1366 clock-output-names = "gpio2_dbck";
1367 clocks = <&per_32k_alwon_fck>;
1368 ti,bit-shift = <13>;
1369 };
1370
1371 wdt3_fck: clock-wdt3-fck {
1372 #clock-cells = <0>;
1373 compatible = "ti,wait-gate-clock";
1374 clock-output-names = "wdt3_fck";
1375 clocks = <&per_32k_alwon_fck>;
1376 ti,bit-shift = <12>;
1377 };
1378
1379 mcbsp2_gate_fck: clock-mcbsp2-gate-fck {
1380 #clock-cells = <0>;
1381 compatible = "ti,composite-gate-clock";
1382 clock-output-names = "mcbsp2_gate_fck";
1383 clocks = <&mcbsp_clks>;
1384 ti,bit-shift = <0>;
1385 };
1386
1387 mcbsp3_gate_fck: clock-mcbsp3-gate-fck {
1388 #clock-cells = <0>;
1389 compatible = "ti,composite-gate-clock";
1390 clock-output-names = "mcbsp3_gate_fck";
1391 clocks = <&mcbsp_clks>;
1392 ti,bit-shift = <1>;
1393 };
1394
1395 mcbsp4_gate_fck: clock-mcbsp4-gate-fck {
1396 #clock-cells = <0>;
1397 compatible = "ti,composite-gate-clock";
1398 clock-output-names = "mcbsp4_gate_fck";
1399 clocks = <&mcbsp_clks>;
1400 ti,bit-shift = <2>;
1401 };
1402 };
1403
1404 /* CM_CLKSEL_PER */
1405 clock@1040 {
1406 compatible = "ti,clksel";
1407 reg = <0x1040>;
1408 #clock-cells = <2>;
1409 #address-cells = <0>;
1410
1411 gpt2_mux_fck: clock-gpt2-mux-fck {
1412 #clock-cells = <0>;
1413 compatible = "ti,composite-mux-clock";
1414 clock-output-names = "gpt2_mux_fck";
1415 clocks = <&omap_32k_fck>, <&sys_ck>;
1416 };
1417
1418 gpt3_mux_fck: clock-gpt3-mux-fck {
1419 #clock-cells = <0>;
1420 compatible = "ti,composite-mux-clock";
1421 clock-output-names = "gpt3_mux_fck";
1422 clocks = <&omap_32k_fck>, <&sys_ck>;
1423 ti,bit-shift = <1>;
1424 };
1425
1426 gpt4_mux_fck: clock-gpt4-mux-fck {
1427 #clock-cells = <0>;
1428 compatible = "ti,composite-mux-clock";
1429 clock-output-names = "gpt4_mux_fck";
1430 clocks = <&omap_32k_fck>, <&sys_ck>;
1431 ti,bit-shift = <2>;
1432 };
1433
1434 gpt5_mux_fck: clock-gpt5-mux-fck {
1435 #clock-cells = <0>;
1436 compatible = "ti,composite-mux-clock";
1437 clock-output-names = "gpt5_mux_fck";
1438 clocks = <&omap_32k_fck>, <&sys_ck>;
1439 ti,bit-shift = <3>;
1440 };
1441
1442 gpt6_mux_fck: clock-gpt6-mux-fck {
1443 #clock-cells = <0>;
1444 compatible = "ti,composite-mux-clock";
1445 clock-output-names = "gpt6_mux_fck";
1446 clocks = <&omap_32k_fck>, <&sys_ck>;
1447 ti,bit-shift = <4>;
1448 };
1449
1450 gpt7_mux_fck: clock-gpt7-mux-fck {
1451 #clock-cells = <0>;
1452 compatible = "ti,composite-mux-clock";
1453 clock-output-names = "gpt7_mux_fck";
1454 clocks = <&omap_32k_fck>, <&sys_ck>;
1455 ti,bit-shift = <5>;
1456 };
1457
1458 gpt8_mux_fck: clock-gpt8-mux-fck {
1459 #clock-cells = <0>;
1460 compatible = "ti,composite-mux-clock";
1461 clock-output-names = "gpt8_mux_fck";
1462 clocks = <&omap_32k_fck>, <&sys_ck>;
1463 ti,bit-shift = <6>;
1464 };
1465
1466 gpt9_mux_fck: clock-gpt9-mux-fck {
1467 #clock-cells = <0>;
1468 compatible = "ti,composite-mux-clock";
1469 clock-output-names = "gpt9_mux_fck";
1470 clocks = <&omap_32k_fck>, <&sys_ck>;
1471 ti,bit-shift = <7>;
1472 };
1473 };
1474
1475 gpt2_fck: gpt2_fck {
1476 #clock-cells = <0>;
1477 compatible = "ti,composite-clock";
1478 clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
1479 };
1480
1481 gpt3_fck: gpt3_fck {
1482 #clock-cells = <0>;
1483 compatible = "ti,composite-clock";
1484 clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
1485 };
1486
1487 gpt4_fck: gpt4_fck {
1488 #clock-cells = <0>;
1489 compatible = "ti,composite-clock";
1490 clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
1491 };
1492
1493 gpt5_fck: gpt5_fck {
1494 #clock-cells = <0>;
1495 compatible = "ti,composite-clock";
1496 clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
1497 };
1498
1499 gpt6_fck: gpt6_fck {
1500 #clock-cells = <0>;
1501 compatible = "ti,composite-clock";
1502 clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
1503 };
1504
1505 gpt7_fck: gpt7_fck {
1506 #clock-cells = <0>;
1507 compatible = "ti,composite-clock";
1508 clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
1509 };
1510
1511 gpt8_fck: gpt8_fck {
1512 #clock-cells = <0>;
1513 compatible = "ti,composite-clock";
1514 clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
1515 };
1516
1517 gpt9_fck: gpt9_fck {
1518 #clock-cells = <0>;
1519 compatible = "ti,composite-clock";
1520 clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
1521 };
1522
1523 per_32k_alwon_fck: per_32k_alwon_fck {
1524 #clock-cells = <0>;
1525 compatible = "fixed-factor-clock";
1526 clocks = <&omap_32k_fck>;
1527 clock-mult = <1>;
1528 clock-div = <1>;
1529 };
1530
1531 per_l4_ick: per_l4_ick {
1532 #clock-cells = <0>;
1533 compatible = "fixed-factor-clock";
1534 clocks = <&l4_ick>;
1535 clock-mult = <1>;
1536 clock-div = <1>;
1537 };
1538
1539 /* CM_ICLKEN_PER */
1540 clock@1010 {
1541 compatible = "ti,clksel";
1542 reg = <0x1010>;
1543 #clock-cells = <2>;
1544 #address-cells = <0>;
1545
1546 gpio6_ick: clock-gpio6-ick {
1547 #clock-cells = <0>;
1548 compatible = "ti,omap3-interface-clock";
1549 clock-output-names = "gpio6_ick";
1550 clocks = <&per_l4_ick>;
1551 ti,bit-shift = <17>;
1552 };
1553
1554 gpio5_ick: clock-gpio5-ick {
1555 #clock-cells = <0>;
1556 compatible = "ti,omap3-interface-clock";
1557 clock-output-names = "gpio5_ick";
1558 clocks = <&per_l4_ick>;
1559 ti,bit-shift = <16>;
1560 };
1561
1562 gpio4_ick: clock-gpio4-ick {
1563 #clock-cells = <0>;
1564 compatible = "ti,omap3-interface-clock";
1565 clock-output-names = "gpio4_ick";
1566 clocks = <&per_l4_ick>;
1567 ti,bit-shift = <15>;
1568 };
1569
1570 gpio3_ick: clock-gpio3-ick {
1571 #clock-cells = <0>;
1572 compatible = "ti,omap3-interface-clock";
1573 clock-output-names = "gpio3_ick";
1574 clocks = <&per_l4_ick>;
1575 ti,bit-shift = <14>;
1576 };
1577
1578 gpio2_ick: clock-gpio2-ick {
1579 #clock-cells = <0>;
1580 compatible = "ti,omap3-interface-clock";
1581 clock-output-names = "gpio2_ick";
1582 clocks = <&per_l4_ick>;
1583 ti,bit-shift = <13>;
1584 };
1585
1586 wdt3_ick: clock-wdt3-ick {
1587 #clock-cells = <0>;
1588 compatible = "ti,omap3-interface-clock";
1589 clock-output-names = "wdt3_ick";
1590 clocks = <&per_l4_ick>;
1591 ti,bit-shift = <12>;
1592 };
1593
1594 uart3_ick: clock-uart3-ick {
1595 #clock-cells = <0>;
1596 compatible = "ti,omap3-interface-clock";
1597 clock-output-names = "uart3_ick";
1598 clocks = <&per_l4_ick>;
1599 ti,bit-shift = <11>;
1600 };
1601
1602 uart4_ick: clock-uart4-ick {
1603 #clock-cells = <0>;
1604 compatible = "ti,omap3-interface-clock";
1605 clock-output-names = "uart4_ick";
1606 clocks = <&per_l4_ick>;
1607 ti,bit-shift = <18>;
1608 };
1609
1610 gpt9_ick: clock-gpt9-ick {
1611 #clock-cells = <0>;
1612 compatible = "ti,omap3-interface-clock";
1613 clock-output-names = "gpt9_ick";
1614 clocks = <&per_l4_ick>;
1615 ti,bit-shift = <10>;
1616 };
1617
1618 gpt8_ick: clock-gpt8-ick {
1619 #clock-cells = <0>;
1620 compatible = "ti,omap3-interface-clock";
1621 clock-output-names = "gpt8_ick";
1622 clocks = <&per_l4_ick>;
1623 ti,bit-shift = <9>;
1624 };
1625
1626 gpt7_ick: clock-gpt7-ick {
1627 #clock-cells = <0>;
1628 compatible = "ti,omap3-interface-clock";
1629 clock-output-names = "gpt7_ick";
1630 clocks = <&per_l4_ick>;
1631 ti,bit-shift = <8>;
1632 };
1633
1634 gpt6_ick: clock-gpt6-ick {
1635 #clock-cells = <0>;
1636 compatible = "ti,omap3-interface-clock";
1637 clock-output-names = "gpt6_ick";
1638 clocks = <&per_l4_ick>;
1639 ti,bit-shift = <7>;
1640 };
1641
1642 gpt5_ick: clock-gpt5-ick {
1643 #clock-cells = <0>;
1644 compatible = "ti,omap3-interface-clock";
1645 clock-output-names = "gpt5_ick";
1646 clocks = <&per_l4_ick>;
1647 ti,bit-shift = <6>;
1648 };
1649
1650 gpt4_ick: clock-gpt4-ick {
1651 #clock-cells = <0>;
1652 compatible = "ti,omap3-interface-clock";
1653 clock-output-names = "gpt4_ick";
1654 clocks = <&per_l4_ick>;
1655 ti,bit-shift = <5>;
1656 };
1657
1658 gpt3_ick: clock-gpt3-ick {
1659 #clock-cells = <0>;
1660 compatible = "ti,omap3-interface-clock";
1661 clock-output-names = "gpt3_ick";
1662 clocks = <&per_l4_ick>;
1663 ti,bit-shift = <4>;
1664 };
1665
1666 gpt2_ick: clock-gpt2-ick {
1667 #clock-cells = <0>;
1668 compatible = "ti,omap3-interface-clock";
1669 clock-output-names = "gpt2_ick";
1670 clocks = <&per_l4_ick>;
1671 ti,bit-shift = <3>;
1672 };
1673
1674 mcbsp2_ick: clock-mcbsp2-ick {
1675 #clock-cells = <0>;
1676 compatible = "ti,omap3-interface-clock";
1677 clock-output-names = "mcbsp2_ick";
1678 clocks = <&per_l4_ick>;
1679 ti,bit-shift = <0>;
1680 };
1681
1682 mcbsp3_ick: clock-mcbsp3-ick {
1683 #clock-cells = <0>;
1684 compatible = "ti,omap3-interface-clock";
1685 clock-output-names = "mcbsp3_ick";
1686 clocks = <&per_l4_ick>;
1687 ti,bit-shift = <1>;
1688 };
1689
1690 mcbsp4_ick: clock-mcbsp4-ick {
1691 #clock-cells = <0>;
1692 compatible = "ti,omap3-interface-clock";
1693 clock-output-names = "mcbsp4_ick";
1694 clocks = <&per_l4_ick>;
1695 ti,bit-shift = <2>;
1696 };
1697 };
1698
1699 emu_src_ck: emu_src_ck {
1700 #clock-cells = <0>;
1701 compatible = "ti,clkdm-gate-clock";
1702 clocks = <&emu_src_mux_ck>;
1703 };
1704
1705 secure_32k_fck: secure_32k_fck {
1706 #clock-cells = <0>;
1707 compatible = "fixed-clock";
1708 clock-frequency = <32768>;
1709 };
1710
1711 gpt12_fck: gpt12_fck {
1712 #clock-cells = <0>;
1713 compatible = "fixed-factor-clock";
1714 clocks = <&secure_32k_fck>;
1715 clock-mult = <1>;
1716 clock-div = <1>;
1717 };
1718
1719 wdt1_fck: wdt1_fck {
1720 #clock-cells = <0>;
1721 compatible = "fixed-factor-clock";
1722 clocks = <&secure_32k_fck>;
1723 clock-mult = <1>;
1724 clock-div = <1>;
1725 };
1726 };
1727
1728 &cm_clockdomains {
1729 core_l3_clkdm: core_l3_clkdm {
1730 compatible = "ti,clockdomain";
1731 clocks = <&sdrc_ick>;
1732 };
1733
1734 dpll3_clkdm: dpll3_clkdm {
1735 compatible = "ti,clockdomain";
1736 clocks = <&dpll3_ck>;
1737 };
1738
1739 dpll1_clkdm: dpll1_clkdm {
1740 compatible = "ti,clockdomain";
1741 clocks = <&dpll1_ck>;
1742 };
1743
1744 per_clkdm: per_clkdm {
1745 compatible = "ti,clockdomain";
1746 clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
1747 <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
1748 <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
1749 <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
1750 <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
1751 <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
1752 <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
1753 <&mcbsp4_ick>;
1754 };
1755
1756 emu_clkdm: emu_clkdm {
1757 compatible = "ti,clockdomain";
1758 clocks = <&emu_src_ck>;
1759 };
1760
1761 dpll4_clkdm: dpll4_clkdm {
1762 compatible = "ti,clockdomain";
1763 clocks = <&dpll4_ck>;
1764 };
1765
1766 wkup_clkdm: wkup_clkdm {
1767 compatible = "ti,clockdomain";
1768 clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
1769 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
1770 <&gpt1_ick>;
1771 };
1772
1773 dss_clkdm: dss_clkdm {
1774 compatible = "ti,clockdomain";
1775 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>;
1776 };
1777
1778 core_l4_clkdm: core_l4_clkdm {
1779 compatible = "ti,clockdomain";
1780 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
1781 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
1782 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
1783 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
1784 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
1785 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
1786 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
1787 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
1788 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>;
1789 };
1790 };
