0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for OMAP3 SoC
0004 *
0005 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
0006 */
0007
0008 #include <dt-bindings/bus/ti-sysc.h>
0009 #include <dt-bindings/media/omap3-isp.h>
0010
0011 #include "omap3.dtsi"
0012
0013 / {
0014 aliases {
0015 serial3 = &uart4;
0016 };
0017
0018 cpus {
0019 /* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */
0020 cpu: cpu@0 {
0021 operating-points-v2 = <&cpu0_opp_table>;
0022
0023 vbb-supply = <&abb_mpu_iva>;
0024 clock-latency = <300000>; /* From omap-cpufreq driver */
0025 #cooling-cells = <2>;
0026 };
0027 };
0028
0029 cpu0_opp_table: opp-table {
0030 compatible = "operating-points-v2-ti-cpu";
0031 syscon = <&scm_conf>;
0032
0033 opp50-300000000 {
0034 opp-hz = /bits/ 64 <300000000>;
0035 /*
0036 * we currently only select the max voltage from table
0037 * Table 4-19 of the DM3730 Data sheet (SPRS685B)
0038 * Format is: cpu0-supply: <target min max>
0039 * vbb-supply: <target min max>
0040 */
0041 opp-microvolt = <1012500 1012500 1012500>,
0042 <1012500 1012500 1012500>;
0043 /*
0044 * first value is silicon revision bit mask
0045 * second one is "speed binned" bit mask
0046 */
0047 opp-supported-hw = <0xffffffff 3>;
0048 opp-suspend;
0049 };
0050
0051 opp100-600000000 {
0052 opp-hz = /bits/ 64 <600000000>;
0053 opp-microvolt = <1200000 1200000 1200000>,
0054 <1200000 1200000 1200000>;
0055 opp-supported-hw = <0xffffffff 3>;
0056 };
0057
0058 opp130-800000000 {
0059 opp-hz = /bits/ 64 <800000000>;
0060 opp-microvolt = <1325000 1325000 1325000>,
0061 <1325000 1325000 1325000>;
0062 opp-supported-hw = <0xffffffff 3>;
0063 };
0064
0065 opp1g-1000000000 {
0066 opp-hz = /bits/ 64 <1000000000>;
0067 opp-microvolt = <1375000 1375000 1375000>,
0068 <1375000 1375000 1375000>;
0069 /* only on am/dm37x with speed-binned bit set */
0070 opp-supported-hw = <0xffffffff 2>;
0071 };
0072 };
0073
0074 opp_supply_mpu_iva: opp_supply {
0075 compatible = "ti,omap-opp-supply";
0076 ti,absolute-max-voltage-uv = <1375000>;
0077 };
0078
0079 ocp@68000000 {
0080 uart4: serial@49042000 {
0081 compatible = "ti,omap3-uart";
0082 reg = <0x49042000 0x400>;
0083 interrupts = <80>;
0084 dmas = <&sdma 81 &sdma 82>;
0085 dma-names = "tx", "rx";
0086 ti,hwmods = "uart4";
0087 clock-frequency = <48000000>;
0088 };
0089
0090 abb_mpu_iva: regulator-abb-mpu {
0091 compatible = "ti,abb-v1";
0092 regulator-name = "abb_mpu_iva";
0093 #address-cells = <0>;
0094 #size-cells = <0>;
0095 reg = <0x483072f0 0x8>, <0x48306818 0x4>;
0096 reg-names = "base-address", "int-address";
0097 ti,tranxdone-status-mask = <0x4000000>;
0098 clocks = <&sys_ck>;
0099 ti,settling-time = <30>;
0100 ti,clock-cycles = <8>;
0101 ti,abb_info = <
0102 /*uV ABB efuse rbb_m fbb_m vset_m*/
0103 1012500 0 0 0 0 0
0104 1200000 0 0 0 0 0
0105 1325000 0 0 0 0 0
0106 1375000 1 0 0 0 0
0107 >;
0108 };
0109
0110 omap3_pmx_core2: pinmux@480025a0 {
0111 compatible = "ti,omap3-padconf", "pinctrl-single";
0112 reg = <0x480025a0 0x5c>;
0113 #address-cells = <1>;
0114 #size-cells = <0>;
0115 #pinctrl-cells = <1>;
0116 #interrupt-cells = <1>;
0117 interrupt-controller;
0118 pinctrl-single,register-width = <16>;
0119 pinctrl-single,function-mask = <0xff1f>;
0120 };
0121
0122 isp: isp@480bc000 {
0123 compatible = "ti,omap3-isp";
0124 reg = <0x480bc000 0x12fc
0125 0x480bd800 0x0600>;
0126 interrupts = <24>;
0127 iommus = <&mmu_isp>;
0128 syscon = <&scm_conf 0x2f0>;
0129 ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
0130 #clock-cells = <1>;
0131 ports {
0132 #address-cells = <1>;
0133 #size-cells = <0>;
0134 };
0135 };
0136
0137 bandgap: bandgap@48002524 {
0138 reg = <0x48002524 0x4>;
0139 compatible = "ti,omap36xx-bandgap";
0140 #thermal-sensor-cells = <0>;
0141 };
0142
0143 target-module@480cb000 {
0144 compatible = "ti,sysc-omap3630-sr", "ti,sysc";
0145 ti,hwmods = "smartreflex_core";
0146 reg = <0x480cb038 0x4>;
0147 reg-names = "sysc";
0148 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
0149 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0150 <SYSC_IDLE_NO>,
0151 <SYSC_IDLE_SMART>;
0152 clocks = <&sr2_fck>;
0153 clock-names = "fck";
0154 #address-cells = <1>;
0155 #size-cells = <1>;
0156 ranges = <0 0x480cb000 0x001000>;
0157
0158 smartreflex_core: smartreflex@0 {
0159 compatible = "ti,omap3-smartreflex-core";
0160 reg = <0 0x400>;
0161 interrupts = <19>;
0162 };
0163 };
0164
0165 target-module@480c9000 {
0166 compatible = "ti,sysc-omap3630-sr", "ti,sysc";
0167 ti,hwmods = "smartreflex_mpu_iva";
0168 reg = <0x480c9038 0x4>;
0169 reg-names = "sysc";
0170 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
0171 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0172 <SYSC_IDLE_NO>,
0173 <SYSC_IDLE_SMART>;
0174 clocks = <&sr1_fck>;
0175 clock-names = "fck";
0176 #address-cells = <1>;
0177 #size-cells = <1>;
0178 ranges = <0 0x480c9000 0x001000>;
0179
0180
0181 smartreflex_mpu_iva: smartreflex@480c9000 {
0182 compatible = "ti,omap3-smartreflex-mpu-iva";
0183 reg = <0 0x400>;
0184 interrupts = <18>;
0185 };
0186 };
0187
0188 /*
0189 * Note that the sysconfig register layout is a subset of the
0190 * "ti,sysc-omap4" type register with just sidle and midle bits
0191 * available while omap34xx has "ti,sysc-omap2" type sysconfig.
0192 */
0193 sgx_module: target-module@50000000 {
0194 compatible = "ti,sysc-omap4", "ti,sysc";
0195 reg = <0x5000fe00 0x4>,
0196 <0x5000fe10 0x4>;
0197 reg-names = "rev", "sysc";
0198 ti,sysc-midle = <SYSC_IDLE_FORCE>,
0199 <SYSC_IDLE_NO>,
0200 <SYSC_IDLE_SMART>;
0201 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
0202 <SYSC_IDLE_NO>,
0203 <SYSC_IDLE_SMART>;
0204 clocks = <&sgx_fck>, <&sgx_ick>;
0205 clock-names = "fck", "ick";
0206 #address-cells = <1>;
0207 #size-cells = <1>;
0208 ranges = <0 0x50000000 0x2000000>;
0209
0210 /*
0211 * Closed source PowerVR driver, no child device
0212 * binding or driver in mainline
0213 */
0214 };
0215 };
0216
0217 thermal_zones: thermal-zones {
0218 #include "omap3-cpu-thermal.dtsi"
0219 };
0220 };
0221
0222 &sdma {
0223 compatible = "ti,omap3630-sdma", "ti,omap-sdma";
0224 };
0225
0226 /* OMAP3630 needs dss_96m_fck for VENC */
0227 &venc {
0228 clocks = <&dss_tv_fck>, <&dss_96m_fck>;
0229 clock-names = "fck", "tv_dac_clk";
0230 };
0231
0232 &ssi {
0233 status = "okay";
0234
0235 clocks = <&ssi_ssr_fck>,
0236 <&ssi_sst_fck>,
0237 <&ssi_ick>;
0238 clock-names = "ssi_ssr_fck",
0239 "ssi_sst_fck",
0240 "ssi_ick";
0241 };
0242
0243 /include/ "omap34xx-omap36xx-clocks.dtsi"
0244 /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
0245 /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
0246 /include/ "omap36xx-clocks.dtsi"
