0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for OMAP34xx/OMAP36xx clock data
0004 *
0005 * Copyright (C) 2013 Texas Instruments, Inc.
0006 */
0007 &cm_clocks {
0008 clock@a00 {
0009 compatible = "ti,clksel";
0010 reg = <0xa00>;
0011 #clock-cells = <2>;
0012 #address-cells = <0>;
0013
0014 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 {
0015 #clock-cells = <0>;
0016 compatible = "ti,composite-no-wait-gate-clock";
0017 clock-output-names = "ssi_ssr_gate_fck_3430es2";
0018 clocks = <&corex2_fck>;
0019 ti,bit-shift = <0>;
0020 };
0021 };
0022
0023 clock@a40 {
0024 compatible = "ti,clksel";
0025 reg = <0xa40>;
0026 #clock-cells = <2>;
0027 #address-cells = <0>;
0028
0029 ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 {
0030 #clock-cells = <0>;
0031 compatible = "ti,composite-divider-clock";
0032 clock-output-names = "ssi_ssr_div_fck_3430es2";
0033 clocks = <&corex2_fck>;
0034 ti,bit-shift = <8>;
0035 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
0036 };
0037 };
0038
0039 ssi_ssr_fck: ssi_ssr_fck_3430es2 {
0040 #clock-cells = <0>;
0041 compatible = "ti,composite-clock";
0042 clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
0043 };
0044
0045 ssi_sst_fck: ssi_sst_fck_3430es2 {
0046 #clock-cells = <0>;
0047 compatible = "fixed-factor-clock";
0048 clocks = <&ssi_ssr_fck>;
0049 clock-mult = <1>;
0050 clock-div = <2>;
0051 };
0052
0053 clock@a10 {
0054 compatible = "ti,clksel";
0055 reg = <0xa10>;
0056 #clock-cells = <2>;
0057 #address-cells = <0>;
0058
0059 hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2 {
0060 #clock-cells = <0>;
0061 compatible = "ti,omap3-hsotgusb-interface-clock";
0062 clock-output-names = "hsotgusb_ick_3430es2";
0063 clocks = <&core_l3_ick>;
0064 ti,bit-shift = <4>;
0065 };
0066
0067 ssi_ick: clock-ssi-ick-3430es2 {
0068 #clock-cells = <0>;
0069 compatible = "ti,omap3-ssi-interface-clock";
0070 clock-output-names = "ssi_ick_3430es2";
0071 clocks = <&ssi_l4_ick>;
0072 ti,bit-shift = <0>;
0073 };
0074 };
0075
0076 ssi_l4_ick: ssi_l4_ick {
0077 #clock-cells = <0>;
0078 compatible = "fixed-factor-clock";
0079 clocks = <&l4_ick>;
0080 clock-mult = <1>;
0081 clock-div = <1>;
0082 };
0083
0084 clock@c00 {
0085 compatible = "ti,clksel";
0086 reg = <0xc00>;
0087 #clock-cells = <2>;
0088 #address-cells = <0>;
0089
0090 usim_gate_fck: clock-usim-gate-fck {
0091 #clock-cells = <0>;
0092 compatible = "ti,composite-gate-clock";
0093 clock-output-names = "usim_gate_fck";
0094 clocks = <&omap_96m_fck>;
0095 ti,bit-shift = <9>;
0096 };
0097 };
0098
0099 sys_d2_ck: sys_d2_ck {
0100 #clock-cells = <0>;
0101 compatible = "fixed-factor-clock";
0102 clocks = <&sys_ck>;
0103 clock-mult = <1>;
0104 clock-div = <2>;
0105 };
0106
0107 omap_96m_d2_fck: omap_96m_d2_fck {
0108 #clock-cells = <0>;
0109 compatible = "fixed-factor-clock";
0110 clocks = <&omap_96m_fck>;
0111 clock-mult = <1>;
0112 clock-div = <2>;
0113 };
0114
0115 omap_96m_d4_fck: omap_96m_d4_fck {
0116 #clock-cells = <0>;
0117 compatible = "fixed-factor-clock";
0118 clocks = <&omap_96m_fck>;
0119 clock-mult = <1>;
0120 clock-div = <4>;
0121 };
0122
0123 omap_96m_d8_fck: omap_96m_d8_fck {
0124 #clock-cells = <0>;
0125 compatible = "fixed-factor-clock";
0126 clocks = <&omap_96m_fck>;
0127 clock-mult = <1>;
0128 clock-div = <8>;
0129 };
0130
0131 omap_96m_d10_fck: omap_96m_d10_fck {
0132 #clock-cells = <0>;
0133 compatible = "fixed-factor-clock";
0134 clocks = <&omap_96m_fck>;
0135 clock-mult = <1>;
0136 clock-div = <10>;
0137 };
0138
0139 dpll5_m2_d4_ck: dpll5_m2_d4_ck {
0140 #clock-cells = <0>;
0141 compatible = "fixed-factor-clock";
0142 clocks = <&dpll5_m2_ck>;
0143 clock-mult = <1>;
0144 clock-div = <4>;
0145 };
0146
0147 dpll5_m2_d8_ck: dpll5_m2_d8_ck {
0148 #clock-cells = <0>;
0149 compatible = "fixed-factor-clock";
0150 clocks = <&dpll5_m2_ck>;
0151 clock-mult = <1>;
0152 clock-div = <8>;
0153 };
0154
0155 dpll5_m2_d16_ck: dpll5_m2_d16_ck {
0156 #clock-cells = <0>;
0157 compatible = "fixed-factor-clock";
0158 clocks = <&dpll5_m2_ck>;
0159 clock-mult = <1>;
0160 clock-div = <16>;
0161 };
0162
0163 dpll5_m2_d20_ck: dpll5_m2_d20_ck {
0164 #clock-cells = <0>;
0165 compatible = "fixed-factor-clock";
0166 clocks = <&dpll5_m2_ck>;
0167 clock-mult = <1>;
0168 clock-div = <20>;
0169 };
0170
0171 clock@c40 {
0172 compatible = "ti,clksel";
0173 reg = <0xc40>;
0174 #clock-cells = <2>;
0175 #address-cells = <0>;
0176
0177 usim_mux_fck: clock-usim-mux-fck {
0178 #clock-cells = <0>;
0179 compatible = "ti,composite-mux-clock";
0180 clock-output-names = "usim_mux_fck";
0181 clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
0182 ti,bit-shift = <3>;
0183 ti,index-starts-at-one;
0184 };
0185 };
0186
0187 usim_fck: usim_fck {
0188 #clock-cells = <0>;
0189 compatible = "ti,composite-clock";
0190 clocks = <&usim_gate_fck>, <&usim_mux_fck>;
0191 };
0192
0193 clock@c10 {
0194 compatible = "ti,clksel";
0195 reg = <0xc10>;
0196 #clock-cells = <2>;
0197 #address-cells = <0>;
0198
0199 usim_ick: clock-usim-ick {
0200 #clock-cells = <0>;
0201 compatible = "ti,omap3-interface-clock";
0202 clock-output-names = "usim_ick";
0203 clocks = <&wkup_l4_ick>;
0204 ti,bit-shift = <9>;
0205 };
0206 };
0207 };
0208
0209 &cm_clockdomains {
0210 core_l3_clkdm: core_l3_clkdm {
0211 compatible = "ti,clockdomain";
0212 clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
0213 };
0214
0215 wkup_clkdm: wkup_clkdm {
0216 compatible = "ti,clockdomain";
0217 clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
0218 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
0219 <&gpt1_ick>, <&usim_ick>;
0220 };
0221
0222 core_l4_clkdm: core_l4_clkdm {
0223 compatible = "ti,clockdomain";
0224 clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
0225 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
0226 <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
0227 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
0228 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
0229 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
0230 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
0231 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
0232 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
0233 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
0234 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
0235 <&ssi_ick>;
0236 };
0237 };
