0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Device Tree Source for OMAP36xx clock data
0004 *
0005 * Copyright (C) 2013 Texas Instruments, Inc.
0006 */
0007 &cm_clocks {
0008 dpll4_ck: dpll4_ck@d00 {
0009 #clock-cells = <0>;
0010 compatible = "ti,omap3-dpll-per-j-type-clock";
0011 clocks = <&sys_ck>, <&sys_ck>;
0012 reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
0013 };
0014
0015 dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
0016 #clock-cells = <0>;
0017 compatible = "ti,hsdiv-gate-clock";
0018 clocks = <&dpll4_m5x2_mul_ck>;
0019 ti,bit-shift = <0x1e>;
0020 reg = <0x0d00>;
0021 ti,set-rate-parent;
0022 ti,set-bit-to-disable;
0023 };
0024
0025 dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
0026 #clock-cells = <0>;
0027 compatible = "ti,hsdiv-gate-clock";
0028 clocks = <&dpll4_m2x2_mul_ck>;
0029 ti,bit-shift = <0x1b>;
0030 reg = <0x0d00>;
0031 ti,set-bit-to-disable;
0032 };
0033
0034 dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
0035 #clock-cells = <0>;
0036 compatible = "ti,hsdiv-gate-clock";
0037 clocks = <&dpll3_m3x2_mul_ck>;
0038 ti,bit-shift = <0xc>;
0039 reg = <0x0d00>;
0040 ti,set-bit-to-disable;
0041 };
0042
0043 dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
0044 #clock-cells = <0>;
0045 compatible = "ti,hsdiv-gate-clock";
0046 clocks = <&dpll4_m3x2_mul_ck>;
0047 ti,bit-shift = <0x1c>;
0048 reg = <0x0d00>;
0049 ti,set-bit-to-disable;
0050 };
0051
0052 dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
0053 #clock-cells = <0>;
0054 compatible = "ti,hsdiv-gate-clock";
0055 clocks = <&dpll4_m6x2_mul_ck>;
0056 ti,bit-shift = <0x1f>;
0057 reg = <0x0d00>;
0058 ti,set-bit-to-disable;
0059 };
0060
0061 clock@1000 {
0062 compatible = "ti,clksel";
0063 reg = <0x1000>;
0064 #clock-cells = <2>;
0065 #address-cells = <0>;
0066
0067 uart4_fck: clock-uart4-fck {
0068 #clock-cells = <0>;
0069 compatible = "ti,wait-gate-clock";
0070 clock-output-names = "uart4_fck";
0071 clocks = <&per_48m_fck>;
0072 ti,bit-shift = <18>;
0073 };
0074 };
0075 };
0076
0077 &dpll4_m2x2_mul_ck {
0078 clock-mult = <1>;
0079 };
0080
0081 &dpll4_m3x2_mul_ck {
0082 clock-mult = <1>;
0083 };
0084
0085 &dpll4_m4x2_mul_ck {
0086 ti,clock-mult = <1>;
0087 };
0088
0089 &dpll4_m5x2_mul_ck {
0090 ti,clock-mult = <1>;
0091 };
0092
0093 &dpll4_m6x2_mul_ck {
0094 clock-mult = <1>;
0095 };
0096
0097 &cm_clockdomains {
0098 dpll4_clkdm: dpll4_clkdm {
0099 compatible = "ti,clockdomain";
0100 clocks = <&dpll4_ck>;
0101 };
0102
0103 per_clkdm: per_clkdm {
0104 compatible = "ti,clockdomain";
0105 clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
0106 <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
0107 <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
0108 <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
0109 <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
0110 <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
0111 <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
0112 <&mcbsp4_ick>, <&uart4_fck>;
0113 };
0114 };
0115
0116 &dpll4_m4_ck {
0117 ti,max-div = <31>;
0118 };
